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19-4782; Rev 1; 3/99
ANUAL N KIT M LUATIO ATA SHEET EVA WS D FOLLO
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Features
o 12-Bit Resolution, 1/2LSB Linearity o +5V Single-Supply Operation o SPI/QSPI and MICROWIRE-Compatible 3-Wire Interface o Four Software-Selectable Input Ranges MAX1270: 0 to +10V, 0 to +5V, 10V, 5V MAX1271: 0 to VREF, 0 to VREF/2, VREF, VREF/2 o Eight Analog Input Channels o 110ksps Sampling Rate o 16.5V Overvoltage-Tolerant Input Multiplexer o Internal 4.096V or External Reference o Two Power-Down Modes o Internal or External Clock o 24-Pin Narrow DIP or 28-Pin SSOP Packages
General Description
The MAX1270/MAX1271 are multirange, 12-bit dataacquisition systems (DAS) that require only a single +5V supply for operation, yet accept signals at their analog inputs that may span above the power-supply rail and below ground. These systems provide eight analog input channels that are independently software programmable for a variety of ranges: 10V, 5V, 0 to +10V, 0 to +5V for the MAX1270; VREF, VREF/2, 0 to VREF, 0 to VREF/2 for the MAX1271. This range switching increases the effective dynamic range to 14 bits and provides the flexibility to interface 4-20mA, 12V, and 15V powered sensors directly to a single +5V system. In addition, these converters are fault protected to 16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, softwareselectable internal/external clock, 110ksps throughput rate, and internal 4.096V or external reference operation. The MAX1270/MAX1271 serial interface directly connects to SPITM/QSPITM and MICROWIRETM devices without external logic. A hardware shutdown input (SHDN) and two softwareprogrammable power-down modes, standby (STBYPD) or full power-down (FULLPD), are provided for low-current shutdown between conversions. In standby mode, the reference buffer remains active, eliminating start-up delays. The MAX1270/MAX1271 are available in 24-pin narrow DIP or space-saving 28-pin SSOP packages.
MAX1270/MAX1271
Typical Operating Circuit
+5V
0.1F
VDD SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
Applications
Industrial Control Systems Data-Acquisition Systems Robotics Automatic Testing Battery-Powered Instruments Medical Instruments
ANALOG INPUTS
MAX1270 MAX1271
MC68HCXX CS SCLK DIN DOUT SSTRB AGND I/O SCK MOSI MISO
REF REFADJ 4.7F 0.01F DGND
Ordering Information
PART TEMP. RANGE PIN-PACKAGE INL (LSB) 1/2 1 1/2 1
MAX1270ACNG 0C to +70C 24 Narrow Plastic DIP MAX1270BCNG 0C to +70C 24 Narrow Plastic DIP 0C to +70C 28 SSOP MAX1270ACAI MAX1270BCAI 0C to +70C 28 SSOP Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. 7-169
____________________________________________________________ Maxim Integrated Products
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V CH0-CH7 to AGND ......................................................... 16.5V REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V) SSTRB, DOUT to DGND.............................-0.3V to (VDD + 0.3V) SHDN, CS, DIN, SCLK to DGND..............................-0.3V to +6V Max Current into Any Pin ....................................................50mA Continuous Power Dissipation (TA = +70C) 24-Pin Narrow DIP (derate 13.33mW/C above +70C) ..1067mW 28-Pin SSOP (derate 9.52mW/C above +70C) ..........762mW Operating Temperature Ranges MAX127_C_ _ ......................................................0C to +70C MAX127_E_ _....................................................-40C to +85C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10sec) ............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5.0V 5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7F at REF; external clock, fCLK = 2.0MHz (50% duty cycle), 18 clock/conversion cycle, 110ksps; TA = TMIN to TMAX; unless otherwise noted. Typical values are TA = +25C.) PARAMETERS ACCURACY (Note 1) ACCURACY (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity INL DNL MAX127_A MAX127_B No missing codes over temperature Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching Unipolar Bipolar Unipolar Gain Error (Note 2) Bipolar Gain Error Temperature Coefficient (Note 2) MAX127_A MAX127_B MAX127_A MAX127_B 3 5 MAX127_A MAX127_B MAX127_A MAX127_B 0.1 0.3 7 10 7 10 ppm/C LSB 12 0.5 1.0 1 3 5 5 10 LSB LSB bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
Unipolar, external reference Bipolar, external reference
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 10Vp-p (MAX1270), or 4.096Vp-p (MAX1271), fSAMPLE = 110ksps) SPECIFICATIONS Signal-to-Noise + Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Aperture Delay Aperture Jitter 7-170 SINAD THD SFDR 50kHz (Note 3) DC, VIN = 16.5V External clock mode External clock mode Internal clock mode Up to the 5th harmonic 80 -86 -96 15 <50 10 70 -87 -78 dB dB dB dB dB ns ps ns
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5.0V 5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7F at REF; external clock, fCLK = 2.0MHz (50% duty cycle), 18 clock/conversion cycle, 110ksps; TA = TMIN to TMAX; unless otherwise noted. Typical values are TA = +25C.) PARAMETERS ANALOG INPUT INPUT Track/Hold Acquisition Time tACQ fCLK = 2.0MHz 10V or VREF range Small-Signal Bandwidth -3dB rolloff 5V or VREF/2 range 0 to 10V or 0 to VREF range 0 to 5V or 0 to VREF/2 range Unipolar (BIP = 0), Table 3 Input Voltage Range VIN Bipolar (BIP = 1), Table 3 MAX1270 MAX1271 MAX1270 MAX1271 Input Current IIN Bipolar MAX1271 Dynamic Resistance Input Capacitance INTERNAL REFERENCE INTERNAL REFERENCE REF Output Voltage REF Output Tempco Output Short Circuit Current Load Regulation (Note 5) Capacitive Bypass at REF Capacitive Bypass at REFADJ REFADJ Output Voltage REFADJ Adjustment Range Buffer Voltage Gain REFERENCEINPUT (Reference buffer disabled, reference input applied to REF) REFERENCE INPUT (Reference Input Voltage Range Input Current VREF = 4.18V Normal or STBYPD FULLPD 2.40 4.18 400 1 V A Figure 1 0 to 0.5mA output current 4.7 0.01 2.465 2.500 1.5 1.638 2.535 VREF TC VREF TA = +25C MAX1270_C/MAX1271_C MAX1270_E/MAX1271_E 4.076 4.096 15 30 30 10 4.116 V ppm/C mA mV F F V % V/V VIN/IIN Unipolar Bipolar (Note 4) MAX1270 10V range 5V range VREF range VREF/2 range MAX1270 MAX1271 RNG = 1 RNG = 0 RNG = 1 RNG = 0 RNG = 1 RNG = 0 RNG = 1 RNG = 0 0 to 10V range 0 to 5V range 0 0 0 0 -10 -5 -VREF -VREF/2 -10 -10 -10 -1200 -600 -1200 -600 21 16 40 0.1 5 2.5 2.5 1.25 10 5 VREF VREF/2 10 5 VREF VREF/2 720 360 10 720 360 10 10 k pF A V MHz 3 s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1270/MAX1271
Unipolar
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5.0V 5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7F at REF; external clock, fCLK = 2.0MHz (50% duty cycle), 18 clock/conversion cycle, 110ksps; TA = TMIN to TMAX; unless otherwise noted. Typical values are TA = +25C.) PARAMETERS Input Resistance REFADJ Threshold for Buffer Disable POWER REQUIREMENT POWER REQUIREMENT Supply Voltage VDD Normal Supply Current IDD Bipolar range Unipolar range 6 700 120 0.1 0.5 4.75 5.25 18 10 850 220 0.5 V mA A LSB SYMBOL VREF = 4.18V CONDITIONS Normal or STBYPD FULLPD MIN 10 4.18 VDD - 0.5 TYP MAX UNITS k M V
STBYPD power down mode (Note 6) FULLPD power down mode External reference = 4.096V Internal reference
Power-Supply Rejection Ratio (Note 7) TIMING External Clock Frequency Range Acquisition Phase Conversion Time Throughput Rate Bandgap Reference Start-Up Time (Note 9) Reference Buffer Settling Time
PSRR
fCLK External clock mode (Note 8) Internal clock mode, Figure 9 tCONV External clock mode (Note 8) Internal clock mode, Figure 9 External clock mode Internal clock mode Power-up To 0.1mV, REF bypass capacitor fully discharged VIH VIL VHYS IIN CIN VIN = 0 to VDD (Note 4) ISINK = 5mA ISINK = 16mA ISOURCE = 0.5mA CS = VDD CS = VDD (Note 4) CREF = 4.7F CREF = 33F
0.1 3 3 6 6 7.7
2.0
MHz s s ksps s
5 11 110 43 200 8
ms 60
DIGITAL INPUTS: DIN, SCLK, CS, SHDN INPUTS: DIN, SCLK, Input High Threshold Voltage Input Low Threshold Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS: DOUT, SSTRB OUTPUTS: DOUT, Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VOL VOH IL COUT 0.4 0.4 VDD - 0.5 -10 10 15 V V A pF 2.4 0.8 0.2 -10 10 15 V V V A pF
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
TIMING CHARACTERISTICS
(VDD = +4.75V to +5.25; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7F at REF; external clock, fCLK = 2MHz; TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) (Figures 2, 5, 7, 10) PARAMETERS DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low SCLK Fall to SSTRB CS to SSTRB Output Enable CS to SSTRB Output Disable SSTRB Rise to SCLK Rise (Note 4) SYMBOL tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tSSTRB tSDV tSTR tSCK CLOAD = 100pF CLOAD = 100pF External clock mode only CLOAD = 100pF External clock mode only Internal clock mode only 0 CLOAD = 100pF CLOAD = 100pF CLOAD = 100pF 100 0 200 200 200 200 200 20 CONDITIONS MIN 100 0 170 120 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX1270/MAX1271
Note 1: Accuracy specifications tested at VDD = +5.0V. Performance at power-supply tolerance limit is guaranteed by Power-Supply Rejection test. Note 2: External reference: VREF = 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2LSB. Note 3: Ground "on" channel; sine wave applied to all "off" channels. VIN = 5V (MAX1270), VIN = 4V (MAX1271). Note 4: Guaranteed by design, not production tested. Note 5: Use static external loads during conversion for specified accuracy. Note 6: Tested using internal reference. Note 7: PSRR measured at full scale. Tested for the 10V (MAX1270) and 4.096V (MAX1271) input ranges. Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6). Note 9: Not production tested. Provided for design guidance only.
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
Typical Operating Characteristics
(Typical Operating Circuit, VDD = +5V; external reference mode, VREF = +4.096V; 4.7F at REF; external clock, fCLK = 2MHz; 110ksps; TA = +25C; unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1270/1 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX1270/1 toc02
STANDBY SUPPLY CURRENT vs. TEMPERATURE
MAX1270/1 toc03
25
6.5
750 STANDBY SUPPLY CURRENT (A) 650 550 450 350 250 150 EXTERNAL REFERENCE INTERNAL REFERENCE
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
20
6.3
15
6.1
10
5.9
5
5.7
0 0 1 2 3 4 5 6 7 SUPPLY VOLTAGE (V)
5.5 -40 -15 10 35 60 85 TEMPERATURE (C)
50 -40 -15 10 35 60 85 TEMPERATURE (C)
MAX1270/1 toc05
MAX1270/1 toc04
FULL POWER-DOWN SUPPLY CURRENT (A)
BIPOLAR MODE
NORMALIZED REFERENCE VOLTAGE
0.30 0.25 0.20 0.15 0.10 0.05 0 -40 -15 10 35 60 UNIPOLAR MODE
130
EXTERNAL REFERENCE
1.000
110
0.999
90 INTERNAL REFERENCE
0.998
70
0.997
50 -40 -15 10 35 60 85 TEMPERATURE (C)
0.996 -40 -15 10 35 60 85 TEMPERATURE (C)
85
TEMPERATURE (C)
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB)
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE
MAX1270/1 toc07
INTEGRAL NONLINEARITY vs. DIGITAL CODE
MAX1270/1 toc08
FTT PLOT
fIN = 10kHz fSAMPLE = 110ksps
MAX1270/1 toc09
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -40 -15 10 35 60 UNIPOLAR MODE
0.15 INTEGRAL NONLINEARITY (LSB) 0.10 0.05 0 -0.05 -0.10 -0.15
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120
BIPOLAR MODE
85
0
819
1638
2457
3276
4095
0
10k
20k
30k
40k
50k
TEMPERATURE (C)
DIGITAL CODE
FREQUENCY (Hz)
7-174
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MAX1270/1 toc06
150
1.001
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB)
FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE
NORMALIZED REFERENCE VOLTAGE vs. TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE
0.35
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VDD = +5V; external reference mode, VREF = +4.096V; 4.7F at REF; external clock, fCLK = 2MHz; 110ksps; TA = +25C; unless otherwise noted.) AVERAGE SUPPLY CURRENT vs. AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING FULLPD) CONVERSION RATE (USING STANDBY)
MAX1270-toc10
8 AVERAGE SUPPLY CURRENT (mA) 7 6 5 4 3 2 1 0
AVERAGE SUPPLY CURRENT (mA)
VDD = 5V, INTERNAL REFERENCE, fCLK = 2MHz EXTERNAL CLOCK MODE. LOW-RANGE UNIPOLAR MODE. VCH_ = 0
7 6 5 4 3 2 1 0
VDD = 5V, INTERNAL REFERENCE, fCLK = 2MHz EXTERNAL CLOCK MODE. LOW-RANGE UNIPOLAR MODE. VCH_ = 0
0.1
1
10
100
1000
0.1
1
10
100
1000
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
Pin Description
PIN DIP 1 2, 4 3, 9, 22, 24 SSOP 1 2, 3 4, 7, 8, 11, 22, 24, 25, 28 5 6 9 10 12 13 14 15-21, 23 26 NAME VDD DGND N.C. FUNCTION +5V Supply. Bypass with a 0.1F capacitor to AGND. Digital Ground No Connect. No internal connection.
5 6 7 8 10 11 12 13-20 21
SCLK CS DIN SSTRB DOUT SHDN AGND CH0- CH7 REFADJ
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. Serial Data Input. Data is clocked in on the rising edge of SCLK. Serial Strobe Output. In internal clock mode, SSTRB goes low after the falling edge of the eighth SCLK and returns high when conversion is done. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high in external clock mode. Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is high. Shutdown Input. When low, device is in FULLPD mode. Connect high for normal operation. Analog Ground Analog Input Channels Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01F capacitor to AGND. Connect to VDD when using an external reference at REF. Reference-Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF. 7-175
23
27
REF
____________________________________________________________________________________
MAX1270-toc11
8
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
+5V 5mA 510k 100k 0.01F 24k a) HIGH-Z TO VOH, VOL TO VOH, AND VOH TO HIGH-Z b) HIGH-Z TO VOH, VOL TO VOH, AND VOH TO HIGH-Z REFADJ
+5V
MAX1270 MAX1271
DOUT OR SSTRB 0.5mA CLOAD
DOUT OR SSTRB
CLOAD
Figure 1. Reference-Adjust Circuit
Figure 2. Output Load Circuit for Timing Characteristics
Detailed Description
Converter Operation
The MAX1270/MAX1271 multirange, fault-tolerant ADCs use successive approximation and internal track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. Figure 3 shows the block diagram of the MAX1270/MAX1271.
Analog-Input Track/Hold
The T/H enters tracking/acquisition mode on the falling edge of the sixth clock in the 8-bit input control word, and enters hold/conversion mode when the timed acquisition interval (six clock cycles, 3s minimum) ends. In internal clock mode, the acquisition is timed by two external clock cycles and four internal clock cycles. When operating in bipolar (MAX1270 and MAX1271) or
unipolar mode (MAX1270) the signal applied at the input channel is rescaled through the resistor-divider network formed by R1, R2, and R3 (Figure 4); a lowimpedance (<4) input source is recommended to minimize gain error. When the MAX1271 is configured for unipolar mode, the channel input resistance (RIN) becomes a fixed 5.12k (typ). Source impedances below 15k (0 to VREF) and 5k (0 to VREF/2) do not significantly affect the AC performance of the ADC. The acquisition time (tACQ) is a function of the source output resistance, the channel input resistance, and the T/H capacitance. Higher source impedances can be used if an input capacitor is connected between the analog inputs and AGND. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC's signal bandwidth.
DIN
SSTRB
DOUT
CS
SCLK
SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 REF
SERIAL INTERFACE LOGIC
INT CLOCK VDD AGND DGND OUT CLOCK 12-BIT SAR ADC
ANALOG INPUT MUX AND SIGNAL CONDITIONING
T/H +4.096V
IN REF
2.5V REFERENCE REFADJ
10k
Av = 1.638
MAX1270 MAX1271
Figure 3. Block Diagram 7-176 ___________________________________________________________________________________
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Input Bandwidth
The ADC's input small-signal bandwidth depends on the selected input range and varies from 1.5MHz to 5MHz (see Electrical Characteristics). The MAX1270/ MAX1271 maximum sampling rate is 110ksps. By using undersampling techniques, it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate. To avoid high-frequency signals being aliased into the frequency band of interest, anti-aliasing filtering is recommended.
Digital Interface
The MAX1270/MAX1271 feature a serial interface that is fully compatible with SPI/QSPI and MICROWIRE devices. For SPI/QSPI, set CPOL = 0, CPHA = 0 in the SPI control registers of the microcontroller. Figure 5 shows detailed serial interface timing information. Refer to Table 1 for programming the input control byte.
MAX1270/MAX1271
BIPOLAR S1 UNIPOLAR R3 5.12k R1 CH_ S2 ON R2 HOLD S3 TRACK TRACK OFF CHOLD
VOLTAGE REFERENCE
Input Range and Protection
The MAX1270/MAX1271 have software-selectable input ranges. Each analog input channel can be independently programmed to one of four ranges by setting the appropriate control bits (RNG, BIP) in the control byte (Table 1). The MAX1270 has selectable input ranges extending to 10V (VREF * 2.441), while the MAX1271 has selectable input ranges extending to VREF. Figure 4 shows the equivalent input circuit. A resistor network on each analog input provides 16.5V fault protection for all channels. Whether or not the channel is on, this circuit limits the current going into or out of the pin to less than 2mA. This provides an added layer of protection when momentary overvoltages occur at the selected input channel, when a negative signal is applied to the input, and when the device is configured for unipolar mode. The overvoltage protection is active even if the device is in power-down mode or if VDD = 0.
T/H OUT HOLD S4
S1 = BIPOLAR/UNIPOLAR SWITCH S2 = INPUT MUX SWITCH S3, S4 = T/H SWITCH
R1 = 12.5k (MAX1270) or 5.12k (MAX1271) R2 = 8.67k (MAX1270) or (MAX1271)
Figure 4. Equivalent Input Circuit
CS
***
tCSH SCLK
tCSS
tCL
tCH
tCSH
*** tDS tDH
DIN tDV DOUT
*** tDO *** tTR
Figure 5. Detailed Serial-Interface Timing ____________________________________________________________________________________ 7-177
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
Table 1. Control-Byte Format
Bit 7 (MSB) START BIT 7 (MSB) 6, 5, 4 3 2 1, 0 (LSB) Bit 6 SEL2 NAME START SEL2, SEL1, SEL0 RNG BIP PD1, PD0 Bit 5 SEL1 Bit 4 SEL0 Bit 3 RNG Bit 2 BIP Bit 1 PD1 Bit 0 (LSB) PD0
DESCRIPTION First logic "1" after CS goes low defines the beginning of the control byte. These three bits select the desired "on" channel (Table 2). Selects the full-scale input voltage range (Table 3). Selects unipolar or bipolar conversion mode (Table 3). Select clock and power-down modes (Table 4).
Table 2. Channel Selection
SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 CHANNEL CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
Table 4. Power Down and Clock Selection
PD1 0 0 1 1 PD0 0 1 0 1 MODE Normal Operation (always on), Internal Clock Mode Normal Operation (always on), External Clock Mode Standby Power-Down Mode (STBYPD), Clock Mode Unaffected Full Power-Down Mode (FULLPD), Clock Mode Unaffected
Table 3. Range and Polarity Selection for MAX1270/MAX1271
RANGE AND POLARITY SELECTION FOR MAX1270 Range and Polarity INPUT RANGE 0 to 5V 0 to 10V 5V 10V RNG 0 1 0 1 BIP 0 0 1 1 NEGATIVE FULL SCALE -- -- -VREF * 1.2207 -VREF * 2.4414 NEGATIVE FULL SCALE -- -- -VREF/2 -VREF ZERO SCALE (V) 0 0 0 0 FULL SCALE VREF * 1.2207 VREF * 2.4414 VREF * 1.2207 VREF * 2.4414
Range and Polarity RANGE AND POLARITY SELECTION FOR MAX1271 INPUT RANGE 0 to VREF/2 0 to VREF VREF/2 VREF RNG 0 1 0 1 BIP 0 0 1 1 ZERO SCALE (V) 0 0 0 0 FULL SCALE VREF/2 VREF VREF/2 VREF
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Input Data Format Input data (control byte) is clocked in at DIN at the rising edge of SCLK. CS enables communication with the MAX1270/MAX1271. After CS falls, the first arriving logic "1" bit represents the start bit (MSB) of the input control byte. The start bit is defined as: The first high bit clocked into DIN with CS low anytime the converter is idle; e.g., after VDD is applied. OR The first high bit clocked into DIN after bit 6 (D6) of a conversion in progress is clocked onto DOUT. Output Data Format Output data is clocked out on the falling edge of SCLK at DOUT, MSB first (D11). In unipolar mode, the output is straight binary. For bipolar mode, the output is two'scomplement binary. For output binary codes, refer to the Transfer Function section. How to Start a Conversion The MAX1270/MAX1271 use either an external serial clock or the internal clock to complete an acquisition and perform a conversion. In both clock modes, the external clock shifts data in and out. Refer to Table 4 for programming clock modes. The falling edge of CS does not start a conversion on the MAX1270/MAX1271; a control byte is required for each conversion. Acquisition starts after the sixth bit is programmed in the input control byte. Conversion starts when the acquisition time, six clock cycles, expires. Keep CS low during successive conversions. If a startbit is received after CS transitions from high to low, but before the output bit 6 (D6) becomes available, the current conversion will terminate and a new conversion will begin. External Clock Mode (PD1 = 0, PD0 = 1) In external clock mode, the clock shifts data in and out of the MAX1270/MAX1271 and controls the acquisition and conversion timings. When acquisition is done, SSTRB pulses high for one clock cycle and conversion begins. Successive-approximation bit decisions appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). Additional SCLK falling edges will result in zeros appearing at DOUT. Figure 7 shows the SSTRB timing in external clock mode. SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB and DOUT will output a logic low. The conversion must be completed in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the clock period exceeds 10s, or if serial-clock interruptions could cause the conversion interval to exceed 120s. The fastest the MAX1270/MAX1271 can run is 18 clocks per conversion in external clock mode, and with a clock rate of 2MHz, the maximum sampling rate is 111 ksps (Figure 8). In order to achieve maximum throughput, keep CS low, use external clock mode with a continuous SCLK, and start the following control byte after bit 6 (D6) of the conversion in progress is clocked onto DOUT. If CS is low and SCLK is continuous, guarantee a start bit by first clocking in 18 zeros.
MAX1270/MAX1271
CS
SCLK
1
8
12
13
14
24
25
DIN SSTRB HIGH-Z DOUT HIGH-Z
START SEL2 SEL1 SEL0 RNG MSB
BIP
PD1
PD0 LSB
HIGH-Z FILLED WITH HIGH-Z ZEROS
D11 MSB
D10
D9
D1
D0 LSB
A/D STATE
ACQUISITION 6 SCLK
CONVERSION 12 SCLK
Figure 6. External Clock Mode, 25 Clocks/Conversion Timing ____________________________________________________________________________________ 7-179
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
CS tSDV SSTRB HIGH-Z *** *** *** *** tSTR HIGH-Z
tSSTRB tSSTRB SCLK ** * * ****
SCLK 12
Figure 7. External Clock Mode SSTRB Detailed Timing
CS
*** ***
SCLK
1 MSB
8
13
14
16
19
24
26
31
32
37
CONTROL BYTE O
LSB
CONTROL BYTE 1
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
CONTROL BYTE 2
START SEL2
DIN
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
***
HIGH-Z SSTRB
18 SCLK ***
MSB
RESULT O
D8 D7 D6 D5 D4 D3 D2 D1
LSB D0 D11 D10 D9
RESULT 1
D8 D7 D6 D5
HIGH-Z DOUT
D11 D10 D9
***
18 SCLK A/D STATE ACQUISITION 6 SCLK CONVERSION 12 SCLK ACQUISITION 6 SCLK CONVERSION 12 SCLK
Figure 8. External Clock Mode, 18 Clocks/Conversion Timing
Internal Clock Mode (PD1 = 0, PD0 = 0) In internal clock mode, the MAX1270/MAX1271 generate their conversion clock internally. This frees the microprocessor from the burden of running the acquisition and the SAR conversion clock, and allows the conversion results to be read back at the processor's convenience, at any clock rate from 0 to typically 10MHz. SSTRB goes low after the falling edge of the last bit (PD0) of the control byte has been shifted in, and returns high when the conversion is complete. Acquisition is completed and conversion begins on the falling edge of the 4th internal clock pulse after the control byte; conversion ends on the falling edge of the
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16th internal clock pulse (12 internal clock cycle pulses are used for conversion). SSTRB will remain low for a maximum of 15s, during which time SCLK should remain low for best noise performance. An internal register stores data while the conversion is in progress. The MSB of the result byte (D11) is present at DOUT starting at the falling edge of the last internal clock of conversion. Successive falling edges of SCLK will shift the remaining data out of this register (Figure 9). Additional SCLK edges will result in zeros on DOUT. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Pulling CS high prevents data from being clocked in and three-states DOUT, but does not adversely affect a
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
CS
SCLK
1
8
9
10
19
20
DIN SSTRB
START SEL2 SEL1 SEL0 RNG MSB
BIP
PD1
PD0 LSB
16 INT CLK DOUT HIGH-Z HIGH-Z ACQUISITION CONVERSION A/D STATE 2 EXT SCLK +4 INT CLK 12 INT CLK
D11 D10 MSB D1 D0 LSB
FILLED WITH ZEROS
HIGH-Z
Figure 9. Internal Clock Mode, 20 SCLK/Conversion Timing
CS * * *
tCSS tCSH tSCK
SSTRB * * * tSSTRB SCLK * * *
SCLK #8
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
conversion in progress. Figure 10 shows the SSTRB timing in internal clock mode. Internal clock mode conversions can be completed with 13 external clocks per conversion but require a waiting period of 15s for the conversion to be completed (Figure 11). Most microcontrollers require that conversions occur in multiples of 8 SCLK clock cycles; 16 clock cycles per conversion, as shown in Figure 12, will typically be the most convenient way for a microcontroller to drive the MAX1270/MAX1271.
Applications Information
Power-On Reset
The MAX1270/MAX1271 power up in normal operation (all internal circuitry active) and internal clock mode, waiting for a start bit. The contents of the output data register are cleared at power-up.
Internal or External Reference
The MAX1270/MAX1271 operate with either an internal or external reference. An external reference is connected to either REF or REFADJ (Figure 13). The REFADJ internal buffer gain is trimmed to 1.638V to provide 4.096V at REF from a 2.5V reference.
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
CS *** *** CONTROL BYTE 2
START SEL2 SEL1 SEL0
SCLK
1
8
9
14
16
22
24
CONTROL BYTE O DIN
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
CONTROL BYTE 1
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
***
13 SCLK *** SSTRB RESULT O HIGH-Z DOUT
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9
RESULT 1
D8 D7 D6 D5 D4 D3
***
13 SCLK ACQUISITION CONVERSION A/D STATE ACQUISITION CONVERSION
Figure 11. Internal Clock Mode, 13 Clocks/Conversion Timing
CS
*** *** CB 2
START
SCLK
1
8
9
16
17
24
25
32
CONTROL BYTE O DIN
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
CONTROL BYTE 1
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
***
16 SCLK SSTRB RESULT O DOUT HIGH-Z HIGH-Z
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
*** RESULT 1 HIGH-Z
D11 D10 D9 D8 D7 D6 D5 D4 D3
***
16 SCLK ACQUISITION CONVERSION A/D STATE IDLE ACQUISITION CONVERSION
Figure 12. Internal Clock Mode, 16 Clocks/Conversion Timing
Internal Reference The internally trimmed 2.50V reference is amplified through the REFADJ buffer to provide 4.096V at REF. Bypass REF with a 4.7F capacitor to AGND and REFADJ with a 0.01F capacitor to AGND (Figure 13a). The internal reference voltage is adjustable to 1.5% (65 LSBs) with the reference-adjust circuit of Figure 1. External Reference To use the REF input directly, disable the internal buffer by tying REFADJ to V DD (Figure 13b). Using the REFADJ input eliminates the need to buffer the reference externally. When a reference is applied at REFADJ, bypass REFADJ with a 0.01F capacitor to AGND. Note that when an external reference is applied at REFADJ, the voltage at REF is given by:
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VREF = 1.6384 * VREFADJ (2.4 < VREF < 4.18) (Figure 13c). At REF and REFADJ, the input impedance is a minimum of 10k for DC currents. During conversions, an external reference at REF must be able to deliver 400A DC load currents and must have an output impedance of 10 or less. If the reference has higher output impedance or is noisy, bypass REF with a 4.7F capacitor to AGND as close to the chip as possible. With an external reference voltage of less than 4.096V at REF or less than 2.5V at REFADJ, the increase in the ratio of RMS noise to the LSB value (full-scale / 4096) results in performance degradation (loss of effective bits).
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Power-Down Mode
REF 4.7F CREF AV = 1.638 REFADJ 0.01F 10k
MAX1270/MAX1271
MAX1270 MAX1271
2.5V
Figure 13a. Internal Reference
To save power, configure the converter into low-current shutdown mode between conversions. Two programmable power-down modes are available in addition to a hardware shutdown. Select STBYPD or FULLPD by programming PD0 and PD1 in the input control byte (Table 4). When software power-down is asserted, it becomes effective only after the end of conversion. For example, if the control byte contains PD1 = 0, then the chip will remain powered up. If PD1 = 1, then the chip will power-down at the end of conversion. In all powerdown modes, the interface remains active and conversion results may be read. Input overvoltage protection is active in all power-down modes. The first logical 1 on DIN after CS falls is interpreted as a start condition, and powers up the MAX1270/ MAX1271 from a software selected STBYPD or FULLPD condition. For hardware-controlled power-down (FULLPD), pull SHDN low. When hardware shutdown is asserted, it becomes effective immediately, and any conversion in progress is aborted. Choosing Power-Down Modes The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7F capacitor at REF. This is a "DC" state that does not degrade after power-down of any duration. In FULLPD mode, only the bandgap reference is active. Connect a 33F capacitor between REF and AGND to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for reference recovery prior to conversion. This allows conversion to begin immediately after power-up. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate, and add 50s for settling time. Auto-Shutdown Selecting STBYPD on every conversion automatically shuts down the MAX1270/MAX1271 after each conversion without requiring any start-up time on the next conversion.
REF
4.096V 4.7F CREF
MAX1270 MAX1271
AV = 1.638 REFADJ 10k
VDD
2.5V
Figure 13b. External Reference, Reference at REF
REF
MAX1270 MAX1271
AV = 1.638 REFADJ 10k
4.7F CREF
2.5V 0.01F
2.5V
Figure 13c. External Reference, Reference at REFADJ
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
OUTPUT CODE 11... 111 11... 110 11... 101 000... 001 000... 000 111... 111 FULL-SCALE TRANSITION OUTPUT CODE FS 1 LSB = 4096 1 LSB = 011... 111 011... 110 2FS 4096
00... 011 00... 010 00... 001 00... 000 0 1 2 3 INPUT VOLTAGE (LSB) FS - 3/2 LSB FS
100... 010 100... 001 100... 000 -FS 0 INPUT VOLTAGE (LSB) +FS - 1 LSB
Figure 14a. Unipolar Transfer Function
Figure 14b. Bipolar Transfer Function
Transfer Function
Output data coding for the MAX1270/MAX1271 is binary in unipolar mode with 1LSB = (FS / 4096) and two's complement binary in bipolar mode with 1LSB = [(2 * | FS | ) / 4096]. Code transitions occur halfway between successive-integer LSB values. Figures 14a and 14b show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. For full-scale values, refer to Table 3.
SUPPLY +5V GND
4.7F R* = 5 0.1F ** VDD AGND DGND +5V DGND
Layout, Grounding, and Bypassing
Careful printed circuit board layout is essential for best system performance. Use a ground plane for best performance. To reduce crosstalk and noise injection, keep analog and digital signals separate. Connect analog grounds and DGND in a star configuration to AGND. For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass VDD with 0.1F and 4.7F capacitors to AGND to minimize highand low-frequency fluctuations. If the supply is excessively noisy, connect a 5 resistor between the supply and VDD, as shown in Figure 15.
MAX1270 MAX1271
DIGITAL CIRCUITRY
* OPTIONAL ** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE.
Figure 15. Power-Supply Grounding Connections
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Pin Configurations
TOP VIEW
VDD 1 VDD 1 DGND 2 N.C. 3 DGND 4 SCLK 5 CS 6 DIN 7 SSTRB 8 N.C. 9 DOUT 10 SHDN 11 AGND 12 24 N.C. 23 REF 22 N.C. 21 REFADJ DGND 2 DGND 3 N.C. 4 SCLK 5 CS 6 N.C. 7 N.C. 8 DIN 9 SSTRB 10 N.C. 11 DOUT 12 SHDN 13 AGND 14 28 N.C. 27 REF 26 REFADJ 25 N.C. 24 N.C.
MAX1270/MAX1271
MAX1270 MAX1271
20 CH7 19 CH6 18 CH5 17 CH4 16 CH3 15 CH2 14 CH1 13 CH0
MAX1270 MAX1271
23 CH7 22 N.C. 21 CH6 20 CH5 19 CH4 18 CH3 17 CH2 16 CH1 15 CH0
DIP
SSOP
Ordering Information (continued)
PART TEMP. RANGE PIN-PACKAGE INL (LSB) 1/2 1 1/2 1 1/2 1 1/2 1 1/2
Chip Information
TRANSISTOR COUNT: 4219 SUBSTRATE CONNECTED TO AGND
MAX1270AENG -40C to +85C 24 Narrow Plastic DIP MAX1270BENG -40C to +85C 24 Narrow Plastic DIP MAX1270AEAI -40C to +85C 28 SSOP MAX1270BEAI -40C to +85C 28 SSOP MAX1271ACNG 0C to +70C 24 Narrow Plastic DIP MAX1271BCNG 0C to +70C MAX1271ACAI 0C to +70C MAX1271BCAI 0C to +70C MAX1271AENG -40C to +85C 24 Narrow Plastic DIP 28 SSOP 28 SSOP 24 Narrow Plastic DIP
MAX1271BENG -40C to +85C 24 Narrow Plastic DIP 1 MAX1271AEAI -40C to +85C 28 SSOP 1/2 MAX1271BEAI -40C to +85C 28 SSOP 1
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
________________________________________________________Package Information
PDIPN.EPS
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Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
Package Information (continued)
MAX1270/MAX1271
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SSOP.EPS
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271
NOTES
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