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E2E1017-27-Y3 Semiconductor
Semiconductor MSM65X227
8-Bit Microcontroller (with 4K-Byte EEPROM)
This version: Jan. 1998 MSM65X227 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM65X227 is a high-performance, 8-bit microcontroller that employs OKI original CPU core, the nX-8/50. The MSM65X227 includes a minimum instruction execution time of 667 ns (@6 MHz) that enables high-speed processing. It has 60K-byte program memory space, internal 4K bytes of EEPROM (general memory space), 1K-byte data memory (384 bytes for local memory space and 640 bytes for general memory space), a timer, a serial port and an A/D converter. The MSM65X227, which has no internal program ROM, is provided with the special time-division data/address bus that can be connected to an extrernal program ROM.
FEATURES
* Operating range Operating frequency Operating voltage Operating temperature * Memory space Program memory space Internal EEPROM Internal data memory * Minimum instruction execution time * Ample instruction set
: : : : : : : : :
0 to 6MHz 4.5 to 5.5V - 40 to +85C 128K bytes 60K bytes 4K bytes 1K bytes 667ns @ 6MHz 81 basic instructions 8/16-bit operation instructions Bit manipulation instructions Complex function instructions 8-bit auto-reload timer 2 (one is shared with the baud rate generator) Watchdog timer 1 Time base counter 1 Serial port 1 (UART/clock synchronous system) 8 bits 4 channels 7 ports, 48 bits 5 ports 8 bits, 1 port 4 bits 1 port 4 bits 2 10
* Ample addressing modes * Timer
:
* Counter * Serial port
: :
* A/D converter : * I/O port : Input-output port : Input-port : * External interrupts : * Interrupt sources : * Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM65X227TS-K)
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Semiconductor
BLOCK DIAGRAM
EEPROM (4K bytes) OSC0 OSC1 RESET HSTOP* XT XT INST. DEC. VDD GND T/C IR ALU GMAR PC
BUS CONT.
EXT.MEM. CONT.
AD0-7 A8-16 RD WR ALE EXWR
OSC CONT. CPU CORE
RAM (640 bytes)
RAM (384 bytes) TBC WDT
WUP TIMER
8-bit TIMERx2
AR
BR
PSW
SP
LMAR SIO
T1OUT* T0CK* GATE* TXD* RXD* INT0* INT1*
INTERRUPT CONT.
8-bit A/D C 4ch
I/O PORT
* is secondary function of each port. **P5 is a 4-bit input-output port. ***P6 is a 4-bit input only port.
MSM65X227
P0
P1
P2
P3
P4
P5**
P6***
AI0*- AI3* AGND VRL VRH AVDD
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MSM65X227
PIN CONFIGURATION (TOP VIEW)
NC NC P0.3 P0.4 P0.5 P0.6 P0.7 XT NC
1 2 3 4 5 6 7 8 9
XT 10 GND 11 OSC0 12 NC 13 OSC1 14 ALE 15 NC 16 RD 17 WR 18 RESET 19 EXWR 20 AGND 21 P6.0 22 P6.1 23 P6.2 24 P6.3 25
99 P0.1 98 P0.0 96 P1.7 95 P1.6 94 P1.5 93 P1.4 100 P0.2 97 NC 92 NC AVDD 28 29 30 31 32 33 34 VRH VRL 27 26 P5.0 P5.1 P5.2 P5.3 NC P4.0
91 P1.3
90 P1.2
89 P1.1
87 P1.0
86 P2.7
84 P2.6
83 P2.5
82 P2.4
80 P2.3
79 P2.2
78 P2.1
77 P2.0
76 A16
88 NC
85 NC
81 NC
75 NC 74 A15 73 A14 72 A13 71 NC 70 A12 69 A11 68 A10 67 A9 66 A8 65 VDD 64 P3.7 63 NC 62 P3.6 61 P3.5 60 NC 59 P3.4 58 P3.3 57 P3.2 56 P3.1 55 P3.0 54 AD7 53 AD6 52 AD5 51 NC
35
36
37
38
39
40
41
42
43
44
45
46
47
48 AD3
49 AD4
P4.1
P4.2
P4.3
NC
P4.4
NC
P4.5
P4.6
P4.7
AD0
AD1
AD2
NC
NC: No-connection Pin 100-Pin Plastic TQFP
NC
50
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Semiconductor
MSM65X227
PIN DESCRIPTION
Basic Functions
Function Power Supply Symbol VDD GND AVDD AGND VRH VRL OSC0 Oscillation OSC1 XT XT Type -- -- -- -- -- -- I O I O Description Digital power supply (5V) Digital ground Analog power supply (5V) Analog ground Analog reference voltage (5V) Analog reference voltage (ground) CPU oscillation input pin CPU oscillation output pin CPU start-up timer oscillation input pin CPU start-up timer oscillation output pin System reset input: When this pin goes into the "L" state, the internal state is initialized and the execution of an instruction starts from address 0040H. The input is pulled up to VDD with an internal pull-up resistor. External write enable pin : Sampled at a system reset and enables external EEPROM write and read during the "L" level. Read signal at external memory access: Read cycle in memory is indicated when the signal goes into the "L" level during external memory access. Write-signal during external memory access: Write cycle in memory is indicated when the signal goes into the "L" level during external memory access. Address latch signal at external memory access: The MSM65X227 uses a time dividing address/data bus. This signal uses the lower 8 bits of the address as a strobe signal to latch the external latch circuit. 8-bit address/data bus: Address/data bus performs lower 8-bit address output, instruction fetch or data read/write along with the ALE, RD and WR pins. 9-bit address bus: Address bus for the upper 9 bits.
RESET
I
EXWR
I
RD
O
Control WR O
ALE
O
AD0 - AD7
I/O
A8 - A16
O
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Semiconductor
MSM65X227
Basic Functions (Continued)
Function Symbol P0.0 - P0.7 Type I/O Description 8-bit input-output port (Port 0): Users can specify input or output at each bit with the port 0 direction register (P0DIR). 8-bit input-output port (Port 1): Users can specify input or output at each bit with the port 1 direction register (P1DIR). In the input mode, ports can be set as inputs with a pull-up resistor at each bit. A secondary function shown in the next table is assigned at the P1.7 pin. 8-bit input-output port ( Port 2): Users can specify input or output at each bit by the port 2 direction register (P2DIR). Each pin of Port 2 is assigned a secondary function shown in the next table. 8-bit input-output port (Port 3): Users can specify input or output at each bit by the port 3 direction register (P3DIR). A secondary function shown in the next table is assigned at the P3.0 pin. 8-bit input-output port (Port 4): Users can specify input or output at each bit with the port 4 direction register (P4DIR). 4-bit input-output port (Port 5): Users can specify input or output at each bit with the port 5 direction register (P5DIR). 4-bit input port (Port 6): Each pin of Port 6 functions as an analog input channel during A/D conversion.
P1.0 - P1.7
I/O
P2.0 - P2.7 Port
I/O
P3.0 - P3.7
I/O
P4.0 - P4.7
I/O
P5.0 - P5.3
I/O
P6.0 - P6.3
I
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Semiconductor Secondary Functions
MSM65X227
Function
Symbol INT0
Type I
Description Secondary function of P1.7: Input pin of external interrupt 0. "Receive" is enabled at rising/falling edges or at the "L" level. Secondary function of P2.0: Input pin of external interrupt 1. "Receive" is enabled at rising/falling edges or at the "L" level. Can also be used as a gate signal input pin that enables/disables the count of Timer 0. Secondary function of P3.0: Hardware stop mode input pin. Changes to hardware stop mode by setting this pin to the "L" level when the HSTP bit of SBYCON is 1. In hardware stop mode, the oscillation of OSC is halted to reduce power consumption. Secondary function of P 2.1: External clock input pin of Timer 0. Secondary function of P 2.2: This pin outputs a waveform with a period equal to two times of overflow of Timer 1. Secondary function of P 2.3: As UART: Receive data input pin of asynchronous communication. As clock synchronization: Send/receive data input-output pin of clock synchronous communication. Secondary function of P 2.4: As UART: Send data output pin of asynchronous communication. As clock synchronization: Synchronized clock output pin of clock synchronous communication. Secondary function of P 6.0 to P 6.3: Functions as an analog input channel at A/D conversion.
External Interrupt INT1 I
Control
HSTOP
I
Timer 0
T0CK
I
Timer 1
T1OUT
O
RXD
I/O
Serial Port
TXD
O
A/D Converter
AI0 - AI3
I
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Semiconductor
MSM65X227
MEMORY MAPS
General Memory Space 0FFFFH 0F000H
Local Memory Space 1FFH
Data Memory
Page 1
Program/Data Area
100H
SFR
100H 80H
Data Memory
Vector Call Table
80H Page 0
Program/Data Area
40H 30H 20H 10H 0
Local Register Set 3 Local Register Set 2 Local Register Set 1 Local Register Set 0
40H 20H 0
Interrupt Vector Table Vector Call Table
,
0FFFFH
EEPROM
Bank 0
Bank 1
Internal Memory
External Data Memory
External Memory
External Memory
1000H
Unavailable Area
27FH
Internal Memory
Data Memory
0
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Semiconductor
MSM65X227
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Output Voltage Analog Reference Voltage Analog Input Voltage Maximum Power Dissipation Storage Temperature Symbol VDD=AVDD VI VO VRH, VRL VAI PD TSTG Ta=25C (per package) Ta=25C (per output pin) Excluding EEPROM data storage GND=AGND=0V Ta=25C Condition Rating -0.3 to 7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 400 50 -55 to +150 mW C V Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Analog Supply Voltage Analog Reference Voltage Analog Input Voltage Memory Hold Voltage Operating Frequency Operating Temperature Symbol VDD AVDD VRH* VAI VDDMH fOSC Top Condition fOSC6MHz VDD=AVDD VRL=AGND=GND=0V fOSC=0Hz VDD=4.5V to 5.5V -- Range 4.5 to 5.5 4.5 to 5.5 AVDD-0.5 to AVDD VRL to VRH 2.0 to 5.5 1 to 6 -40 to +85 MHz C V Unit
*
VRH should be connected to VRL if A/D converter is not used.
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Semiconductor
MSM65X227
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=-40 to +85C) Parameter "H" Input Voltage 1 * "L" Input Voltage "H" Output Voltage "L" Output Voltage Input Leakage Current 1 *3 Input Leakage Current 2 * "L" Input Current *5 "L" Input Current *6 Input Capacitance Current Consumption at Standby Current Consumption during Writing to EEPROM Operating Current Consumption
4 1
Symbol VIH1 VIH2 VIL VOH1 VOL1 ILI1 ILI2 IIL IIL CI IDDS IDDE IDD
Condition CPUCLK=1MHz CPUCLK=1MHz CPUCLK=1MHz IOH=-200mA IOL=1.6mA VI=VDD/0V VI=VDD/0V VI=0V VI=0V f=1MHz, Ta=25C Sleep mode** Sleep mode, no load fOSC=6MHz, no load See Figure 15-1
Min. 2.4 0.7VDD -- 0.75VDD -- -- -- -100 -40 -- -- -- --
Typ. -- -- -- -- -- -- -- -250 -100 5 50 4 20
Max. -- -- 0.8 -- 0.4 1 10 -500 -200 -- 100 10
Unit
"H" Input Voltage 2 *2
V
mA
pF mA
mA 40
*1 *2 *3 *4 *5 *6 **
Excluding OSC0 and RESET OSC0 and RESET EXWR and P6 Excluding EXWR and P6 P1 in pull-up input RESET When the input ports and VREF are at 0V and the output ports are unloaded.
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Semiconductor
MSM65X227
AC Characteristics * External memory control
(VDD=AVDD=VRH=4.5 to 5.5V, GND=AGND=VRL=0V, Ta=-40 to +85C) Parameter Clock Cycle "L" Clock Pulse Width "H" Clock Pulse Width ALE Pulse Width ALE Pulse Delay Time 1 ALE Pulse Delay Time 2 RD Pulse Width RD Pulse Delay Time WR Pulse Width WR Pulse Delay Time "L" Address Setup Time "H" Address Setup Time "L" Address Hold Time Bus Floating Time "H" Address Hold Time "H" Address Hold Time Read Data Access Time Read Data Access Time Read Data Hold Time Write Data Hold Time Write Data Hold Time Symbol tC tCLW tCHW tAW tALD1 tALD2 tRW tRD tWW tWD tLAS tHAS tLAH tLAZ tHAHR tHAHW tRDAA tRDAR tRDH tWDS tWDH CL=100pF -- Condition Min. 167 75 75 tC+tCHW-40 tCLW-20 tCLW-20 tC+tCHW-40 tCLW-20 tC+tCHW-40 tCLW-20 tC-40 tC+tCHW-40 tCLW-20 -- tCLW-20 tCLW-20 -- -- 0 tC+tCHW-40 tCLW-20 Max. -- -- -- -- -- -- -- tCLW+40 -- tCLW+40 -- -- -- 20 -- -- tC+tCLW-15 tCHW+10 -- -- -- ns Unit
* CPU control
(VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=-40 to +85C) Parameter RESET Pulse Width
*1
Symbol tRESW1 tRESW2
Condition -- --
Min. 20 oscillation stabilization time
Max. -- --
Unit ns --
RESET Pulse Width *2
*1 Except during power-on, sleep, and hardware stop modes *2 During power-on, sleep, and hardware stop modes
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Semiconductor * Peripheral control 1
MSM65X227
(VDD = AVDD = 4.5 to 5.5V, GND = AGND = 0V, Ta = -40 to +85C) Parameter OSC EXI T0 Clock Cycle External Interrupt Pulse Width External Clock Pulse Width GATE Pulse Width Symbol tC tEXIW tT0CW tT0GW -- Condition -- MIN 167 4 tC 4 tC 1 tT0CLK * MAX -- -- ns -- -- Unit
*
tT0CLK: Cycle time of timer 0 count clock selected by T0CON.
* Peripheral control 2
(VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=-40 to +85C) Parameter OSC Clock Cycle Synchronous Clock Cycle Synchronous Clock "L" Pulse Width Symbol tC tSIC tSICLW tSICHW tSIOS tSIOH tSIIS tSIIH Condition Min. 167 8 tC 4 tC-20 4 tC-20 6 tC-100 2 tC-100 tC+tCLW+100 0 Max. -- -- -- -- -- -- -- -- Unit
SIO (Clock Synchronous Clock "H" Synchro- Pulse Width nous Output Data Setup Time Mode) Output Data Hold Time Input Data Setup Time Input Data Hold Time
--
ns
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Semiconductor * A/D converter characteristics
MSM65X227
(VDD = AVDD = VRH = 4.5 to 5.5V, GND = AGND = VRL = 0V, Ta = -40 to +85C) Parameter Resolution Linearity Error Differential Linearity Error Zero Scale Error Full Scale Error Crosstalk Conversion Time* Symbol n EL ED EZS EFS ECT tCONV Refer to the measuring circuit. fOSC = 6MHz Refer to the recommended circuit. Analog input source impedance RI 5kW -- -- -- -- -- -- -- -- -- 26.7 Condition Min. -- -- Typ. 8 -- Max. -- +1.5 -1.5 0.5 +1.5 -1.5 0.5 -- Unit bit LSB LSB LSB LSB LSB ms/CH
*
The conversion time immediately after G0 bit is set to "I" is 24.7s/CH.
Definition of Terms Resolution Recognizable minimum input analog value. This can be resolved into 28 = 256, that is (VRH - VRL) / 256 Deviation between ideal conversion characteristics as an 8-bit A/D converter and actual conversion characteristics. (Not including quantization error.) Ideal conversion characteristics means a step which divides voltage between VRH and LRL into 256. Shows the smoothness of conversion characteristics. 1LSB = (VRH - VRL) / 256 is ideal for analog input voltage width corresponding to change per 1 bit of digital output. The differential linearity error is the deviation between this ideal bit size and a bit size at arbitrary point in conversion range. Deviation between ideal conversion characteristics of transfer point for digital outputs "000H" to "001H" and actual conversion characteristics. Deviation between ideal conversion characteristics of transfer point for digital outputs "0FEH" to "0FFH" and actual conversion characteristics.
Linearity Error
Differential Linearity Error
Zero Scale Error
Full Scale Error
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Semiconductor Recommended circuit
MSM65X227
AVDD VRH VDD +5V
MSM65X227 - + VRL Analog Voltage Input 0.1 F AGND
+ 0.1 47 F F
RI AI0-3 GND
0V
RI (Analog input source impedance) 5kW
Crosstalk measuring circuit
- +
5kW
AI0 AI1
Analog Voltage Input 0.1 F AI3
Crosstalk is defined as the difference of A/D conversion result between supplying the same voltage to AI0 to AI3 and supplying voltage shown in this left diagram.
VRH or AGND
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Semiconductor
MSM65X227
EEPROM Characteristics
Parameter Number of rewrites Data storage time Rating 10,000 100 10 years 100 bytes 3,996 bytes Storage between -40 and 85C Failure rate < 1% Condition
(VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=-40 to +85C) Parameter Write disable time after reset Write time Symbol tINHWR tEEWR Min. -- -- Typ. 5 6 Max. -- 8 Unit ms ms
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Semiconductor
MSM65X227
TIMING DIAGRAM
External Memory Control
tCHW OSC0 tCLW ALE tRD RD tRDAR tLAS AD0-7 ADDRESS L tRDAA tHAS A8-16 tWD WR tWDS AD0-7 ADDRESS L DATA OUT tHAHW A8-16 ADDRESS H tWDH ADDRESS H tWW tALD2 tHAHR tLAH tLAZ INST or DATA IN tRDH tRW tALD1 tAW tC
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Semiconductor
MSM65X227
CPU Control 1) RESET pulse width
tRESW1, 2 RESET
Peripheral control 1
tC OSC0 tCLW
1) EXI Pulse width
tEXIW INT0-1
2) T0
tT0CW T0CK tT0GW GATE
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Semiconductor Peripheral control 2 1) SIO (Clock synchronous mode)
tSFC tSFCLW TXD tSFCHW
MSM65X227
tSFOS RXD (transmission) tSFIS RXD (reception)
tSFOH
tSFIH
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Semiconductor
MSM65X227
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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