View UPD3719_5359.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD3719
10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
The PD3719 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3719 has 3 rows of 10600 pixels, and each row has a single-sided readout type of charge transfer register. It has reset feed-through level clamp circuits and voltage amplifiers. Moreover, a large dynamic range is realized by using a large saturation voltage and a low-noise amplifier. Therefore, it is suitable for 1200 dpi/A4 professional color image scanners and so on.
FEATURES
* Valid photocell * Line spacing * Color filter * Resolution : 10600 pixels x 3 : 70 m (10 lines) Red line-Green line, Green line-Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx*hour) : 48 dot/mm A4 (210 x 297 mm) size (shorter side) 1200 dpi US letter (8.5" x 11") size (shorter side) * Drive clock level : CMOS output under 5 V operation * Data rate * Power supply : 2 MHz MAX. : +15 V Voltage amplifiers
* Photocell's pitch : 7 m
* On-chip circuits : Reset feed-through level clamp circuits
ORDERING INFORMATION
Part Number Package CCD linear image sensor 36-pin ceramic DIP (600 mil)
PD3719D
The information in this document is subject to change without notice. Document No. S13492EJ1V0DS00(1st edition) Date published September 1998 N CP(K) Printed in Japan
(c)
1998
PD3719
BLOCK DIAGRAM
CLB
31
GND 3
GND 34
GND 32
GND 15
S10599 S10600
2
25
1
24 22 GND
******
Photocell (Blue)
D14
D64
D65
D66
D67
S1
S2
Transfer gate VOUT1 33 (Blue)
D14
23
TG
CCD analog shift register
S10599 S10600
21
D65 D66 D67
GND
******
Photocell (Green)
D64
S1
VOUT2 (Green) 35
D14
Transfer gate CCD analog shift register 14
S10599
S2
GND
******
Photocell (Red)
S10600
D64
D65
D66
Transfer gate VOUT3 (Red) 2 CCD analog shift register
D67
S1
S2
4 VOD
5
6 VRD
12
13
RB
2
1
2
PD3719
PIN CONFIGURATION (Top View) CCD linear image sensor 36-pin ceramic DIP (600 mil)
No connection Output signal 3 (Red) Ground Output drain voltage Reset gate clock Reset drain voltage No connection No connection No connection
NC VOUT3 GND VOD
1 2 1 1 1 3 4 5 6 7 8 9
36 35 34 33 32 31 30 29 28
NC VOUT2 GND VOUT1 GND
No connection Output signal 2 (Green) Ground Output signal 1 (Blue) Ground Reset feed-through level clamp clock No connection No connection No connection
RB
VRD NC NC NC
CLB
NC NC NC
Green
Blue
Red
No connection No connection Shift register clock 2 Shift register clock 1 Ground Ground No connection No connection No connection
NC NC
10 11 12 13 14 15 10600 10600 10600 16 17 18
27 26 25 24 23 22 21 20 19
NC NC
No connection No connection Shift register clock 2 Shift register clock 1 Transfer gate clock Ground Ground No connection No connection
2 1
GND GND NC NC NC
2 1 TG
GND GND NC NC
3
PD3719
PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
7 m
Blue photocell array 10 lines (70 m)
4 m
3 m
7 m Green photocell array
7 m
Channel stopper
7 m Red photocell array
10 lines (70 m)
Aluminum shield
4
PD3719
ABSOLUTE MAXIMUM RATINGS (TA = +25 C)
Parameter Output drain voltage Reset drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature VOD VRD V1, V2 VRB VCLB VTG TA Tstg Symbol Ratings -0.3 to +16 -0.3 to +16 -0.3 to +8 -0.3 to +8 -0.3 to +8 -0.3 to +8 -25 to +60 -40 to +100 Unit V V V V V V C C
Caution
Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 C)
Parameter Output drain voltage Reset drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high level Transfer gate clock low level Data rate VOD VRD V1H, V2H V1L, V2L VRBH VRBL VCLBH VCLBL VTGH VTGL fRB Symbol MIN. 14.0 14.0 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.5 -0.3 - TYP. 15.0 VOD 5.0 0 5.0 0 5.0 0 V1HNote 0 1 MAX. 16.0 VOD 5.5 +0.5 5.5 +0.5 5.5 +0.5 V1HNote +0.3 2 Unit V V V V V V V V V V MHz
Note
When Transfer gate clock high level (VTGH) is higher than Shift register clock high level (V1H), Image lag can increase.
5
PD3719
ELECTRICAL CHARACTERISTICS
TA = +25 C, VOD = 15 V, VRD = 15 V, data rate (fRB) = 2 MHz, storage time = 5.5 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Red Green Blue Image lag Offset level
Note1 Note2
Symbol Vsat SER SEG SEB PRNU ADS DSNU PW ZO RR RG RB IL VOS td TTE Red Green Blue
Test Conditions
MIN. 4.0
TYP. 5.0 0.52 0.57 0.94
MAX. -
Unit V lx*s lx*s lx*s
VOUT = 2.5 V Light shielding Light shielding
6 0.8 1.5 400 0.5 6.8 6.2 3.8 9.7 8.8 5.3 2.0 8.8 10.8 70 92 98 630 540 460
20 3.0 5.0 600 1 12.6 11.4 6.8 5.0 12.8
% mV mV mW k V/lx*s V/lx*s V/lx*s % V ns % nm nm nm times times
VOUT = 2.5 V
Output fall delay time
VOUT = 2.5 V VOUT = 2.5 V
Total transfer efficiency Response peak
Dynamic range
DR1 DR2
Vsat /DSNU Vsat / Light shielding Light shielding 0 -
3333 10000 1500 0.5 2500 -
Reset feed-through noise Random noise
Note1
RFTN
mV mV
Notes 1. Refer to TIMING CHART 2. 2. When the fall time of 1 (t1) is the TYP. value (refer to TIMING CHART 2).
6
PD3719
INPUT PIN CAPACITANCE (TA = +25 C, VOD = VRD = 15 V)
Parameter Shift register clock pin capacitance 1 Symbol C1 Pin name Pin No. 13 24 Shift register clock pin capacitance 2 C2 MIN. TYP. 1600 1600 1600 1600 15 15 200 MAX. Unit pF pF pF pF pF pF pF
1
2
12 25
Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance
CRB CCLB CTG
RB CLB TG
5 31 23
Remark Pins 13 and 24 (1), 12 and 25 (2) are each connected inside of the device.
7
VOUT1 to VOUT3
Optical black (49 pixels)
Valid photocell (10600 pixels)
Invalid photocell (2 pixels)
Note
Input the RB and CLB pulses continuously during this period, too.
10663 10664 10665 10666 10667 10668 10669
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
61 62 63 64 65 66
8
TIMING CHART 1 (for each color)
TG
1
2
RB
CLB
Note Note
Invalid photocell (3 pixels)
PD3719
TIMING CHART 2 (for each color)
t1 t2
1
90 % 10 %
2
t5 t6
90 % 10 % t3 t4
RB
90 % 10 % t10 90 % 10 % t8 t7 t9 t11
CLB
td VOUT1 to VOUT3
RFTN
VOS 10 %
PD3719
9
PD3719
TG, 1, 2 TIMING CHART
t12 90 % t14 t13
TG
10 % t15 90 % t16
1
2
Symbol t1, t2 t3 t4 t5, t6 t7 t8, t9 t10 t11 t12, t13 t14 t15, t16
MIN. 0 30 70 0 30 0 10 5 0 3000 900
TYP. 25 50 150 25 75 25 20 10 50 10000 1000
MAX. -- -- -- -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns
Remark
TYP. is an example of at 1 MHz data rate (fRB) operation.
1, 2 cross points
1
2 V or more 2 V or more
2
Remark
Adjust cross points of 1 and 2 with input resistance of each pin.
10
PD3719
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
PRNU (%) = x x 100 x x : maximum of xj - x
10600 j=1
xj
x=
10600
xj : Output voltage of valid pixel number j
VOUT
Register Dark DC level
x x
4.
Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
10600
ADS (mV) =
dj j=1
dj : Dark signal of valid pixel number j
10600
5.
Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj - ADS j = 1 to 10600 dj : Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
11
PD3719
6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix*s). Note that the response varies with a light source (spectral characteristic). 8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light
ON
OFF
VOUT V1 VOUT
V1 IL (%) = VOUT
x100
9.
Random noise: Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding).
100
(mV) =
(Vi - V) i=1
100
2
, V=
1
100
100 i=1
Vi
Vi: A valid pixel output signal among all of the valid pixels for each color
VOUT
V1 V2
line 1 line 2
V100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
...
line 100
...
12
PD3719
STANDARD CHARACTERISTIC CURVES
DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 C)
4
Relative Output Voltage Relative Output Voltage
1
2
1
0.5
0.25
0.2
0.1 0
10
20
30
40
50
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA(C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) (TA = +25 C) 100 R
B 80
G
Response Ratio (%)
60
40
G 20
B 0 400 500 600 Wavelength (nm) 700 800
13
PD3719
APPLICATION CIRCUIT EXAMPLE
+5 V 10 + 1 10 F/16 V 0.1 F
B3
+15 V
PD3719
NC VOUT3 GND VOD
RB
+ 36 35 34 + 33 32 31 30 29 28 47
B1
NC VOUT2 GND VOUT1 GND
CLB
2 3 4
0.1 F 47 F/25 V
B2
+5 V
RB
47
5 6 + 7 8 9
0.1F 10 F/16 V
CLB
VRD NC NC NC
NC NC NC
47 F/25 V
10 11
2
NC NC
2 1
NC NC
2 1 TG
27 26 25 24 23 22 21 20 19 4.7 4.7 4.7
1 TG
4.7 4.7
12 13 14 15 16 17 18
GND GND NC NC NC
GND GND NC NC
Remark
The inverters shown in the above application circuit example are the 74HC04.
B1 to B3 EQUIVALENT CIRCUIT 15 V + 100 CCD VOUT 100 2SC945 47 F/25 V
2 k
14
PD3719
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (600mil)
(Unit : mm)
94.000.50 8.10.6
1
36.40.6 The 1st valid pixel
2
14.990.3
15.24 1.270.05 (4.33) (2.33)
3
0.460.05 88.90.6
2.54 20.32 2.00.3
4
0.250.05 3.500.5 0.970.3 3.300.35
Name Glass cap 1 The 1st valid pixel 2 The 1st valid pixel 3 The surface of the chip 4 The bottom of the package
Dimensions 93.0 x 13.6 x 1.0
Refractive index 1.5
The center of the pin1 The center of the package The top of the glass cap (Reference) The surface of the chip
36D-1CCD-PKG-1
15
PD3719
NOTES ON THE USE OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. When mounting the package, use a circuit board which will not subject the package to bending stress, or use a socket. For this product, the reference value for the three-point bending strengthNote is 30 kg. Avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). Note Three-point bending strength test Distance between supports: 70 mm, Support R: R 2 mm, Loading rate: 0.5 mm / min.
Load
Load
70 mm
70 mm
16
PD3719
[MEMO]
17
PD3719
[MEMO]
18
PD3719
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
19
PD3719
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

▲Up To Search▲

Price & Availability of UPD3719

	To Download UPD3719 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .