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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3739
5000 PIXELS CCD LINEAR IMAGE SENSOR
The PD3739 is a CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal. The PD3739 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the photo signal electrons of 5000 pixels separately in odd and even pixels. It is developed as the higher sensitivity version of the previous device, the PD35H71A. It is suitable for 400 dpi/A3 high-speed digital copiers, OCRs and high-end business facsimiles.
FEATURES
* Valid photocell * Photocell's pitch * High sensitivity * Low image lag * Resolution * Data rate * Output type * Power supply * Drive clock level * On-chip circuit * Pin assign : 5000 pixels : 7 m : 9.0 V/lx*s TYP. (Light source: Daylight color fluorescent lamp) : 1 % MAX. : 16 dot/mm (400 dpi) A3 (297 x 420 mm) size (shorter side) : 40 MHz MAX. (20 MHz/1 output) : 2 outputs out of phase (2 outputs in phase also supported) : +12 V : CMOS output under 5 V operation : Automatic R level adjuster : Functional compatible with the PD35H71A
* Peak response wavelength : 550 nm (green)
ORDERING INFORMATION
Part Number Package CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)
PD3739D
The information in this document is subject to change without notice. Document No. S12744EJ1V0DS00 (1st edition) Date Published September 1997 N Printed in Japan
(c)
1997
PD3739
COMPARISON CHART
Item PIN CONFIGURATION Pin 1 Pin 2 Pin 4 Pin 11 Pin 21 Pin 22 RECOMMENDED OPERATING CONDITIONS Capacitance of reset gate clock pin external capacitor (pF) Data rate MIN. (MHz) ELECTRICAL CHARACTERISTICS Saturation exposure TYP. (Ixs) Photo response non-uniformity (%) TYP. MAX.
PD3739
GND NC NC NC NC NC 1000 20 %
PD35H71A
DGND TEST VDD VSUB AGND DGND Unspecified
0.5 0.17 4 10 0.3 0 4 6 400 7.2 9.0 10.8 3.5 MIN. TYP. MAX. DR1 DR2 MIN. TYP. MAX. 250 350 500 375 2143 0 400 600 0.7 In phase outputs operating timing is added
Unspecified 0.29 5 10 1.0 -3 -1, +3 +6 Unspecified 4.15 5.2 6.25 3.0 400 500 800 500 Undefined Unspecified 250 500 Undefined Out of phase outputs operation only Minus and plus value Minus and plus value Undefined
Average dark signal TYP. (mV) Dark signal non-uniformity (mV) MIN. TYP. MAX. Power consumption MAX. (mW) Response (V/Ixs) MIN. TYP. MAX.
Offset level TYP. (V) Shift register clock pin capacitance (pF) Note
Dynamic range TYP. (times) Reset feed-through noise (mV)
Random noise TYP. (mV) TIMING CHART
DEFINITIONS OF CHARACTERISTICS ITEMS
Photo response non-uniformity Dark signal non-uniformity Random noise
Absolute value Absolute value Standard deviation of signal level distribution by scan Wave soldering is deleted
RECOMMENDED SOLDERING CONDITIONS
--
Note Due to the changing of measurement conditions, and pin capacitance of each devices is almost the same. (PD3739: Power supply = 12 V, PD35H71A: Power supply = 0 V)
2
BLOCK DIAGRAM
GND 1
VOD 19
R2
18
1L2
17
22
14
12
13
VOUT2
20
CCD analog shift register Transfer gate
S4999
S5000
D32
D33
D34
D9
S1
S2
Automatic R level adjuster
......
Photocell
12
TG
Transfer gate VOUT1 3 CCD analog shift register
5
6
9
10
R1
2L1
21
11
PD3739
3
PD3739
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)
Ground
1
GND
NC
22
No connection
No connection
2
NC
NC
21
No connection
Output signal 1
3
VOUT1
VOUT2
20
Output signal 2
No connection
4
NC
VOD
19
Output drain voltage
Reset gate clock 1
5
R1 2L1
R2 1L2
18
Reset gate clock 2
Last stage shift register clock 2
6
17
Last stage shift register clock 1
No connection
7
NC
NC
16
No connection
No connection
8
NC
NC
15
No connection
Shift register clock 2
9
21 11
NC
22 12 TG
14
Shift register clock 2
Shift register clock 1
10
13
Shift register clock 1
No connection
11
12
Transfer gate clock
PHOTOCELL STRUCTURE DIAGRAM
5 m
2 m
7 m
Channel stopper
Aluminum shield
4
PD3739
ABSOLUTE MAXIMUM RATINGS (TA = +25 C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature VOD V1, V2 VR1, VR2 VTG TA Tstg Symbol Ratings -0.3 to +15 -0.3 to +15 -0.3 to +15 -0.3 to +15 -25 to +55 -40 to +100 Unit V V V V C C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = -25 to +55 C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Capacitance of reset gate clock pin external capacitor Transfer gate clock high level Transfer gate clock low level Data rate Symbol VOD V1H, V2H V1L, V2L VR1H, VR2H VR1L, VR2L CEXTR VTGH VTGL 2fR1, 2fR2 Note Note Non-polar type Conditions MIN. 11.4 4.5 -0.3 4.5 -0.3 800 4.5 -0.3 0.5 TYP. 12.0 5.0 0 5.0 0 1000 5.0 0 2 MAX. 12.6 5.5 +0.5 5.5 +0.5 1200 5.5 +0.5 40 Unit V V V V V pF V V MHz
Note Input the reset gate clocks 1 and 2 (R1, R2) to pins 5 and 18, respectively, via an input resistor and a capacitor. Use of a capacitor is indispensable. Refer to APPLICATION CIRCUIT EXAMPLE for the connection method. The reset gate clock high level and low level at the IC pins (after passing through the external capacitor) varies according to the IC, due to the on-chip automatic R level adjuster. The recommended operating conditions of reset gate clocks 1, 2 (R1, R2) in the table above are for signals applied to the external capacitor. Remark 1 in the above tables represents 11, 12 and 1L2. 2 represents 21, 22 and 2L1.
5
PD3739
ELECTRICAL CHARACTERISTICS
TA = +25 C, VOD = 12 V, f1 = 1 MHz, data rate = 2 MHz, storage time = 10 ms light source: 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 Vp-p
Parameter Saturation voltage Saturation exposure Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Response peak wavelength Image lag Offset level
Note 1 Note 2
Symbol Vsat SE PRNU ADS DSNU PW ZO RF
Test Conditions
MIN. 1.0
TYP. 1.5 0.17 4 0.3
MAX.
Unit V lx*s
Daylight color fluorescent lamp VOUT = 500 mV Light shielding Light shielding 0
10 3.0 6.0 400 0.5 10.8
% mV mV mW k V/Ix*s nm
4.0 200 0.2
Daylight color fluorescent lamp
7.2
9.0 550
IL VOS td RI TTE DR1 DR2
VOUT = 1 V 2.0 VOUT = 1 V VOUT = 500 mV VOUT = 500 mV, data rate = 40 MHz Vsat/DSNU Vsat/ Light shielding Light shielding 0 -- 0 92
0.3 3.5 20
1.0 5.0
% V ns
Output fall delay time Register imbalance
4.0 98 375 2143 400 0.7 600 --
% % times times mV mV
Total transfer efficiency Dynamic range
Reset feed-through noise Note 1 Random noise
RFTN
Notes 1. Refer to TIMING CHART 2, 5. 2. Typical value when the respective fall times of 1L2 and 2L1 are t11', t41' and t2', t32' (refer to TIMING CHART 2, 5). Note that VOUT1 and VOUT2 are the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE.
6
PD3739
INPUT PIN CAPACITANCE (TA = +25 C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Symbol C1 Pin name Pin No. 10 13 9 14 17 6 5 18 12 MIN. 250 250 250 250 40 40 8 8 100 TYP. 350 350 350 350 50 50 10 10 150 MAX. 500 500 500 500 100 100 15 15 200 Unit pF pF pF pF pF pF pF pF pF
11 12
Shift register clock pin capacitance 2
C2
21 22
Last stage shift register clock pin capacitance
CL
1L2 2L1
Reset gate clock pin capacitance
CR
R1 R2
Transfer gate clock pin capacitance
CTG
TG
7
5029
5031
5033
5035 5034 5036
VOUT1
12 22 1L2 R2
Note
5030 5032 5038 10 12 28 30 32 34 36 2 4 6 8
VOUT2
Optical black (22 pixels) Invalid photocell (2 pixels)
Valid photocell (5000 pixels)
5037
11
27
29
31
33
35
1
3
5
7
9
8
TIMING CHART 1 (Out of phase operation)
TG 11 21 2L1 R1
PD3739
Note Input the R1 and R2 pulses continuously during this period, too.
Invalid photocell (2 pixels)
TIMING CHART 2 (Out of phase operation)
t7 t1 90 % 10 % 90 % 10 % 50 % t5 t6 t4 50 % td VOUT1 RFTN VOS 10 % t3 t2
11 21
50 % 50 % t1' t2' 90 % 10 % 90 % 10 %
2L1
t7'
R1
t12
t11 50 % 50 %
t17
12 22 1L2
90 % 10 % 90 % 10 %
t11' t17' t15 90 % 10 % td 90 % 10 % t14
t12'
50 %
t16
R2
50 %
t13
VOUT2 RFTN VOS 10 %
PD3739
9
PD3739
TIMING CHART 3 (Out of phase operation)
t21 90 % t22
TG
50 % 10 % t24 t23 t25
11, 12, 1L2
50 %
21, 22, 2L1
11, 21 cross points
11
12, 22 cross points
12
21
2 V or more
2 V or more
22
2 V or more
2 V or more
11, 2L1 cross points
11
1L2, 22 cross points
22
2L1
2 V or more
0.5 V or more
1L2
2 V or more
0.5 V or more
Remark Adjust cross points of (11, 21), (12, 22), (11, 2L1) and (1L2, 22) with input resistance of each pin.
Symbol t1, t2, t11, t12 t1', t2', t11', t12' t3, t13 t4, t14 t5, t6, t15, t16 t7, t7', t17, t17' t21, t22 t23 t24, t25 MIN. 0 0 15 5 0 25 0 1000 10 TYP. 50 5 50 20 20 -- 50 2000 100 5000 MAX. Unit ns ns ns ns ns ns ns ns ns
10
TIMING CHART 4 (In phase operation)
TG 11 21 2L1 R1
5029 5031 5033 5035 5036 5037 5038
11
27
29
31
33
VOUT1
12 22 1L2 R2
Note
5030 5032 5034 10 12 28 30 32 34 36 2 4 6 8
VOUT2
Optical black (22 pixels)
35
1
3
5
7
9
Valid photocell (5000 pixels)
PD3739
Note Input the R1 and R2 pulses continuously during this period, too.
Invalid photocell (2 pixels)
Invalid photocell (2 pixels)
11
12
TIMING CHART 5 (In phase operation)
t37
t31 90 % 10 % 90 % 10 % 50 %
t32
11 21
50 %
50 % t32' 90 % 10 %
t31' t37'
2L1 R1
90 % 10 %
t35 t36
t34
50 % td
t33
VOUT1 RFTN VOS 10 %
t47
t42 90 % 10 % 90 % 10 % 50 %
t41
12 22
50 % 50 % t41' 90 % 10 %
t42' t47'
1L2
t45 90 % 10 %
t46
t44
R2
50 % td
t43
VOUT2 RFTN VOS
PD3739
10 %
PD3739
TIMING CHART 6 (In phase operation)
t51 90 % 50 % 10 % t54 t53 t55 t52
TG
11
50 %
21, 2L1
12, 1L2
50 %
22
11, 21 cross points
11
12, 22 cross points
12
21
2 V or more
2 V or more
22
2 V or more
2 V or more
11, 2L1 cross points
11
1L2, 22 cross points
22
2L1
2 V or more
0.5 V or more
1L2
2 V or more
0.5 V or more
Remark Adjust cross points of (11, 21), (12, 22), (11, 2L1) and (1L2, 22) with input resistance of each pin.
Symbol t31, t32, t41, t42 t31', t32', t41', t42' t33, t43 t34, t44 t35, t36, t45, t46 t37, t37', t47, t47' t51, t52 t53 t54, t55 MIN. 0 0 15 5 0 25 0 1000 10 TYP. 50 5 50 20 20 -- 50 2000 100 5000 MAX. Unit ns ns ns ns ns ns ns ns ns
13
PD3739
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time(s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
PRNU (%) =
x x 100 x x : maximum of xj - x
5000 2700
x= x = 5000 2700
xj : Output voltage of valid pixel number j
j j=1 =1
xjxj
VOUT x Register Dark DC level x
4.
Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
5000
j=1 ADS (mV) = 5000 2700
dj ADS (mV) =
j=1
2700
dj
dj : Dark signal of valid pixel number j
14
PD3739
5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV): maximum of | dj - ADS |
j = 1 to 5000
dj: Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
6.
Output impedance: ZO Impedance of the output pins viewed from outside.
7.
Response: R Output voltage divided by exposure (Ix*s). Note that the response varies with a light source (spectral characteristic).
8.
Image lag: IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light OFF
ON
VOUT VOUT
V1
V1 IL (%) = VOUT
x100
15
PD3739
9. Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
n
2 n RI (%) =
(V2j - 1 - V2j)
j= 1
2
1 n
Vj
j= 1
n
x 100
n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise: Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding).
(Vi - V) 2
(mV) =
i=1
100
100
, V=
1 100
Vi
i=1
100
Vi : A valid pixel output signal among all of the valid pixels
VOUT V1 line 1
V2
line 2
V100
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
16
PD3739
STANDARD CHARACTERISTIC CURVES (TA = +25 C)
DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC
4 1
Relative Output Voltage
2
1
0.5
Relative Output Voltage
0.25
0.2
0.1 0 10 20 30 40 50 Operating Ambient Temperature TA (C)
0.1 1 5 Storage Time (ms) 10
SPECTRAL RESPONSE CHARACTERISTIC 100
80
Response Ratio (%)
60
40
20
0 400 600 800 Wavelength (nm) 1000 1200
17
PD3739
APPLICATION CIRCUIT EXAMPLE (Out of phase operation)
+12 V 10
PD3739
+5 V 1 2 GND NC NC NC 22 21
+
0.1 F 47F/25 V
+
+5 V
+
10 F/16 V 0.1 F
B1
3 4
VOUT1 NC
VOUT2 VOD
20 19
B2
0.1 F 10 F/16 V
R1 2
200 1000 pF 47
5 6
R1 2L1
NC NC
R2 1L2
NC NC
18 17
1000 pF 200 47
R2 1
7 8 2 2 9 10
16 15 14 13 2 2 2
21 11
NC
22 12 TG
11
12
TG
Remarks 1. The PD3739 can be operated leaving pin 2 (NC) unconnected, and connecting pin 4 (NC) and pin 11 (NC) to a +12 V power supply (when replaces the PD35H71A). 2. It is recommended that pins 6 (2L1) and 17 (1L2) each is separately driven a driver other than that of pins 10, 13 (11, 12) and pins 9, 14 (21, 22). 3. The inverters shown in the above application circuit example are the 74AC04.
B1, B2 EQUIVALENT CIRCUIT
+12 V
4.7 k 110 CCD VOUT 47 2SA1005
47 F/25V
+
2SC945
1 k
18
PD3739
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22PIN CERAMIC DIP(CERDIP)(400mil)
(Unit : mm)
1bit 4.0 0.3
1.600.25
42.2 0.25 48.6 0.5
10.16
(1.95) 4.330.5
9.650.3
2.38 0.3
(5.27)
1.02 0.15 0.46 0.06 25.4
2.54
4.680.5
0 to 10
0.250
.05
Name
Glass cap
Dimensions 47.5x9.25x0.7
Refractive index
1.5
22D-1CCD-PKG8
19
PD3739
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Type of Through-hole Device
PD3739D: CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)
Process Partial heating method Conditions Pin temperature: 260 C or below, Heat time: 10 seconds or less (per pin).
20
PD3739
[MEMO]
21
PD3739
[MEMO]
22
PD3739
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
23
PD3739
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
2

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