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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3788
7300 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
The PD3788 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3788 has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels. Moreover, the spectral response characteristics of the PD3788 is modified from the previous device PD3728 to be suitable for Xe-lamp. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on.
FEATURES
* Valid photocell * Photocell pitch * Photocell size * Line spacing * Color filter * Resolution * Data rate * Output type * Power supply * On-chip circuits : 7300 pixels x 3 : 10 m : 10 x 10 m2 : 40 m (4 lines) Red line-Green line, Green line-Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx*hour) : 24 dot/mm (600 dpi) A3 (297 x 420 mm) size (shorter side) : 40 MHz MAX. (20 MHz/1 output) : 2 outputs in phase/color : +12 V : Reset feed-through level clamp circuits Voltage amplifiers
* Drive clock level : CMOS output under 5 V operation
ORDERING INFORMATION
Part Number Package CCD linear image sensor 36-pin ceramic DIP (15.24 mm (600))
PD3788D
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14664EJ1V0DS00(1st edition) Date published June 2000 N CP(K) Printed in Japan
(c)
2000
PD3788
COMPARISON CHART
Item ABSOLUTE MAXIMUM RATINGS Shift register clock voltage (V) Reset gate clock voltage (V) Reset feed-through level clamp clock voltage (V) Transfer gate clock voltage (V) ELECTRICAL CHARACTERISTICS Saturation exposure (Ix*s) Red Green Blue Response (V/Ix*s) Red TYP. TYP. TYP. MIN. TYP. MAX. Green MIN. TYP. MAX. Blue MIN. TYP. MAX. Response peak (nm) Red Green Blue Random noise test conditions TIMING CHART t3 (ns) t7 (ns) t10 (ns) tCP (ns) MIN. MIN. MIN. MIN. TYP. STANDARD CHARACTERISTIC CURVES TOTAL SPECTRAL RESPONSE CHARACTERISTICS TYP. TYP. TYP.
PD3788
-0.3 to +8 -0.3 to +8 -0.3 to +8 -0.3 to +8 0.36 0.37 0.80 3.85 5.5 7.15 3.78 5.4 7.02 1.75 2.5 3.25 645 540 445 tcp = 20 ns 17 17 -20 5 150 modified
PD3728
-0.3 to +15 -0.3 to +15 -0.3 to +15 -0.3 to +15 0.35 0.39 0.31 3.9 5.6 7.3 3.6 5.1 6.6 4.5 6.4 8.3 630 540 460 t7 = 150 ns 20 20 -10 - - -
2
Data Sheet S14664EJ1V0DS00
PD3788
BLOCK DIAGRAM
CLB
30
1L
29
20
28
GND 16
1
23
2
24
GND
31
VOUT2 (Blue, even)
32
D128
CCD analog shift register Transfer gate
S7299 S7300 D129 D27
GND
33
.....
S1 S2
Photocell (Blue)
.....
D134
22
TG1 (Blue)
VOUT1 (Blue, odd) GND
34 35
Transfer gate CCD analog shift register
VOUT3 36 (Green, odd)
D128 D27
CCD analog shift register Transfer gate
S7299 S7300 D129 S1 S2
.....
Photocell (Green)
.....
D134
21
TG2 (Green)
VOUT4 1 (Green, even) GND VOUT6 (Red, even) 2 3
D128
Transfer gate CCD analog shift register
CCD analog shift register Transfer gate
S7299 S7300 D129 D27 S1 S2
GND
4
.....
Photocell (Red)
.....
D134
15
TG3 (Red)
VOUT5 (Red, odd)
5
Transfer gate CCD analog shift register
GND
6
7 VOD
8
9
13
14
RB
10
1
2
Data Sheet S14664EJ1V0DS00
3
PD3788
PIN CONFIGURATION (Top View) CCD linear image sensor 36-pin ceramic DIP (15.24 mm (600))
* PD3788D
Output signal 4 (Green, even) VOUT4 1 Ground GND 2
1 1 1
36 VOUT3 35 GND 34 VOUT1 33 GND 32 VOUT2 31 GND 30 CLB 29 1L 28 20
Green
Output signal 3 (Green, odd) Ground Output signal 1 (Blue, odd) Ground Output signal 2 (Blue, even) Ground Reset feed-through level clamp clock Last stage shift register clock 1 Shift register clock 20
Output signal 6 (Red, even) VOUT6 3 Ground GND 4
Output signal 5 (Red, odd) VOUT5 5 Ground Output drain voltage Reset gate clock Shift register clock 10 GND 6 VOD 7
RB 8 10 9
Blue
Red
No connection No connection No connection Shift register clock 1 Shift register clock 2
NC 10 NC 11 NC 12
27 NC 26 NC 25 NC 24 2 23 1 22 TG1
7300 7300 7300
No connection No connection No connection Shift register clock 2 Shift register clock 1 Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green) No connection No connection
1 13 2 14
Transfer gate clock 3 (for Red) TG3 15 Ground No connection No connection GND 16 NC 17 NC 18
21 TG2 20 NC 19 NC
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
10 m
7 m 3 m
Blue photocell array 4 lines (40 m)
10 m
Channel stopper
10 m
Green photocell array 4 lines (40 m)
10 m
Aluminum shield
Red photocell array
4
Data Sheet S14664EJ1V0DS00
PD3788
ABSOLUTE MAXIMUM RATINGS (TA = +25 C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature VOD V1, V1L, V10, V2, V20 VRB VCLB VTG1 to VTG3 TA Tstg Symbol Ratings -0.3 to +15 -0.3 to +8 -0.3 to +8 -0.3 to +8 -0.3 to +8 -25 to +60 -40 to +100 Unit V V V V V C C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high levelNote VOD V1H, V1LH, V10H, V2H, V20H V1L, V1LL, V10L, V2L, V20L VRBH VRBL VCLBH VCLBL VTG1H to VTG3H Symbol MIN. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.5 TYP. 12.0 5.0 0 5.0 0 5.0 0 V1H (V10H) 0 2 MAX. 12.6 5.5 +0.5 5.5 +0.5 5.5 +0.5 V1H (V10H) +0.5 40 Unit V V V V V V V V
Transfer gate clock low level Data rate
VTG1L to VTG3L 2fRB
-0.3 -
V MHz
Note
When Transfer gate clock high level (VTG1H to VTG3H) is higher than Shift register clock high level (V1H (V10H)), Image lag can increase.
Remark Pin 9 (10) and pin 28 (20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
Data Sheet S14664EJ1V0DS00
5
PD3788
ELECTRICAL CHARACTERISTICS
TA = +25 C, VOD = 12 V, fRB = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) +HA-50 (heat absorbing filter, t = 3mm)
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal
Note 1
Symbol Vsat SER SEG SEB PRNU ADS1 ADS2
Test Conditions
MIN. 1.5
TYP. 2.0 0.36 0.37 0.80
MAX. -
Unit V lx*s lx*s lx*s
VOUT = 1 V Light shielding
6 1.0 0.5
18 5.0 5.0 5.0 5.0 800 0.5 7.15 7.02 3.25 5.0 5.0 6.0
% mV mV mV mV mW k V/lx*s V/lx*s V/lx*s % % V ns
Dark signal non-uniformity
Note 1
DSNU1 DSNU2
Light shielding
2.0 1.0 600 0.3 3.85 3.78 1.75 5.5 5.4 2.5 2.0 1.0 4.0 5.0 20 0 95 98
Power consumption Output impedance Response Red Green Blue Image lag
Note 1
PW ZO RR RG RB IL1 IL2 VOUT = 1 V
Offset level
Note 2 Note 3
VOS td RI TTE VOUT = 1 V VOUT = 1 V VOUT = 1 V, data rate = 40 MHz
Output fall delay time Register imbalance
4.0
% %
Total transfer efficiency
Response peak
Red Green Blue
645 540 445 DR11 DR12 DR21 DR22 Vsat/DSNU1 Vsat/DSNU2 Vsat/bit1 Vsat/bit2 Light shielding Light shielding, bit clamp mode (tcp = 20 ns) Light shielding, line clamp mode (t19 = 3 s) -500 - - - - 1000 2000 2000 4000 +200 1.0 0.5 4.0 2.0 +500 - - - -
nm nm nm times times times times mV mV mV mV mV
Dynamic range
Note 1
Reset feed-through noise Random noise
Note 1
Note 2
RFTN bit1 bit2 line1 line2
Notes 1. ADS1, DSNU1, IL1, DR11, DR21, bit1 and line1 show the specification of VOUT1 and VOUT2. ADS2, DSNU2, IL2, DR12, DR22, bit2 and line2 show the specification of VOUT3 to VOUT6. 2. Refer to TIMING CHART 2, 5. 3. When the fall time of 1L (t2') is the TYP. value (refer to TIMING CHART 2, 5).
6
Data Sheet S14664EJ1V0DS00
PD3788
INPUT PIN CAPACITANCE (TA = +25 C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Symbol Pin name Pin No. C1 MIN. TYP. 350 350 350 350 350 350 10 10 10 100 100 100 MAX. 500 500 500 500 500 500 Unit pF pF pF pF pF pF pF pF pF pF pF pF
1
13 23
10
Shift register clock pin capacitance 2 C2
9 14 24
2
20
Last stage shift register clock pin capacitance Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance CL CRB CCLB CTG
28 29 8 30 22 21 15
1L RB CLB TG1 TG2 TG3
Remark Pins 13, 23 (1) and pin 9 (10) are connected each other inside of the device. Pins 14, 24 (2) and pin 28 (20) are connected each other inside of the device.
Data Sheet S14664EJ1V0DS00
7
7425 7427 7429 7431 7433
VOUT1, 3, 5
7426 7428 7430 7432 7434
VOUT2, 4, 6
Optical black (96 pixels) Invalid photocell (6 pixels)
Valid photocell (7300 pixels) Invalid photocell (6 pixels)
7436 7438
120 122
124 126 128
130
132
2 4 6 8 10 12 14
16 18 20
22
24 26
28 30
7435 7437
119 121
123 125 127
129
131
1 3 5 7 9 11 13
15 17 19
21
23 25
27 29
8
Data Sheet S14664EJ1V0DS00
TIMING CHART 1 (Bit clamp mode, for each color)
TG1 to TG3
1 ( 10)
2 ( 20) 1L
RB
CLB
Note Note
PD3788
Note
Input the RB and CLB pulses continuously during this period, too.
PD3788
TIMING CHART 2 (Bit clamp mode, for each color)
t1
t2
1 ( 10)
10 %
90 %
2 ( 20)
90 % 10 % 90 % 10 % t1' 90 % 10 % t5 t3 t10 t8 90 % 10 % td tcp t9 t7 t11 t6 t4 t2'
1L
RB
CLB
VOUT1 to VOUT6
RFTN
VOS 10 %
Symbol t1, t2 t1', t2' t3 t4 t5, t6 t7 t8, t9 t10 t11 tcp
MIN. 0 0 17 5 0 17 0 -20Note 1 -5Note 2 5
TYP. 50 5 50 200 20 150 20 +50 +50 150
MAX.
Unit ns ns ns
-
ns ns ns ns
-
ns ns ns
Data Sheet S14664EJ1V0DS00
9
PD3788
Notes 1. MIN. of t10 shows that the RB and CLB overlap each other.
RB
90 %
t10
CLB
90 %
2. MIN. of t11 shows that the 1L and CLB overlap each other.
1L
90 %
CLB
t11
90 %
10
Data Sheet S14664EJ1V0DS00
PD3788
TIMING CHART 3 (Bit clamp mode, for each color)
t13 90 % 10 % t15 t16 t12 t14
TG1 to TG3
1 ( 10) 2 ( 20)
90 %
1L RB CLB
Note 1
90 %
t11 90 %
Symbol t11 t12 t13, t14 t15, t16
MIN. -5Note 2 3000 0 900
TYP. +50 10000 50 1000
MAX.
Unit ns ns ns ns
Notes 1. Input the RB and CLB pulses continuously during this period, too. 2. MIN. of t11 shows that the 1L and CLB overlap each other.
1L
90 %
t11
CLB
90 %
1 (10), 2 (20) cross points
1L, 2 (20) cross points
1 ( 10)
2 ( 20)
2 V or more
2 ( 20)
2 V or more
1L
2 V or more
0.5 V or more
Remark
Adjust cross points (1 (10), 2 (20)) and (1L, 2 (20)) with input resistance of each pin.
Data Sheet S14664EJ1V0DS00
11
VOUT1, 3, 5
VOUT2, 4, 6
Optical black (96 pixels)
Valid photocell (7300 pixels) Invalid photocell (6 pixels) Invalid photocell (6 pixels)
Note
Set the RB to high level during this period.
7426 7428 7430 7432 7434 7436 7438
120 122
124 126 128
130
132
2 4 6 8 10 12 14
16 18 20
22
24 26 28 30
7425 7427 7429 7431 7433 7435 7437
119 121
123 125 127
129
131
1 3 5 7 9 11 13
15 17 19
21
23 25 27 29
12
Data Sheet S14664EJ1V0DS00
TIMING CHART 4 (Line clamp mode, for each color)
TG1 to TG3
1 ( 10)
2 ( 20) 1L
RB
CLB
Note Note
PD3788
Remark Inverse pulse of the TG1 to TG3 can be used as CLB.
PD3788
TIMING CHART 5 (Line clamp mode, for each color)
t1
t2
1( 10)
10 %
90 %
2( 20)
90 % 10 % 90 % 10 % t1' 90 % t5 t3 t6 t4 t2'
1L
RB
10 % "H"
CLB
td VOUT1 to VOUT6
RFTN
VOS 10 %
Symbol t1, t2 t1', t2' t3 t4 t5, t6
MIN. 0 0 17 5 0
TYP. 50 5 50 200 20
MAX.
Unit ns ns ns
-
ns ns
Data Sheet S14664EJ1V0DS00
13
PD3788
TIMING CHART 6 (Line clamp mode, for each color)
t13 90 % 10 % t15
t12
t14
TG1 to TG3
t16
1 ( 10) 2 ( 20)
90 %
1L RB CLB
90 % Note
t17 90 % 10 % t20
t18
t19
t21
Symbol t12 t13, t14 t15, t16 t17, t18 t19 t20, t21
MIN. 3000 0 900 100 200 0
TYP. 10000 50 1000 1000 t12 20
MAX.
Unit ns ns ns ns ns ns
Note
Set the RB to high level during this period.
Remark Inverse pulse of the TG1 to TG3 can be used as CLB.
1 (10), 2 (20) cross points
1 ( 10)
1L, 2 (20) cross points
2 ( 20)
2 V or more
2 V or more
2 V or more
0.5 V or more
2 ( 20)
1L
Remark Adjust cross points (1 (10), 2 (20)) and (1L, 2 (20)) with input resistance of each pin.
14
Data Sheet S14664EJ1V0DS00
PD3788
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
PRNU (%) = x x 100 x x : maximum of xj - x
7300 j=1
xj
7300
x=
xj : Output voltage of valid pixel number j
VOUT
Register Dark DC level
x x
4.
Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
7300 j=1
dj
7300 dj : Dark signal of valid pixel number j
ADS (mV) =
Data Sheet S14664EJ1V0DS00
15
PD3788
5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of dj - ADS j = 1 to 7300 dj : Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
6.
Output impedance: ZO Impedance of the output pins viewed from outside.
7.
Response: R Output voltage divided by exposure (Ix*s). Note that the response varies with a light source (spectral characteristic).
8.
Image lag: IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light
ON
OFF
VOUT V1 VOUT
V1 IL (%) = VOUT
x100
16
Data Sheet S14664EJ1V0DS00
PD3788
9. Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
n
2 n RI (%) =
(V2j - 1 - V2j)
j= 1
2
1 n
Vj
j= 1
n
x 100
n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise: Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding).
100
(mV) =
(Vi - V)
i=1
2
, V=
1
100
100
100 i=1
Vi
Vi: A valid pixel output signal among all of the valid pixels for each color
VOUT
V1 V2
line 1 line 2
V100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
Data Sheet S14664EJ1V0DS00
...
line 100
...
17
PD3788
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 C)
4 Relative Output Voltage Relative Output Voltage 10 20 30 40 50 1
2
1
0.5
0.25
0.2
0.1 0
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA(C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25 C) 100 B R G 80
Response Ratio (%)
60
40
B
20
G
0 400
500
600 Wavelength (nm)
700
800
18
Data Sheet S14664EJ1V0DS00
PD3788
APPLICATION CIRCUIT EXAMPLE
+5 V 10 + 10 F/16 V 0.1 F
B4
+12 V
PD3788
1 2
B6
+ 36 35 34 33 32 31 30 29 28 47 47 2
B2 B1 B3
VOUT4 GND VOUT6 GND VOUT5 GND VOD
VOUT3 GND VOUT1 GND VOUT2 GND
0.1 F 47 F/25 V
+5 V
3 4
+ 0.1 F 10 F/16 V
B5
5 6 7
RB
47 2
CLB 1L 20
CLB
8 9
RB 10
10 11 12 2 13 14 15 16 17 18
NC NC NC
NC NC NC
27 26 25 24 23 22 21 20 19 2 2 2 2
2
2 2
1 2 TG3
GND NC NC
2 1 TG1 TG2
NC NC
1 TG
Remarks 1. Pin 9 (10) and pin 28 (20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so. 2. The inverters shown in the above application circuit example are the 74AC04.
Data Sheet S14664EJ1V0DS00
19
PD3788
B1 to B6 EQUIVALENT CIRCUIT
+12 V 47 F/25 V +
0.1 F
4.7 k 110 CCD VOUT 47 2SA1005 1 k 2SC945
20
Data Sheet S14664EJ1V0DS00
PD3788
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24mm (600))
(Unit : mm)
94.000.50 9.50.9
1
(35.0) The 1st valid pixel
2
14.990.3
15.24 (4.33) 1.270.05 (2.33)
3
0.460.05 88.90.6
2.54 20.32 2.00.3
4
0.250.05 3.500.5 0.970.3 3.300.35
Name Glass cap 1 The 1st valid pixel 2 The 1st valid pixel 3 The surface of the chip 4 The bottom of the package
Dimensions 93.0 x 13.6 x 1.0
Refractive index 1.5
The center of the pin1 The center of the package (Reference) The top of the glass cap (Reference) The surface of the chip
36D-1CCD-PKG1-2
Data Sheet S14664EJ1V0DS00
21
PD3788
NOTES ON THE USE OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. When mounting the package, use a circuit board which will not subject the package to bending stress, or use a socket. For this product, the reference value for the three-point bending strengthNote is 300 [N]. Avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). Note Three-point bending strength test Distance between supports: 70 mm, Support R: R 2 mm, Loading rate: 0.5 mm / min.
Load
Load
70 mm
70 mm
22
Data Sheet S14664EJ1V0DS00
PD3788
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14664EJ1V0DS00
23
PD3788
* The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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