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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT373 Octal D-type transparent latch; 3-state Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state FEATURES * 3-state non-inverting outputs for bus oriented applications * Common 3-state output enable input * Functionally identical to the "563", "573" and "533" * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT373 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT373 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT373 input and an output enable (OE) input are common to all latches. The "373" consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. The "373" is functionally identical to the "533", "563" and "573", but the "563" and "533" have inverted outputs and the "563" and "573" have a different pin arrangement. TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay Dn to Qn LE to Qn CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per latch notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 12 15 3.5 45 14 13 3.5 41 ns ns pF pF HCT UNIT September 1993 2 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state PIN DESCRIPTION PIN NO. 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 SYMBOL OE Q0 to Q7 D0 to D7 GND LE VCC NAME AND FUNCTION 74HC/HCT373 3-state output enable input (active LOW) 3-state latch outputs data inputs ground (0 V) latch enable input (active HIGH) positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. September 1993 3 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state FUNCTION TABLE INPUTS OPERATING MODES OE LE Dn enable and read register (transparent mode) latch and read register latch register and disable outputs Fig.4 Functional diagram. Notes L L H H L H 74HC/HCT373 INTERNAL LATCHES L H OUTPUTS Q0 to Q7 L H L L H H L L X X l h X X L H X X L H Z Z 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition X = don't care Z = high impedance OFF-state Fig.5 Logic diagram (one latch). Fig.6 Logic diagram. September 1993 4 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. 225 45 38 265 53 45 225 45 38 225 45 38 90 18 15 120 24 20 75 15 13 5 5 5 ns 74HC/HCT373 TEST CONDITIONS UNIT V WAVEFORMS CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 min. typ. max. min. max. min. tPHL/ tPLH propagation delay Dn to Qn propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time 41 15 12 50 18 14 44 16 13 47 17 14 14 5 4 80 16 14 50 10 9 5 5 5 17 6 5 14 5 4 -8 -3 -2 150 30 26 175 35 30 150 30 26 150 30 26 60 12 10 100 20 17 65 13 11 5 5 5 190 38 33 220 44 37 190 38 33 190 38 33 75 15 13 tPHL/ tPLH ns Fig.8 tPZH/ tPZL ns Fig.9 tPHZ/ tPLZ ns Fig.9 tTHL/ tTLH ns Fig.7 tW LE pulse width HIGH set-up time Dn to LE hold time Dn to LE ns Fig.8 tsu ns Fig.10 th ns Fig.10 September 1993 5 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT373 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT Dn LE OE UNIT LOAD COEFFICIENT 0.30 1.50 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. 45 48 48 45 18 24 18 4 ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.8 Fig.9 Fig.9 Fig.7 Fig.8 Fig.10 Fig.10 UNIT V WAVEFORMS CC (V) TEST CONDITIONS min. typ. max. min. max. min. tPHL/ tPLH tPHL/ tPLH tPZH/ tPZL tPHZ/ tPLZ tTHL/ tTLH tW tsu th propagation delay Dn to Qn propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time LE pulse width HIGH set-up time Dn to LE hold time Dn to LE 16 12 4 17 16 19 18 5 4 6 -1 30 32 32 30 12 20 15 4 38 40 40 38 15 September 1993 6 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state AC WAVEFORMS 74HC/HCT373 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.8 Fig.7 Waveforms showing the input (Dn) to output (Qn) propagation delays and the output transition times. Waveforms showing the latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the 3-state enable and disable times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the data set-up and hold times for Dn input to LE input. September 1993 7 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". 74HC/HCT373 September 1993 8 |
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