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1CY 622 56 V
fax id: 1069
PRELIMINARY
CY62256V
32K x 8 Static RAM
Features
* * * * * * * * 55, 70 ns access time CMOS for optimum speed/power Wide voltage range: 2.7V-3.6V Low active power (70 ns, LL version) -- 108 mW (max.) Low standby power (70 ns, LL version) -- 18 W (max.) Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 98% when deselected. The CY62256V is in the standard 450-mil-wide (300-mil body width) SOIC, TSOP, and reverse TSOP packages. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to ensure alpha immunity.
Functional Description
The CY62256V is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active
Logic Block Diagram
Pin Configurations
SOIC Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
C62256V-2
INPUT BUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE
C62256V-1
I/O0 I/O1 I/O2
512x512 Y ARRA
I/O3 I/O4 I/O5
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 March 1996 - Revised May 1996
PRELIMINARY
Pin Configurations (continued)
TSOP Top View OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11
22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8
CY62256V
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12
C62256V-3
TSOP Reversed Top View A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE
7 6 5 4 3 2 1 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21
A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0
C62256V-4
Selection Guide
CY62256V-55 Maximum Access Time (ns) Maximum Operating Current (mA) L LL Maximum Standby Current (A) L LL
Shaded area contains advanced information.
CY62256V-70 70 50 50 30 500 50 5
55 50 50 30 500 50 5
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied................................................... 0C to +70C Supply Voltage to Ground Potential (Pin 28 to Pin 14).................................................-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................... -0.5V to VCC + 0.5V
DC Input Voltage[1].................................... -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 2.7V to 3.6V
Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns.
2
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY62256V-55 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[2] VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.5 -1 -5 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 -200 50 L LL L LL ISB2 Automatic CE Power-Down Current-- CMOS Inputs L LL 50 30 5 3 1 500 50 5 2.2 -0.5 -1 -5 Max.
CY62256V
CY62256V-70 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 -200 50 50 30 5 3 1 500 50 5 Max. Unit V V V V A A mA mA mA mA mA mA mA A A A
ISB1
Automatic CE Power-Down Current-- TTL Inputs
Shaded area contains advanced information.
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Max. 6 8 Unit pF pF
Notes: 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
1.1k 3V OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 1.55k 3.0V 10% GND < 5 ns ALL INPUT PULSES 90% 90% 10% < 5 ns
C62256V-6
C62256V-5
Equivalent to:
THEVENIN EQUIVALENT 643 1.75V
OUTPUT
3
PRELIMINARY
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current L LL tCDR[3] tR[3] Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 3.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0 tRC Conditions[4] Min. 2.0
CY62256V
Max. 200 20 5
Unit V A A A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE
C62256V-7
VDR > 2V
3.0V tR
Switching Characteristics Over the Operating Range[5]
CY62256V-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] OE HIGH to High CE LOW to Low CE HIGH to High Z[6, 7] 3 20 0 55 0 70 Z[6, 7] Z[6] 3 20 3 25 3 55 25 3 25 55 55 3 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. CY62256V-70 Min. Max. Unit
CE LOW to Power-Up CE HIGH to Power-Down
Shaded area contains advanced information. Notes: 4. No input may exceed VCC+0.3V. 5. Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
4
PRELIMINARY
Switching Characteristics Over the Operating Range[5] (continued)
CY62256V-55 Parameter WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[8,9]
CY62256V
CY62256V-70 Min. 70 60 60 0 0 50 30 0 Max. Unit ns ns ns ns ns ns ns ns 25 3 ns ns
Description Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[6, 7] WE HIGH to Low Z[6]
Min. 55 45 45 0 0 40 25 0
Max.
20 3
Shaded area contains advanced information.
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C62256V-8
[10, 11]
Read Cycle No. 2 [11, 12]
t RC
CE tACE OE tDOE t LZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT t PU 50%
t HZOE tHZCE DATA VALID t PD
HIGH IMPEDANCE
DATA OUT
ICC 50% ISB
C62256V-9
Notes: 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW.
5
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
[8, 13, 14]
CY62256V
tWC ADDRESS
CE tAW WE tSA t PWE tHA
OE tSD DATA I/O NOTE 15 t HZOE DATAINVALID
C62256V-10
tHD
Write Cycle No. 2 (CE Controlled) [8, 13, 14]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAINVALID
C62256V-11
tSCE
tHA
t HD
Write Cycle No. 3 (WE Controlled, OE LOW)
[ 9, 14]
tWC ADDRESS
CE tAW WE tSA t HA
tSD DATA I/O NOTE 15 t HZWE
Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied.
t HD
DATA INVALID tLZWE
C62256V-12
6
PRELIMINARY
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 2.70 I SB 3.00 3.30 3.60 3.90 VIN =3.3V TA =25C I CC 1.40 1.20 1.00 0.80 30.00 0.60 0.40 0.20 V CC =3.3V V IN =3.3V 20.00 10.00 2.00 I CC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE
CY62256V
OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 50.00 40.00 VCC =3.3V TA =25C
SUPPLY VOLTAGE (V)
I SB 0.00 -55.00 40.00 135.00 AMBIENT TEMPERATURE (C)
2.25
2.50
2.75
3.00
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.40 1.30 1.20 1.10 TA =25C 1.00 0.90 0.80 2.70 1.00 1.40 1.30 1.20
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 10.00 8.00 6.00
1.10 4.00 V CC =3.3V 0.90 0.80 -55.00 2.00 0.00 0.00
3.00
3.30
3.60
3.90
40.00
135.00
0.06
0.12
0.18
0.24
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 2.5 2.0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 2.50 2.00 1.50
NORMALIZED I CC vs. CYCLE TIME 1.30 1.20 1.10 1.00 0.90 0.80 29.00 VCC =3.3V TA =25C VIN =0.3V
1.5 1.00 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 0.50 0.00 0.00 VCC =3.0V TA =25C
33.00 CAPACITANCE (pF)
66.00
47.00
65.00
83.00
SUPPLY VOLTAGE (V)
CYCLE FREQUENCY (MHz)
7
PRELIMINARY
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, Output Disabled Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
CY62256V
Ordering Information
Speed (ns) 55 Ordering Code CY62256V-55SNC CY62256VL-55SNC CY62256VLL-55SNC CY62256V-55RZC CY62256VL-55RZC CY62256VLL-55RZC CY62256V-55ZC CY62256VL-55ZC CY62256VLL-55ZC 70 CY62256V-70SNC CY62256VL-70SNC CY62256VLL-70SNC CY62256V-70RZC CY62256VL-70RZC CY62256VLL-70RZC CY62256V-70ZC CY62256VL-70ZC CY62256VLL-70ZC
Shaded area contains advanced information.
Package Name S22 S22 S22 RZ28 RZ28 RZ28 Z28 Z28 Z28 S22 S22 S22 RZ28 RZ28 RZ28 Z28 Z28 Z28
Package Type 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead Reverse Thin Small Outline Package 28-Lead Reverse Thin Small Outline Package 28-Lead Reverse Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead 450-Mil (300-Mil Body Width) SOIC 28-Lead Reverse Thin Small Outline Package 28-Lead Reverse Thin Small Outline Package 28-Lead Reverse Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package
Operating Range Commercial
Commercial
Document #: 38-00519
8
PRELIMINARY
Package Diagrams
28-Lead 450-Mil (300-Mil Body Width) SOIC S22
CY62256V
28-Lead Reverse Thin Small Outline Package RZ28
9
PRELIMINARY
Package Diagrams (continued)
28-Lead Thin Small Outline Package Z28
CY62256V
(c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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