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IMP1 832
POWER MANAGEMENT
3.3V P Power Supply Monitor and Reset Circuit
Key Features
x Pin compatible with the Dallas Semiconductor DS1832 -- Over 40% lower supply current x 3.3V supply monitor x Push-pull output x Selectable watchdog period x Debounce manual push-button reset input x Precision temperature-compensated voltage reference and comparator x Power-up, power-down and brownout detection x 250ms minimum reset time x Active LOW and HIGH reset signal x Selectable trip point tolerance: 10% or 20% x Low-cost 8-pin DIP/SO and 8-pin MicroSO packages x Wide operating temperature - 40C to +85C
- Selectable Trip -Point Tolerance and Watchdog Period - Push-Button Reset - Push-Pull Reset Outputs
The IMP1832 microprocessor supervisor can halt and restart a "hungup" or "stalled" microprocessor, restart a microprocessor after a power failure, and debounce a manual push-button microprocessor reset switch. The IMP1832 features over 40% lower supply current than the pin compatible Dallas Semiconductor DS1832.
Precision temperature compensated reference and comparator circuits monitor the 3.3V, VCC input voltage. During power-up or when the VCC power supply falls outside selectable tolerance limits, both RESET and RESET become active. When VCC rises above the threshold voltage, the reset signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to stabilize. The trip point Also included is a watchdog timer to stop and restart a tolerance signal, TOL, selects the trip level tolerance to be either 10- or microprocessor that is "hung-up". Three watchdog time20-percent. out periods are selectable: 150ms, 610ms and 1,200ms. If the ST input is not strobed LOW before the time-out period RESET and RESET outputs are push-pull. expires, a reset is issued. A debounced manual reset input, PBRST, activates the reset outputs for Devices are available in 8-pin DIP, 8-pin SO and compact a minimum period of 250ms. 8-pin MicroSO packages.
Block Diagram
VCC 8
IMP1832
10%/20% Tolerance Selection
VCC
TOL
3
6
RESET
+
VCC VCC Reference
-
5 RESET
40k9 PBRST 1 Push Button Debounce Watchdog Timebase Selection Watchdog Transition Detector 4 Reset & Watchdog Timer
TD
2
ST
7
1832_02.eps
GND
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
1
IMP1 832
Pin Configuration
DIP/SO/MicroSO
PBRST 1 TD 2 TOL 3 GND 4 IMP1832 8 VCC 7 ST 6 RESET 5 RESET
1832_01.eps
Pin Descriptions
Pin Number 8-Pin Package
1 2 3 4 5
Name
PBRST TD TOL GND RESET
Function
Debounced manual pushbutton reset input Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms for TD = Open, and tTD =1200ms for TD = VCC) Selects 10% (TOL connected to GND) or 20% (TOL connected to VCC) trip point tolerance Ground Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. Active LOW reset output. (See RESET) Strobe Input 5V power
6 7 8
RESET ST VCC
Ordering Information
Part Number
IMP1832 IMP1832S IMP1832SEMA
Package
8-DIP 8-SO 8-MicroSO
Operating Temperature Range
- 40C to 85C - 40C to 85C - 40C to 85C
Maximum Supply Current (A)
20 20 20
Voltage Monitoring Application
3.3V 3.3V 3.3V
1832_t01.eps
2
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(c) 1999 IMP, Inc.
IMP1 832
Absolute Maximum Ratings
Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Voltage on ST, TD . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V Voltage on PBRST, RESET, RESET . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature Range . . . . . . . . . . . -40C to 85C Voltages measured with respect to ground. These are stress ratings only and functional operation is not implied. Soldering Temperature . . . . . . . . . . . . . . . . . . 260C for 10 seconds Storage Temperature . . . . . . . . . . . . . . . . . . . -55C to 125C
Electrical Characteristics
Unless otherwise stated, 1.2V VCC 5.5V and over the operating temperature range of -40C to +85C . All voltages are referenced to ground.
Parameter
Supply Voltage (VCC) ST and PBRST Input High Level ST and PBRST Input High Level ST and PBRST Input Low Level VCC Trip Point (TOL = GND) VCC Trip Point (TOL = VCC) Watchdog Time-Out Period Watchdog Time-Out Period Watchdog Time-Out Period Output Voltage Output Current Output Current Input Leakage RESET Low Level Internal Pull-Up Resistor Operating Current Input Capacitance Output Capacitance PBRST Manual Reset Minimum Low Time Reset Active Time ST Pulse Width VCC Fail Detect to RESET or RESET VCC Slew Rate PBRST Stable LOW to RESET and RESET Active VCC Detect to RESET or RESET Inactive VCC Slew Rate
Symbol
VCC VIH VIH VIL VCCTP VCCTP tTD tTD tTD VOH IOH IOL IIL VOL
Conditions
VCC 2.7V VCC < 2.7V
Min
1.0 2 VCC - 0.4V - 0.3 2.80 2.47
Typ
Max
5.5 VCC + 0.3V 0.5
Units
V V V V V V ms ms ms V A mA
2.88 2.55 150 1200 610 VCC - 0.1V 350
2.97 2.64 250 2000 1000
TD = GND TD = VCC TD floating I = -500A, VCC < 2.7V Output = 2.4V, VCC 2.7V Output = 0.4V, VCC 2.7V
62.5 500 250 VCC - 0.3V 10 -1.0
1.0 0.4 40 20 5 7
A V k A pF pF ms
PBRST pin ICC1 CIN COUT tPB tRST tST tRPD tF tPDLY tRPU tR trise = 5s 250 0 Must not exceed tRD minimum. Watchdog cannot be disabled. Pulses < 2s at VCCTP minimum will not cause reset. 20 PBRST = VIL 20 250 20 Outputs open. VCC 3.6V and all inputs at VCC or GND
610
1000
ms ns
5
8
s s
20 610 1000
ms ms ns
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
3
IMP1 832
Application Information
Supply Voltage Monitor
The IMP1832 monitors the microprocessor or microcontroller power supply and issues reset signals, both active HIGH and active LOW, that halt processor operation whenever the power supply voltage levels are outside a predetermined tolerance. Tolerance levels are set with the TOL pin. RESET and RESET signals are generated at the last moment of a valid VCC signal. On power-up, both reset signals are active for a minimum of 250ms after the supply has returned to intolerance level. This allows the power supply and monitored processor to stabilize before instruction execution is allowed to begin. Trip Point Tolerance Selection With TOL connected to VCC, RESET and RESET become active whenever VCC falls below 2.64V. RESET and RESET become active when VCC falls below 2.98V if TOL is connected to ground. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. On power-down, once VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or less until VCC drops below 1.2V. The active HIGH reset signal is valid down to a VCC level of 1.2V also.
Tolerance Select
TOL = VCC TOL = GND
TRIP Point Voltage (V) Tolerance
20% 10%
Min
2.47 2.80
Nominal
2.55 2.88
Max
2.64 2.97
1832 t02.eps
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset signals. The pushbutton input is debounced and is pulled HIGH through an internal 40k resistor. When PBRST is held LOW for the minimum time tPB , both resets become active and remain active for a minimum time period of 250ms after PBRST returns HIGH. The debounced input is guaranteed to recognize pulses greater than 20ms. No external pull-up resistor is required, since PBRST is pulled HIGH by an internal 40k resistor. The PBRST can be driven from a TTL or CMOS logic line or shorted to ground with a mechanical switch.
tR VCCTP(MAX) VCCTP
VCCTP(MIN)
VCC
tRPU RESET VOH VIL VOL RESET
1832_04.eps
PBRST
tPB tPDLY VIH
tRST RESET RESET VOH VOL
1832_07.eps
Figure 1. Timing Diagram: Power Up
tF VCC VCCTP(MAX) VCCTP
Figure 3. Timing Diagram: Pushbutton Reset
Supply Voltage IMP1832 1 PBRST TD TOL GND VCC ST RESET RESET 8 7 6 5 P
VCCTP(MIN)
RESET
tRPD
2 3
RESET
VOH VOL
1832_03.eps
4
RESET
1832_05.eps
Figure 2. Timing Diagram: Power Down
4
Figure 4. Application Circuit: Pushbutton Reset
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
IMP1 832
Application Information
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is "hung-up". Through the time delay input, TD, three watchdog time-out periods are selectable: 150ms, 610ms and 1,200ms. If the strobe input, ST, is not strobed LOW prior to timeout, reset signals become active. On power-up or after the supply voltage returns to an in-tolerance condition, the reset signal remains active for 250ms minimum, allowing the power supply and system microprocessor to stabilize. ST Pulses as short as 20ns can be detected.
Valid Strobe Valid Strobe Invalid Strobe
A HIGH-to-LOW ST signal transition must be regularly issued no later than the minimum time-out period defined by the state of the TD signal. This guarantees the watchdog timer does not time-out. Timeouts periods of approximately 150ms, 610ms or 1,200ms are selected through the TD pin.
TD Voltage Level
GND Floating VCC
Watchdog Time-Out Period (ms) Min
62.5 250 500
Nominal
150 610 1200
Max
250 1000 2000
1832_t03.eps
ST
tST tRST RESET tTD (Min) tTD (Max)
1832_08.eps
The watchdog timer can not be disabled. It must be strobed with a high-to-low transition to avoid a watchdog timeout and reset.
Note: ST is ignored whenever a reset is active.
Figure 5. Timing Diagram: Strobe Input
Supply Voltage IMP1832 1 2 3 4 PBRST TD TOL GND VCC ST RESET RESET 8 7 6 5
1832_06.eps
MREQ
mP
RESET
Address Bus
Decoder
Figure 6. Application Circuit: Watchdog Timer
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
5
IMP1 832
Package Dimensions
MicroSO (8-Pin)
a
Inches Min
A A1 A2 b C D e E E1 L a A A1 B C e E H L D
Millimeters Max Min Max MicroSO (8-Pin)*
E1 E
L D A2 A e b A1
0.10mm 0.004in
C
----- 0.0433 0.0020 0.0059 0.0295 0.0374 0.0098 0.0157 0.0051 0.0091 0.1142 0.1220 0.0256 BSC 0.193 BSC 0.1142 0.1220 0.0157 0.0276 0 6 0.053 0.004 0.013 0.007 0.050 0.150 0.228 0.016 0.189 0.157 0.244 0.050 0.197 0.069 0.010 0.020 0.010
---- 1.10 0.050 0.15 0.75 0.95 0.25 0.40 0.13 0.23 2.90 3.10 0.65 BSC 4.90 BSC 2.90 3.10 0.40 0.70 0 6 1.35 0.10 0.33 0.19 1.27 3.80 5.80 0.40 4.80 ---- 0.38 2.92 0.36 1.14 0.80 9.02 0.13 7.62 6.10 2.54 7.62 ----- 2.92 10.92 3.81
1832_t04.at3
D
+
MicroSO (8-Pin).eps
SO (8-Pin)**
1.75 0.25 0.51 0.25 4.00 6.20 1.27 2.00 5.33 ----- 4.95 0.56 1.78 1.14 10.16 ----- 8.26 7.11
SO (8-Pin)
0- 8
L
E
H
Plastic DIP (8-Pin)***
A ----- 0.210 A1 0.015 ----- A2 0.115 0.195 b 0.014 0.022 b2 0.045 0.070 b3 0.030 0.045 D 0.355 0.400 D1 0.005 ----- E 0.300 0.325 E1 0.240 0.280 e 0.100 ----- eA 0.300 ----- eB ----- 0.430 eC ----- 0.060 L 0.115 0.150 *** JEDEC Drawing MO-187AA *** JEDEC Drawing MS-112AA *** JEDEC Drawing MS-001BA
C D A
e B A1
SO (8-Pin).eps
Plastic DIP (8-Pin)
D1
E D A A2 E1
L A1 e b b2
0-15 C eA eB
Plastic DIP (8-Pin)a.eps
6
408-432-9100/www.impweb.com
(c) 1999 IMP, Inc.
IMP1 832
IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners.
(c) 1999 IMP, Inc. Printed in USA Publication #: 1015 Revision: B Issue Date: 11/08/99 Type: Preliminary

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