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KM684000C Family
Document Title
512Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0 1.0
History
Initial draft Finalize
Draft Date
October 20,1998 April 12, 1999
Remark
Preliminary Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.0 April 1999
KM684000C Family
512Kx8 bit Low Power CMOS Static RAM
FEATURES
* Process Technology: TFT * Organization: 512Kx8 * Power Supply Voltage: 4.5~5.5V * Low Data Retention Voltage: 2V(Min) * Three state output and TTL Compatible * Package Type: 32-DIP-600, 32-SOP-525, 32-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The KM684000C families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature ranges and various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Max) 80A 4.5~5.5V Inderstrial (-40~85C) 551)/70ns 20A 100A 30A 55mA 32-SOP 32-TSOP2-F/R Operating (ICC2, Max) PKG Type
KM684000CL KM684000CL-L KM684000CLI KM684000CLI-L
Commercial (0~70C)
32-DIP,32-SOP 32-TSOP2-F/R
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27
FUNCTIONAL BLOCK DIAGRAM
VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6
VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O1 I/O8
Clk gen.
Precharge circuit.
32-DIP 32-SOP 32-TSOP2 (Forward)
26 25 24 23 22 21 20 19 18 17
32-TSOP2 (Reverse)
7 8 9 10 11 12 13 14 15 16
Row select
Memory array 1024 rows 512x8 columns
Data cont
I/O Circuit Column select
Data cont
Pin Name WE CS OE A0~A18 I/O1~I/O8 Vcc Vss
Function Write Enable Input Chip Select Input Output Enable Input Address Inputs Data Inputs/Outputs Power Ground
CS WE OE
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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Revision 1.0 April 1999
KM684000C Family
PRODUCT LIST
Commercial Temperature Products(0~70C) Part Name KM684000CLP-5 KM684000CLP-5L KM684000CLP-7 KM684000CLP-7L KM684000CLG-5 KM684000CLG-5L KM684000CLG-7 KM684000CLG-7L KM684000CLT-5L KM684000CLT-7L KM684000CLR-5L KM684000CLR-7L Function 32-DIP, 55ns, Low Power 32-DIP, 55ns, Low Low Power 32-DIP, 70ns, Low Power 32-DIP, 70ns, Low Low Power 32-SOP, 55ns, Low Power 32-SOP, 55ns, Low Low Power 32-SOP, 70ns, Low Power 32-SOP, 70ns, Low Low Power 32-TSOP2-F, 55ns, Low Low Power 32-TSOP2-F, 70ns, Low Low Power 32-TSOP2-R, 55ns, Low Low Power 32-TSOP2-R, 70ns, Low Low Power
CMOS SRAM
Industrial Temperature Products(-40~85C) Part Name KM684000CLGI-5 KM684000CLGI-5L KM684000CLGI-7 KM684000CLGI-7L KM684000CLTI-5L KM684000CLTI-7L KM684000CLRI-5L KM684000CLRI-7L Function 32-SOP, 55ns, Low Power 32-SOP, 55ns, Low Low Power 32-SOP, 70ns, Low Power 32-SOP, 70ns, Low Low Power 32-TSOP2-F, 55ns, Low Low Power 32-TSOP2-F, 70ns, Low Low Power 32-TSOP2-R, 55ns, Low Low Power 32-TSOP2-R, 70ns, Low Low Power
FUNCTIONAL DESCRIPTION
CS H L L L OE X
1)
WE X
1)
I/O Pin High-Z High-Z Dout Din
Mode Deselected Output disbaled Read Write
Power Standby Active Active Active
H L X
1)
H H L
1. X means dont care.( Must be in low or high state.)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W C C C Remark KM684000CL/L-L KM684000CLI/LI-L
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Revision 1.0 April 1999
KM684000C Family
RECOMMENDED DC OPERATING CONDITIONS 1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.53) Typ 5.0 0 -
CMOS SRAM
Max 5.5 0 Vcc+0.5 2) 0.8 Unit V V V V
Note: 1. Commercial Product : TA=0 to 70C, otherwise specified Industrial Product : TA=-40 to 85C, otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width 30ns 3. Undershoot : -3.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) VOL VOH ISB VIN=Vss to Vcc CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS=VIL, VIN=VIL or VIH, Read Cycle time=1s, 100% duty, IIO=0mA CS0.2V, VIN0.2V or VINVcc-0.2V
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
Test Conditions
Min -1 -1 2.4 KM684000CL -
Typ -
Max 1 1 10 8 55 0.4 3 80 20 100 30
Unit A A mA mA mA V V mA
IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs = VIL or VIH
Standby Current(CMOS)
ISB1
CSVcc-0.2V, Other inputs=0~Vcc
KM684000CL-L KM684000CLI KM684000CLI-L
A
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Revision 1.0 April 1999
KM684000C Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL=50pF+1TTL CL1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, KM684000C Family:TA=0 to 70C, KM684000CI Family:TA=-40 to 85C)
Speed Bins Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 55ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 70ns Max 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Symbol
VDR
Test Condition
CSVcc-0.2V KM684000CL
Min
2.0 0 5
Typ
-
Max
5.5 40 15 50 20 -
Unit
V
Data retention current
IDR
Vcc=3.0V, CSVcc-0.2V
KM684000CL-L KM684000CLI KM684000CLI-L
A
Data retention set-up time Recovery time
tSDR tRDR
See data retention waveform
ms
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Revision 1.0 April 1999
KM684000C Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO1 CS tOE OE tOLZ tLZ Data Valid tOHZ tHZ tOH
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 1.0 April 1999
KM684000C Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS tAW tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (CS
Controlled)
tWC Address tAS(3) CS tAW tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC 4.5V tSDR Data Retention Mode tRDR
2.2V VDR CSVCC - 0.2V
CS GND
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Revision 1.0 April 1999
KM684000C Family
PACKAGE DIMENSIONS
32 PIN DUAL INLINE PACKAGE (600mil)
CMOS SRAM
Units : millimeter(Inch)
0.25
+0.10 -0.05 +0.004 0.010-0.002
#32
#17
13.600.20 0.5350.008
#1 42.31 MAX 1.666 41.910.20 1.6500.008
#16 3.810.20 0.1500.008 5.08 0.200 MAX
15.24 0.600
0~15
(
1.91 ) 0.075
0.460.10 0.0180.004 1.520.10 0.0600.004
3.300.30 0.1300.012 2.54 0.100 0.38 0.015 MIN
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8 #32 #17
14.120.30 0.5560.012
11.430.20 0.4500.008
#1 20.87MAX 0.822 20.470.20 0.8060.008
#16 2.740.20 0.1080.008 3.00 0.118 MAX
13.34 0.525
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.800.20 0.0310.008
0.10 MAX 0.004 MAX
+0.100 -0.050 +0.004 0.016 -0.002
( 0.71 ) 0.028
0.41
1.27 0.050
0.05 0.002 MIN
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Revision 1.0 April 1999
KM684000C Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
CMOS SRAM
Units : millimeter(Inch)
0.25 ( 0.010 ) #32 #17
0~8
0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
#1 21.35 MAX 0.841 20.950.10 0.8250.004
#16 1.000.10 0.0390.004 1.20 0.047MAX 0.10 MAX 0.004 MAX 0.15 +0.10 -0.05 0.006 +0.004 -0.002
10.16 0.400
( 0.50 ) 0.020
( 0.95 ) 0.037
0.400.10 0.0160.004
1.27 0.050
0.05 MIN 0.002
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
( #1 #16 0.25 ) 0.010
0~8
0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
#32 21.35 0.841 MAX 20.950.10 0.8250.004
#17 1.00 0.10 0.0390.004 1.20 0.047 MAX 0.10 MAX 0.004 MAX
+0.10 -0.05 +0.004 0.006 -0.002
10.16 0.400
0.15
( 0.50 ) 0.020
( 0.95 ) 0.037
0.400.10 0.0160.004
1.27 0.050
0.05 MIN 0.002
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Revision 1.0 April 1999

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