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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14500B Industrial Control Unit
The MC14500B Industrial Control Unit (ICU) is a single-bit CMOS processor. The ICU is designed for use in systems requiring decisions based on successive single-bit information. An external ROM stores the control program. With a program counter (and output latches and input multiplexers, if required) the ICU in a system forms a stored-program controller that replaces combinatorial logic. Applications include relay logic processing, serial data manipulation and control. The ICU also may control an MPU or be controlled by an MPU. * * * * * * * 16 Instructions DC to 1.0 MHz Operation at VDD = 5 V On-Chip Clock (Oscillator) Executes One Instruction per Clock Cycle 3 to 18 V Operation Low Quiescent Current Characteristic of CMOS Devices Capable of Driving One Low-Power Schottky Load or Two Low-Power TTL Loads over Full Temperature Range
L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648
DW SUFFIX SOIC CASE 751G
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
BLOCK DIAGRAM
3 2 16 8
DATA
D C D C +V OEN LU OSC D MUX STO STOC
PIN ASSIGNMENT
WRITE VDD VSS
RST WRITE DATA I3 I2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD RR X1 X2 JMP RTN FLAG O FLAG F
X1 X2 I0 I1 I2 I3 RST
IEN 14 13 7 6 5 4 1 INST REG
C RESULT REG. (RR)
15 12 11 10 9
I1
RR JMP RTN FLAG O FLAG F
I0 VSS
X1 -- OSCILLATOR OUTPUT X2 -- OSCILLATOR INPUT
REV 3 1/94
(c)MC14500B 1995 Motorola, Inc. 306
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II I III IIII I III IIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIII IIIIII IIII I I I II II II III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Input Voltage # "0" Level I0, I1, I2, I3 (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Input Voltage "0" Level RST, D, X2 (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Drive Current Other Outputs (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Output Drive Current Data, Write (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Output Voltage Vin = VDD or 0
Vin, Vout
Symbol
MOTOROLA CMOS LOGIC DATA
Iin, Iout VDD Tstg PD TL (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vin = 0 or VDD Characteristic Storage Temperature DC Supply Voltage "1" Level "1" Level "1" Level "0" Level Parameter Source Source Sink Sink
Lead Temperature (8-Second Soldering)
Power Dissipation, per Package
Input or Output Current (DC or Transient), per Pin
Input or Output Voltage (DC or Transient)
Symbol
VOH
VOL
IOH
IOH
VIH
VIH
IOL
IOL
VIL
VIL
VDD Vdc
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
- 0.5 to VDD + 0.5
- 0.5 to + 18.0
- 65 to + 150
- 3.0 - 0.64 - 1.6 - 4.2
4.95 9.95 14.95
- 1.2 - 3.6 - 7.2
0.64 1.6 4.2
Min
1.9 3.6 7.2
2.0 6.0 10
3.5 7.0 11
-- -- --
-- -- --
-- -- --
Value
10
260
500
- 55_C
0.05 0.05 0.05
Max
0.8 1.6 2.4
1.5 3.0 4.0
-- -- --
-- -- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
Unit
mW
mA
_C
_C
V
V
- 2.4 - 0.51 - 1.3 - 3.4
4.95 9.95 14.95
- 1.0 - 3.0 - 6.0
0.51 1.3 3.4
Min
1.6 3.0 6.0
2.0 6.0 10
3.5 7.0 11
-- -- --
-- -- --
-- -- --
- 4.2 - 0.88 - 2.25 - 8.8
Typ #
25_C
- 2.0 - 6.0 - 12
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
0.88 2.25 8.8
2.75 5.50 8.25
2.25 4.50 6.75
3.2 6.0 12
1.9 3.1 4.3
1.1 2.2 3.4
5.0 10 15
0 0 0
0.05 0.05 0.05
Max
0.8 1.6 2.4
1.5 3.0 4.0
-- -- --
-- -- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
v
- 1.7 - 0.36 - 0.9 - 2.4
4.95 9.95 14.95
- 0.7 - 2.1 - 4.2
0.36 0.9 2.4
Min
1.1 2.1 4.2
2.0 6.0 10
3.5 7.0 11
-- -- --
-- -- --
-- -- --
125_C
0.05 0.05 0.05
Max
0.8 1.6 2.4
1.5 3.0 4.0
-- -- --
-- -- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
v
MC14500B 307
mAdc mAdc mAdc mAdc Unit Vdc Vdc Vdc Vdc Vdc Vdc
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I IIIIIIII I IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIII I IIII I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I III IIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II II II III I I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIII IIIIII IIII I I I II II II III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
NOTE 1. Maximum Reset Delay may extend to one-half clock period. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS* (TA = 25_C; tr = tf = 20 ns for X and I inputs; CL = 50 pF for JMP, X1, RR, Flag O, Flag F;
ELECTRICAL CHARACTERISTICS -- continued (Voltages Referenced to VSS)
CL = 130 pF + 1 TTL load for Data and Write.)
Hold Time -- Instruction
Setup Time -- Instruction
Rent Pulse Width, RST
Clock Pulse Width, X1
Propagation Delay Time, X1 to RR
Quiescent Current (Per Package) Iout = 0 A, Vin = 0 or VDD **Total Supply Current at an External Load Capacitance (CL) on All Outputs
Input Capacitance (All Other Inputs)
Input Capacitance (Data)
Input Current
Input Current, RST
MC14500B 308
Data Data RST to Write, Data RST to Flag F, Flag O, RTN, JMP RST to X1 RST to RR X1 to Data X1 to Write X1 to Flag F, Flag O, RTN, JMP Characteristic Characteristic Symbol IDD Cin Cin Iin Iin IT VDD Vdc 5.0 10 15 15 15 -- -- -- Min 25 -- -- -- -- -- -- Symbol -55_C tsu(D) tW(R) tW(cl) tPLH, tPHL th(D) tsu(l) th(l) 0.1 Max 5.0 10 20 -- -- -- VDD Vdc Min 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- 0.00001 Typ # 0.005 0.010 0.015 25_C 150 5.0 15 Min 200 100 100 100 50 50 200 100 80 400 250 180 500 250 200 400 200 180 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IT = (1.5 A/kHz) f + IDD IT = (3.0 A/kHz) f + IDD IT = (4.5 A/kHz) f + IDD
MOTOROLA CMOS LOGIC DATA
0.1 Max 5.0 10 20 7.5 -- -- All Types Typ # 100 50 50 100 50 40 200 125 90 250 125 100 200 100 90 450 225 175 400 200 150 450 200 150 250 125 100 250 120 100 225 125 100 200 100 85 250 125 100 0 0 0 Min -- -- -- -- -- -- -- 125_C Note 1 Max 900 450 350 800 400 300 500 250 200 500 240 200 450 250 200 400 200 170 500 250 200 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.0 Max 150 300 600 250 -- -- Adc Adc Adc Adc Unit Unit pF pF ns ns ns ns ns
1M
100 k
10 k
10 k
Figure 1. Typical Clock Frequency versus Resistor (RC)
MEMORY
4 BIT OP CODE
DATA BUS
MEMORY ADDRESS
PROGRAM COUNTER
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII IIIIIIIIIIII I IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIII I I
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function Symbols RST Write Data I3 I2 I1 I0 VSS Flag F Flag O RTN JMP X2 X1 RR VDD 100 k 1 M RC, CLOCK FREQUENCY RESISTOR Chip Reset Write Pulse Data In/Out MSB Instruction Word Bit 2 Instruction Word Bit 1 Instruction Word LSB Instruction Word Negative Supply (Ground) Flag on NOP F Flag on NOP O Subroutine Return Flag Jump Instruction Flag Oscillator Input Oscillator Output Result Register Positive Supply
f Clk , CLOCK FREQUENCY (Hz)
Table 1. MC14500B Instruction Set
Instruction Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Mnemonic NOPO LD LDC AND ANDC OR ORC XNOR STO STOC IEN OEN JMP RTN SKZ NOPF
No change in registers. RR RR, Flag O Load result register. Data RR Load complement. Data RR Logical AND. RR Data RR Logical AND complement. RR Data RR Logical OR. RR + Data RR Logical OR complement. RR + Data RR Exclusive NOR. If RR = Data, RR 1 Store. RR Data Pin, Write Store complement. RR Data Pin, Write Input enable. Data IEN Register Output enable. Data OEN Register Jump. JMP Flag Return. RTN Flag and skip next instruction Skip next instruction if RR = 0 No change in registers. RR RR, Flag F

Action

ADDITIONAL OUTPUT DEVICES
I/O ADDRESS
MC14599B 8 8-BIT ADDRESSABLE LATCH OUTPUTS WITH BIDIRECTIONAL DATA MC14512 8-CHANNEL DATA SELECTOR TO PERIPHERAL DEVICES 8 INPUTS
ADDITIONAL INPUT DEVICES
I0, I1, I2, I3 MC14500B ICU
CLOCK
DATA
Figure 2. Outline of a Typical Organization for a MC14500B-Based System MC14500B 309
TIMING WAVEFORMS Instructions Instructions NOPO, NOPF RR, IEN, OEN remain unaffected
X1
RST tW(R) IEN REGISTER OEN REGISTER RR tPHL (RESET TO RR) 4-BIT INSTRUCTION NOP0 FLAG 0 tPLH (DATA TO FLAG) tPHL NOPF NOPO tPHL (RESET TO XI)
FLAG F
Instructions Instructions
X1
SKZ, JMP, RTN RR, IEN, OEN remain unaffected
tW(cl) 4-BIT INSTRUCTION SKZ RST * JMP RTN * JMP
RR
JMP FLAG tPHL (RESET TO JUMP)
RTN FLAG SKP F/F INTERNAL * Instructions Ignored.
MC14500B 310
MOTOROLA CMOS LOGIC DATA
TIMING WAVEFORMS Instructions STO, STOC, OEN
X1
DATA
RR
OEN REGISTER (INTERNAL)
WRITE tPHL tPLH VALID WHEN RST = L
X1 LD, etc. 4-BIT INSTRUCTION NOP tsu(I) DATA tsu(D) RR tPLH, tPHL (X1 TO RR) IEN REGISTER (INTERNAL) VALID WHEN RST = L th(D) th(I) IEN LD, etc.
MOTOROLA CMOS LOGIC DATA
EEEEEE EEEEEE EEEEEE EEEEEE
1
4-BIT INSTRUCTION
STO STOC
STO STOC
NOP
OEN
STO STOC
tPLH, tPHL (X1 TO DATA)
NOTE 1. Valid output data.
Instructions Instructions
LD, LDC, AND, ANDC OR, ORC, XNOR, IEN
MC14500B 311
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MC14500B 312
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
16X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45 _ C -T-
14X DIM A B C D F G J K M P R
G
K
SEATING PLANE
M
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MOTOROLA CMOS LOGIC DATA
*MC14500B/D*
MC14500B MC14500B/D 313

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