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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75104A, 75108A
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
PD75108A is a 4-bit single-chip CMOS microcomputer having a data processing capability comparable to
that of an 8-bit microcomputer. Operating at high speeds, the microcomputer allows data to be manipulated in units of 1, 4, or 8 bits. In addition, various bit manipulation instructions are provided to reinforce I/O manipulation capability. Equipped with I/Os for interfacing with peripheral circuits operating on a different supply voltage, outputs that can directly drive LEDs, and analog inputs, PD75108A is suitable for controlling such small equipments as cameras and VCRs.
Detailed functions are described in the following user's manual. Be sure to read it for designing.
PD751XX Series User's Manual: IEM-922
FEATURES
* Internal memory * Program memory (ROM) : 8064 x 8 bits (PD75108A) : 4096 x 8 bits (PD75104A) * Data memory (RAM) : 512 x 4 bits (PD75108A) : 320 x 4 bits (PD75104A) * Architecture "75X" rivaling 8-bit microcomputers * 43 systematically organized instructions * A wealth of bit manipulation instructions * 8-bit data transfer, compare, operation, increment, and decrement instructions * 1-byte relative branch instructions * GETI instruction executing 2-/3-byte instruction with one byte * High speed. Minimum instruction execution time: 0.95 s (at 4.19 MHz, 5V) * Instruction execution time change function: 0.95 s/1.91 s/15.3 s (at 4.19 MHz) * I/O port pins as many as 58 * Three channels of 8-bit timers * 8-bit serial interface * Multiplexed vector interrupt function
Unless there are differences among PD75104A and 75108A functions, PD75108A is treated as the representative model throughout this manual.
The information in this document is subject to change without notice.
Document No. IC-2568A (O. D. No. IC-7080B) Date Published January 1994 P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1989
PD75104A, 75108A
ORDERING INFORMATION
Part Number Package 64-pin plastic QFP ( 64-pin plastic QFP ( 14 mm) 14 mm) Quality Grade Standard Standard
PD75104AGC-xxx-AB8 PD75108AGC-xxx-AB8
Remarks: xxx is ROM code number.
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
PD75104A, 75108A
FUNCTIONAL OUTLINE
Item Number of Basic Instructions Minimum Instruction Execution Time ROM Internal Memory RAM General-Purpose Register Accumulator 8064 x 8 bits (PD75108A), 4096 x 8 bits (PD75104A) 512 x 4 bits (PD75108A), 320 x 4 bits (PD75104A) (4 bits x 8 ) x 4 banks or (8 bis x 4 ) x 4 banks Three accumulators selectable according to the bit length of manipulated data: * 1-bit accumulator (CY), 4-bit accumulator (A), and 8-bit accumulator (XA) 58 port pins * CMOS input pins (Pull-up resistor can be conneced to 4 out of 10 pins in bit units.): 10 * CMOS I/O pins (can directly drive LEDs. Pull-up resistors can be connected to 24 out of 32 pins in bit units.): 32 * Medium voltage N-ch open-drain I/O pins: 12 (can directly drive LEDs. Pull-up resistors can be connected in bit units.) * Comparator input pins (4-bit accuracy): 4 * 8-bit timer/event counter x 2 * 8-bit basic interval timer (can be used as watchdog timer) * 8 bits Serial Interface * LSB first/MSB first mode selectable * Two transfer modes (transfer/reception and reception only modes) External: 3, Internal: 4 External: 2 * STOP and HALT modes * * * * Various bit manipulation instructions (set, reset, test, Boolean operation) 8-bit data transfer, compare, operation, increment, and decrement 1-byte relative branch instructions GETI instruction constituting 2 or 3-byte instruction with 1 byte 43 Changeable in three steps: 0.95 s, 1.91 s, and 15.3 s at 4.19 MHz Specifications
I/O Port
Timer/Counter
Vector Interrupt Test Input Standby
Instruction Set
Others Package
* Power-ON reset circuit (mask option) * Bit manipulation memory (bit sequential buffer: 16 bits) * 64-pin plastic QFP ( 14 mm)
3
PD75104A, 75108A
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) ...............................................................................................
6
2.
BLOCK DIAGRAM ...........................................................................................................................
7
3.
PIN FUNCTIONS ..............................................................................................................................
3.1 3.2 3.3 3.4 3.5 PORT PINS ............................................................................................................................................. PINS OTHER THAN PORTS ................................................................................................................. PIN INPUT/OUTPUT CIRCUITS ........................................................................................................... RECOMMENDED PROCESSING OF UNUSED PINS .......................................................................... NOTES ON USING THE P00/INT4, AND RESET PINS ......................................................................
8
8 9 10 12 13
4.
MEMORY CONFIGURATION ..........................................................................................................
14
5.
PERIPHERAL HARDWARE FUNCTIONS ........................................................................................
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 PORTS .................................................................................................................................................... CLOCK GENERATOR CIRCUIT ............................................................................................................ CLOCK OUTPUT CIRCUIT .................................................................................................................... BASIC INTERVAL TIMER ..................................................................................................................... TIMER/EVENT COUNTER ..................................................................................................................... SERIAL INTERFACE .............................................................................................................................. PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) .................................................... BIT SEQUENTIAL BUFFER .... 16 BITS ............................................................................................... POWER-ON FLAG (MASK OPTION) ....................................................................................................
19
19 20 21 22 22 24 26 27 27
6.
INTERRUPT FUNCTIONS ................................................................................................................
27
7.
STANDBY FUNCTIONS ..................................................................................................................
29
8.
RESET FUNCTION ...........................................................................................................................
30
9.
INSTRUCTION SET .........................................................................................................................
33
10. APPLICATION EXAMPLES ..............................................................................................................
10.1 VCR CAMERA ........................................................................................................................................
42
42
11. MASK OPTION SELECTION ...........................................................................................................
43
4
PD75104A, 75108A
12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 44
13. CHARACTERISTIC DATA (REFERENCE VALUE) ..........................................................................
54
14. PACKAGE DRAWINGS ...................................................................................................................
59
15. RECOMMENDED SOLDERING CONDITIONS ...............................................................................
60
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG THIS SERIES PRODUCTS ........................
61
APPENDIX B. DEVELOPMENT TOOLS ..............................................................................................
62
APPENDIX C.
RELATED DOCUMENTS ..............................................................................................
63
5
PD75104A, 75108A
1. PIN CONFIGURATION (TOP VIEW)
* 64-Pin Plastic QFP ( 14 mm)
RESET
P71
P70
P72
P60
P61
P73
P62
P50
P51
P52
P63
P53
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P83 P82 P81 P80 P93 P92 P91 P90 VSS P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 PTH01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P41 P42 P43 P30 P31 P32 P33 VDD NC P140 P141 P142 P143 P130 P131 P132
TI0
P22/PCL
P21/PTO1
P20/PTO0
P02/SO
PTH00
TI1
P01/SCK
P00/INT4
P123
P122
P121
P03/SI
P120
P23
P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 P90-P93
: Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 8 : Port 9
SCK SO SI PTO0, PTO1 PCL PTH00-PTH03 INT2, INT3 TI0, TI1 X1, X2 RESET NC VDD VSS
: Serial Clock Input/Output : Serial Output : Serial Input : Timer Output : Clock Output : Comparator Input : External Test Input : Timer Input : Oscillation Pin : Reset Input : No Connection : Positive Power Supply : GND
INT0, INT1, INT4 : External Vector Interrupt Input
P120-P123 : Port 12 P130-P133 : Port 13 P140-P143 : Port 14
6
P133
P40
X1
X2
PD75108AGC-xxx-AB8
PD75104AGC-xxx-AB8
2. BLOCK DIAGRAM
BASIC INTERVAL TIMER INTBT TI0 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 TI1 PTO1/P21 TIMER/EVENT COUNTER #1 INTT1 SI/P03 SO/P02 SCK/P01 SERIAL INTERFACE INTSIO INT0/P10 INT1/P11 INT2/P12 INT3/P13 INT4/P00 CLOCK OUTPUT CONTROL ROM PROGRAM MEMORY 8064 x 8BITS : PD75108A 4096 x 4BITS : PD75104A PROGRAM COUNTER* ALU CY SP (8)
BIT SEQ. BUFFER (16)
PORT 0 PORT 1
4 4
P00 - P03 P10 - P13
BANK PORT 2 PORT 3 GENERAL REG. PORT 4 RAM DATA MEMORY 512 x 4BITS : PD75108A 320 x 4BITS : PD75104A PORT 5 PORT 6 PORT 7 PORT 8 4 4 4 4 4 4 P40 - P43 P50 - P53 P60 - P63 P70 - P73 P80 - P83 P90 - P93 4 4 P20 - P23 P30 - P33
DECODE AND CONTROL
INTERRUPT CONTROL f X/2 N
PORT 9
PD75104A, 75108A
PORT 12 PTH00-PTH03 4 PROGRAMMABLE THRESHOLD PORT #0 CLOCK DIVIDER CLOCK GENERATOR STAND BY CONTROL CPU CLOCK PORT 13 PORT 14 PCL/P22 *: 13 bits: PD75108A 12 bits: PD75104A X1 X2 V DD V SS RESET
4 4 4
P120 - P123 P130 - P133 P140 - P143
7
PD75104A, 75108A
3.
3.1
PIN FUNCTIONS
PORT PINS
I/O Circuit Type*1 B F 4-bit input port (PORT 0) P02 P03 P10 P11 Input P12 P13 P20* P21* P22*
3 3
Pin Name P00 P01
I/O Input I/O I/O Input
Shared with: INT4 SCK
Function
8-Bit I/O
At Reset
Input E B x
SO SI INT0 INT1 4-bit input port (PORT 1) INT2 INT3 PTO0 PTO1 Input*2
B -A
I/O
3
4-bit I/O port (PORT 2) PCL x -- 4-bit programmable I/O port (PORT 3)
Input
E
P23*3 P30-P33*3 P40-P43*3 P50-P53*3 P60-P63*3 P70-P73*3 P80-P83* P90-P93*
3 3
I/O I/O I/O I/O I/O I/O I/O
-- Can be specified for input or output bitwise. -- -- -- Can be specified for input or output bitwise. 4-bit I/O port (PORT 7) -- -- 4-bit I/O port (PORT 8) o 4-bit I/O port (PORT 9) 4-bit N-ch open-drain I/O port (PORT 12) Built-in pull-up resistors can be specified in bit o 4-bit I/O port (PORT 4) o 4-bit I/O port (PORT 5) 4-bit programmable I/O port (PORT 6)
Input Input*2 Input*2 Input*2 Input*2 Input* Input*
2 2
E E-A E-A E-A E-A E-A E-A
P120-P123* 3
I/O
-- units (by mask option). Open-drain withstanding voltage: 12 V o 4-bit N-ch open-drain I/O port (PORT 13) Built-in pull-up resistors can be specified in bit
Input*2
M
P130-P133*3
I/O
-- units (by mask option). Open-drain withstanding voltage: 12 V 4-bit N-ch open-drain I/O port (PORT 14)
Input*2
M
P140-P143*3
Built-in pull-up resistors can be specified in bit I/O -- units (by mask option). Open-drain withstanding voltage: 12 V -
Input*2
M
*1: Circles indicate Schmitt trigger input pins. 2: With pull-up resistor connected: high level Without pull-up resistor connected: high impedance 3: Can directly drive LEDs.
8
PD75104A, 75108A
3.2 PINS OTHER THAN PORTS
I/O Circuit Type*1 N
Pin Name PTH00-PTH03 TI0
I/O Input
Shared with: --
Function 4-bit variable threshold voltage analog input port External event pulse inputs for timer/event counter.
At Reset --
Input TI1
--
Also serves as edge-detected vector interrupt input. 1-bit input also possible.
--
B
PTO0 I/O PTO1 SCK SO SI INT4 INT0 Input INT1 INT2 Input INT3 PCL I/O I/O I/O Input Input
P20 Outputs for timer/event counter P21 P01 P02 P03 P00 falling edges detected) P10 P11 P12 Edge-detected testable inputs (rising edge detected) P13 P22 Clock output Crystal/ceramic system clock oscillator connections. Input E Input*2 B -A Edge-detected vectored interrupt inputs (valid Input*2 edge selectable) B -A Serial clock I/O Serial data output Serial data input Edge-detected vectored interrupt input (both rising and Input B Input Input Input F E B Input E
X1, X2
--
--
Input external clock to X1, and signal in reverse phase with X1 to X2.
--
--
RESET NC VDD VSS
Input -- -- --
-- -- -- --
System reset input (low level active type) No Connection Positive power supply GND
-- -- -- --
B -- -- --
*1: Circles indicate Schmitt trigger input pins. 2: With pull-up resistor connected: high level Without pull-up resistor connected: high impedance
9
PD75104A, 75108A
3.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the PD75108A.
TYPE A
VDD
TYPE D
VDD data P-ch OUT
P-ch IN output disable
N-ch
N-ch
Input buffer of CMOS standard
Push - pull output that can be set in a output high- impedance state (both P -ch and N -ch are off)
TYPE B
TYPE E
data IN output disable Type D
IN/OUT
Type A
Schmitt trigger input with hysteresis characteristics
I/O circuit consisting of Type D push-pull output circuit and Type A input buffer
TYPE D
TYPE E-A
V DD V DD Pull-up resistor (mask option) IN data Type D output disable Pull-up resistor (mask option) IN/OUT
Type A
Schmitt trigger input with hysteresis characteristics
I/O circuit consisting of Type D push-pull output and Type A input buffer
10
PD75104A, 75108A
TYPE F
TYPE N
Comparator data Type D output disable
Type B
IN/OUT
IN
+ -
V REF (threshold voltage)
I/O circuit consisting of Type D push-pull output circuit and Type B Schmitt trigger input
TYPE M
Pull-up resistor (mask option)
V DD
IN/OUT
data output disable
N-ch (+12 V withstand)
Medium-voltage input buffer (+12 V withstand)
11
PD75104A, 75108A
3.4 RECOMMENDED PROCESSING OF UNUSED PINS
Pin PTH00-PTH03 TI0 TI1 P00 P01-P03 P10-P13
Recommended connections
Connect to VSS or VDD
Connect to VSS Connect to VSS or VDD * Connect to VDD when a pull-up resistor is provided. * Connect to VSS when a pull-up resistor is not provided.
P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 P90-P93 P120-P123 P130-P133 P140-P143 RESET NC
* *
Input: Connect to VSS Output: Open
*
When a pull-up resistor is provided: Input: Connect to VDD Output: Open
*
When a pull-up resistor is not provided: Input: Connect to VSS or VDD Output: Open
Connect to VDD* Open or connect to VDD
*: Connect this pin to the VDD pin only when a power-ON reset circuit is provided as a mask option.
12
PD75104A, 75108A
3.5 NOTES ON USING THE P00/INT4, AND RESET PINS
In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode, in which the internal fuctions of the PD75108A are tested (solely used for IC tests), is provided to the P00/ INT4 and RESET pins. If a voltage exceeding VDD is applied to either of these pins, the PD75108A is put into test mode. Therefore, even when the PD75108A is in normal operation, if noise exceeding the VDD is input into any of these pins, the PD75108A will enter the test mode, and this will cause problems for normal operation. As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up to these pins and the above montioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. * Connect a diode across P00/INT4 and
RESET , and VDD.
VDD
* Connect a capacitor across P00/INT4 and
RESET , and VDD.
VDD
VDD
VDD
P00/INT4, RESET
P00/INT4, RESET
13
PD75104A, 75108A
4. MEMORY CONFIGURATION
* Program memory (ROM) ... 8064 x 8 bits (0000H-1F7FH) : PD75108A ... 4096 x 8 bits (0000H-0FFFH) : PD75104A * 0000H, 0001H : Vector table to which address from which program is started is written after reset * 0002H-000BH: Vector table to which address from which program is started is written after interrupt * 0020H-007FH : Table area referenced for GETI instruction * Data memory (RAM) * Data area ....512 x 4 bits (000H-1FFH) : PD75108A 320 x 4 bits (000H-13FH) : PD75104A * Peripheral hardware area .... 128 x 4 bits (F80H-FFFH)
14
PD75104A, 75108A
(a) PD75108A
Address 7 0000H 6 5 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE 0 INT0/INT1 start address (upper 5 bits) INT0/INT1 start address (lower 8 bits) 0006H MBE RBE 0 INTSIO start address (upper 5 bits) INTSIO start address (lower 8 bits) 0008H MBE RBE 0 INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) 000AH MBE RBE 0 INTT1 start address (upper 5 bits) INTT1 start address (lower 8 bits) BR $addr instruction relational branch address -15 to -1, +2 to +16 CALLF ! faddr instruction entry address CALL ! addr instruction subroutine entry address 0
MBE RBE
BR ! addr instruction branch address
0020H GETI instruction reference table 007FH 0080H BRCB ! caddr instruction branch address
07FFH 0800H
Branch destination address and subroutine entry address for GETI instruction
0FFFH 1000H BRCB ! caddr instruction branch address 1F7FH
Fig. 4-1 Program Memory Map (1/2)
Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.
15
PD75104A, 75108A
(b) PD75104A
Address 7 0000H 6 5 0 4 0 Internal reset start address (upper 4 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE 0 0 INTBT/INT4 start address (upper 4 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE 0 0 INT0/INT1 start address (upper 4 bits) INT0/INT1 start address (lower 8 bits) 0006H MBE RBE 0 0 INTSIO start address (upper 4 bits) INTSIO start address (lower 8 bits) 0008H MBE RBE 0 0 INTT0 start address (upper 4 bits) INTT0 start address (lower 8 bits) 000AH MBE RBE 0 0 INTT1 start address (upper 4 bits) INTT1 start address (lower 8 bits) CALLF ! faddr instruction entry address CALL ! addr instruction subroutine entry address 0
MBE RBE
BR $addr instruction relational branch address -15 to -1, +2 to +16
0020H GETI instruction reference table 007FH 0080H
BRCB ! caddr instruction branch address
07FFH 0800H
Branch destination address and subroutine entry address for GETI instruction
0FFFH
Fig. 4-1 Program Memory Map (2/2)
Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.
16
PD75104A, 75108A
(a) PD75108A
Data memory General-purpose register area Stack area 256x 4 Data memory Static RAM (512 x 4) 0FFH 100H 000H 01FH (32 x 4)
Memory bank
Bank 0
256x 4
Bank 1
1FFH Not provided F80H 128x 4 FFFH Bank 15
Peripheral hardware area
Fig. 4-2 Data Memory Map(1/2)
17
PD75104A, 75108A
(b) PD75104A
Data memory General-purpose register area 000H 01FH (32 x 4)
Memory bank
Stack area Data area Static RAM (320 x 4) 256x 4
Bank 0
0FFH 100H 64 x 4 13FH Not provided F80H 128x 4 FFFH Bank 15 Bank 1
Peripheral hardware area
Fig. 4-2 Data Memory Map(2/2)
18
PD75104A, 75108A
5.
5.1
PERIPHERAL HARDWARE FUNCTIONS
PORTS : 8
I/O ports are classified into the following 3 kinds: * CMOS input (PORT0, 1) * CMOS input/output (PORT2, 3, 4, 5, 6, 7, 8, 9) : 32 * N-ch open-drain input/output (PORT12, 13, 14) : 12 Total : 52
Table 5-1 Port Function
Port (Symbol) PORT0 Function Operation and Features Remarks Shared witn SI, SO, SCK, and Can always be read or tested regardless of operation INT4 pins Shared with INT0 to 3 pins each bit can be connected to pull-up resistor by mask otion. PORT3 Can be set in input or output mode bitwise PORT6 PORT2 PORT4 PORT5 PORT7 PORT8 PORT9 PORT12 PORT13 PORT14 4-bit I/O* (N-ch open-drain. 12V) Can be set in input or output mode in 4-bit units. Ports 12 and 13 can be used in pairs to input or output 8-bit data Each bit can be connected to pull-up resistor by mask option 4-bit I/O* Can be set in input or output mode in 4-bit units. Ports 4 and 5, 6 and 7, 8 and 9 can be used in pairs to input or output 8-bit data Each bit can be connected to pullup resistor by mask option Each bit of Port 6 pins can be connected to pull-up resistor by mask option Shared with PTO0, PTO1, and PCL pins.
4-bit input
PORT1
mode of shared pin
*: Can directly drive LED.
19
PD75104A, 75108A
5.2 CLOCK GENERATOR CIRCUIT
The clock generator circuit generates clocks to control CPU operation modes by supplying clocks to the CPU and peripheral hardware. In addition, this circuit can change the instruction execution time. * 0.95 s/1.91 s/15.3 s (operating at 4.19 MHz)
* Basic interval timer (BT) * Clock output circuit * Timer/event counter * Serial interface
X1
X1 System clock generator circuit X2 f XX or fX 1/2 1/16 Oscillation stops
1/8 to 1/4096 Frequency divider
X2
Selector
Frequency divider 1/4 * CPU * Clock output circuit
PCC PCC0
Internal bus
PCC1 4 PCC2 HALT* PCC3 STOP* R Q HALT F/F S
Clears PCC2, PCC3
STOP F/F Q S
Wait release signal from BT RES (internal reset) signal
R
Standby release signal from interrupt control circuit
Remarks 1: fXX= Crystal/ceramic oscillator 2: fX = External clock frequency 3: * indicates the instruction execution 4: PCC: Processor clock control register 5 5: One clock cycle (tCY) of is one machine cycle of an instruction. For tCY, refer to AC characteristics in 12. ELECTRICAL SPECIFICATIONS.
Fig. 5-1 Clock Generator Block Diagram
20
PD75104A, 75108A
5.3 CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output clock pulses to the remote control output, peripheral LSIs, etc. * Clock output (PCL) : , 524 kHz, 262 kHz (operating at 4.19 MHz)
From the clock generator f XX/23 f XX/24 Selector Output buffer PCL/P22
PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM
P22 output latch
Bit 2 of PMGB
Port 2 input/ output mode specification bit
4 Internal bus
Fig. 5-2 Clock Output Circuit Configuration
21
PD75104A, 75108A
5.4 BASIC INTERVAL TIMER
The basic interval timer has these functions: * Interval timer operation which generates a reference time interrupt * Watchdog timer application which detects a program runaway * Selects the wait time for releasing the standby mode and counts the wait time * Reads out the count value
From the clock generator Clear fXX/25 Clear
fXX/27 MPX fXX/29 BT Basic interval timer (8-bit frequency divider circuit)
Set signal
BT interrupt request flag
f XX/212
Vector interrupt request IRQBT signal
3
Wait release signal for standby release BTM0 BTM
BTM3
BTM2
BTM1
*SET1
4 Internal bus
8
Remarks : *: Instruction execution
Fig. 5-3 Basic Interval Timer Configuration
5.5 TIMER/EVENT COUNTER
PD75108A contains two channels of timer/event counters.
These two channels are almost identical in terms of configuration and function except the count pulse (CP) that can be selected and the function to supply clocks to the serial interface. The functions of the timer/event counter include: * Programmable interval timer operation * Output of square wave at an arbitrary frequency to PTOn pin * Event counter operation * Input of TIn pin signal as external interrupt input signal * Dividing TIn pin input by N to output to PTOn pin (frequency divider operation) * Supply of serial shift clock to serial interface circuit (channel 0 only) * Reading counting status
22
Internal bus 8 SET1* TMn 8 8 Modulo register (8) TOFn 8 Comparator (8) 8 Tn TIn From clock generator circuit MPX CP Count register (8) Clear Timer operation start RES TMn1 Edge detector circuit Coincidence TOUT F/F To selector TMODn TOEn To enable flag TOn PORT2.n Bit 2 of PGMB P2n Port 2 output I/O latch mode To serial interface (channel 0 only) P2n/PTOn Output buffer INTTn IRQTn set signal
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0 TIn
Input buffer
TMn0 IRQTn clear signal
PD75104A, 75108A
*: SET1: Execution of the instruction
Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1)
23
PD75104A, 75108A
5.6 SERIAL INTERFACE The PD75108A is equipped with clock 8-bit serial interface that operates in the following two modes: * Operation stop mode * Three-line serial I/O mode
24
Internal bus 8 8 SIO0 P03/SI Shift register (8) SIO7 SIO SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0 SIOM 8 SET1*
P02/SO
Serial clock counter (3) Clear P01/SCK R Q S
Overflow
INTSIO IRQSIO set signal IRQSIO clear signal
Serial start
f XX /2 4 MPX f XX /2 10 TOF0 (from timer channel 0)
PD75104A, 75108A
*: Execution of the instruction
Fig. 5-5 Serial Interface Block Diagram
25
PD75104A, 75108A
5.7 PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)
PD75108A is equipped with a 4-bit analog input port (consisting of PTH00 to PTH03 pins) whose threshold
voltage is programmable. This programmable threshold port is configured as shown in Figure 5-6. The threshold voltage (VREF) can be changed in 16 steps (VDD x 0.5/16 - VDD x 15.5/16), and analog signals can be directly input. When VREF is set to VDD x 7.5/16, the programmable threshold port can also be used as a digital signal input port.
Input buffer PTH00 +
PTH01
+ -
PTH02
+ -
PTH03
+ - Operates /stops
Programmable threshold port input latch (4)
-
PTH0
V DD
PTHM7 1 2R R R MPX VREF PTHM4 8 PTHM3 1 2R 4 PTHM2 PTHM1 PTHM0 PTHM PTHM6 PTHM5
Fig. 5-6 Programmable Threshold Port Configuration
26
Internal bus
PD75104A, 75108A
5.8 BIT SEQUENTIAL BUFFER .... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units.
Address bit 3 Symbol
FC3H 2 BSB3 1 0 3
FC2H 2 BSB2 1 0 3
FC1H 2 BSB1 1 0 3
FC0H 2 BSB0 1 0
L register
L=F
L=C L=B INCS L
L=8 L=7 DECS L
L=4 L=3
L=0
Remarks:
For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 5-7 Bit Sequential Buffer Format
5.9 POWER-ON FLAG (MASK OPTION)
The power-ON flag (PONF) is set to only when the power-ON reset circuit operates and power-ON reset signal has been generated (see Fig. 8-1). The PONF flag is mapped at bit 0 of memory space address FD1H, and can be manipulated by a bit manipulation instruction. However, it cannot be set by the SET1 instruction.
6. INTERRUPT FUNCTIONS
The PD75108A has 7 different interrupt sources and can perform multiplexed interrupt processing with priority assigned. In addition to that, the PD75108A is also provided with two types of edge detection testable inputs. The interrupt control circuit of the PD75108A has these functions: * Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt enable flag (IExxx) and interrupt master enable flag (IME). * The interrupt start address can be arbitrarily set. * Multiplexed interrupt function that can specify priority by the interrupt priority selector register (IPS). * Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). * Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
27
28
Internal bus 2 IM1 2 IM0 9 Interrupt enable flag (IE xxx ) IME 4 IPS 2 IST INT BT INT4 /P00 INT0 /P10 INT1 /P11 Edge detection circuit Edge detection circuit Edge detection circuit INTSIO INTT0 IRQBT IRQ4 IRQ0 IRQ1 IRQSIO IRQT0 IRQT1 Priority control circuit Vector table address generator Decoder INTT1 INT2 /P12 INT3 /P13 Edge detection circuit Edge detection circuit IRQ2
PD75104A, 75108A
IRQ3 Interrupt request flag
Standby release signal
Fig. 6-1 Interrupt Control Block Diagram
PD75104A, 75108A
7. STANDBY FUNCTIONS
The PD75108A has two different standby modes (STOP mode and HALT mode) to reduce the power consumption of the microcomputer chip while waiting for program execution.
Table 7-1 Each Status in Standby Mode
STOP Mode Setting Instruction Clock Oscillator circuit Basic Interval Timer STOP instruction Clock oscillation stops
HALT Mode HALT instruction Only CPU clock is stopped Operates (sets IRQBT at reference time intervals) Operates when serial clock other than is specified
Stops
Operates only when input of external
Serial Interface Operation Status Timer/Event Counter
SCK or output of TO0 is selected as serial clock (where external TI0 is input to timer/event counter 0)
Operates only when TIn pin input signal is specified as count clock
Operates
Clock output circuit
Stops Stops
Outputs when clock other than CPU clock is used Stops
CPU Release Signal
Interrupt request signal enabled by interrupt enable flag, or RESET input
29
PD75104A, 75108A
8. RESET FUNCTION
The reset ( RES ) signal generator circuit is configured as shown in Figure 8-1.
RESET
Internal reset signal (RES) Mask option Power-ON reset generator circuit SWA Power-ON flag (PONF) SWB
Execution of bit manipulation instruction*
*: PONF cannot be set to 1 by SET1 instruction.
Fig. 8-1 Reset Signal Generator Circuit
The Power-ON reset generator circuit generates an internal reset signal when the supply voltage rises. This pulse can be used in three ways by specifying a mask option through SWA and SWB shown in Fig. 8-1. (Refer to 11. MASK OPTION SELECTION.) The reset operations performed by the Power-On reset circuit and the RESET input signal are illustrated in Figs. 8-2 and 8-3, respectively.
Supply voltage 0V
Wait* (approx. 31.3 ms: 4.19 MHz)
Internal reset signal (RES)
HALT mode
Operation mode
Internal reset operation
*: The wait time does not include the time required after the RES signal has been generated until the oscillation starts.
Fig. 8-2 Reset by Power-ON Reset Circuit
30
Internal bus
PD75104A, 75108A
Wait* (31.3 ms: 4.19 MHz)
RESET input Operation mode or standby mode
HALT mode
Operation mode
Internal reset operation
*: The wait time does not include the time required after the RES signal has been generated until the oscillation starts.
Fig. 8-3 Reset by RESET Signal
The status of each internal hardware device after the reset operation has been performed is shown in Table 81.
Table 8-1 Hardware Device Status After Reset (1/2)
RESET input during standby mode
Lower 5 bits of program memory address 0000H are set to PC12-8,* 1 and contents of address 0001H are set to PC7-0. Power-ON Reset or RESET Input during Operation Lower 5 bits of program memory address 0000H are set to PC12-8,* 1 and contents of address 0001H are set to PC7-0.
Hardware
Program Counter (PC)
Carry Flag (CY) Skip Flags (SK0-SK2) PSW Interrupt Status Flags (IST0, IST1)
Retained 0 0 Bit 6 of program memory address 0000H is set in RBE, and bit 7 is set in MBE. Undefined Retained*2 Retained 0, 0 Undefined 0 0 FFH 0 0, 0 Retained 0
Undefined 0 0 Bit 6 of program memory address 0000H is set in RBE, and bit 7 is set in MBE. Undefined Undefined Undefined 0, 0 Undefined 0 0 FFH 0 0, 0 Undefined 0
Bank Enable Flags (MBE, RBE)
Stack Pointer (SP) Data Memory (RAM) General-Purpose Registers (X,A,H,L,D,E,B,C) Bank Selector Registers (MBS, RBS) Basic interval timer Counter (BT) Mode Register (BTM) Counter (Tn) Timer/Event Counter (n = 0, 1) Modulo Register (TMODn) Mode Register (TMn) TOEn, TOFn Serial Interface Shift Register (SIO) Mode Register (SIOM)
*1: PC11-8 for PD75104A 2: Data at data memory addresses 0F8H to 0FDH become undefined when the RESET signal has been input.
31
PD75104A, 75108A
Table 8-1 Hardware Device Status After Reset (2/2)
Hardware
Processor Clock Control Register (PCC)
RESET input during standby mode 0 0 Reset (0) 0 0 0, 0 Off Cleared (0) 0 Undefined 0 Retained 0
Power-ON Reset or RESET Input during Operation
0 0 Reset (0) 0 0 0, 0 Off Cleared (0) 0 Undefined 0 1 or undefined* 0
Clock Generator Circuit, Clock Output Circuit
Clock Output Mode Register (CLOM) Interrupt Request Flags (IRQxxx) Interrupt Enable Flags (IExxx)
Interrupt
Priority Selector Register (IPS) INT0, 1 Mode Registers (IM0, IM1) Output Buffer
Digital Port
Output Latch I/O Mode Registers (PMGA, PMGB, PMGC) PTH00-PTH03 Input Latches
Analog Port Power-ON Flag (PONF)
Mode Register (PTHM)
Bit Sequential Buffer (BSB0-BSB3)
*: Power-ON reset: 1
RESET input during operation: undefined
32
PD75104A, 75108A
9. INSTRUCTION SET
(1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and - are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols in the register and flag symbols can be described as labels in the places of mem, fmem, pmem, and bit (for details, refer to PD751XX Series User`s Manual (IEM-922)). However, fmem and pmem restricts the label that can be described.
Representation reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr caddr faddr taddr PORTn IExxx RBn MBn Description X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label* 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label
PD75104A 0000H to 0FFFH immediate data or label PD75108A 0000H to 1F7FH immediate data or label
12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (where bit0 = 0) or label PORT0 - PORT9, PORT12 - PORT14 IEBT, IESIO, IET0, IET1, IE0 - IE4 RB0 - RB3 MB0, MB1, MB15
*: Only even address can be described as mem for 8-bit data processing.
33
PD75104A, 75108A
(2) A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS IExxx RBS MBS PCC . (xx) xxH Legend of operation field : A register; 4-bit accumulator : B register; 4-bit accumulator : C register; 4-bit accumulator : D register; 4-bit accumulator : E register; 4-bit accumulator : H register; 4-bit accumulator : L register; 4-bit accumulator : X register; 4-bit accumulator : Register pair (XA); 8-bit accumulator : Register pair (BC); 8-bit accumulator : Register pair (DE); 8-bit accumulator : Register pair (HL); 8-bit accumulator : Expansion register pair (XA') : Expansion register pair (BC') : Expansion register pair (DE') : Expansion register pair (HL') : Program counter : Stack pointer : Carry flag; or bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt mask enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Delimiter of address and bit : Contents addressed by xx : Hexadecimal data
PORTn : Port n (n = 0 - 9, 12 - 14)
34
PD75104A, 75108A
(3) Symbols in addressing area field
*1 *2 *3 MB = MBE . MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH Data memory addressing
*4 *5 *6 *7 *8 *9 *10
PD75104A PD75108A
addr = 0000H-0FFFH addr = 0000H-1F7FH Program memory addressing
addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16
PD75104A PD75108A
caddr = 0000H-0FFFH (PC11 = 0) caddr = 0000H-0FFFH (PC12 = 0) or 1000H-1F7FH (PC12 = 1)
faddr = 0000H-07FFH taddr = 0020H-007FH
Remarks * MB indicates memory bank that can be accessed. * In *2, MB = 0 regardless of MBE and MBS. * In *4 and *5, MB = 15 regardless of MBE and MBS. * *6 to *10 indicate areas that can be addressed. (4) Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip
function skips. The value of S varies as follows: * When no instruction is skipped ........................................................................ * When 1-byte or 2-byte instruction is skipped ................................................. * When 3-byte instruction (BR ! adder or CALL ! adder) is skipped .............. S=0 S=1 S=2
Note : The GETI instruction is skipped in one machine cycle.
One machine cycle equals to one cycle of the CPU clock , (= tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC).
35
PD75104A, 75108A
Machine Bytes Cycles 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' * PD75104A XA (PC11-8+DE)ROM * PD75108A XA (PC12-8+DE)ROM XA, @PCXA 1 3 * PD75104A XA (PC11-8+XA)ROM * PD75108A XA (PC12-8+XA)ROM *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String effect A String effect B
Instructions
Mnemonics
Operand
Operation
Addressing Area
Skip Conditions
Transfer MOV
A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA
String effect A
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
Table Reference
MOVT
XA, @PCDE
36
PD75104A, 75108A
Instructions Bit transfer
Mnemonics MOV1
Operand
Bytes
Machine Cycles 2 2 2
Operation
Addressing Area *4 *5 *1
Skip Conditions
CY, fmem.bit CY, pmem.@L CY, @H+mem. bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY
2 2 2
CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1,CY rp'1-XA-CY
2 2 2
2 2 2
*4 *5 *1
Arithmetic operation
ADDS
A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA
1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2
1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S
carry carry *1 carry carry carry *1
ADDC
A, @HL XA, rp' rp'1, XA
SUBS
A, @HL XA, rp' rp'1, XA
*1
borrow borrow borrow
SUBC
A, @HL XA, rp' rp'1, XA
*1
AND
A, #n4 A, @HL XA, rp' rp'1, XA
OR
A, #n4 A, @HL XA, rp' rp'1, XA
XOR
A, #n4 A, @HL XA, rp' rp'1, XA
n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA
AA CY A0, A3 CY, An-1 An AA reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1
*1
*1
*1
Accumulator Manipulation
RORC NOT INCS
A A reg rp1 @HL mem
Increment/ decrement
reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH
DECS
reg rp'
37
PD75104A, 75108A
Machine Bytes Cycles 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S
Instructions
Mnemonics
Operand
Operation
Addressing Area
Skip Conditions
Compare
SKE
reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp'
Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY
(mem.bit) 1 (fmem.bit) 1
reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
Carry flag
SET1 CLR1
CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit
Manipu- SKT lation NOT1
CY = 1
Memory/ SET1 Bit Manipulation CLR1
*3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1
(pmem7-2 + L3-2.bit(L1-0)) 1 (H + mem3-0.bit) 1
(mem.bit) 0 (fmem.bit) 0
mem.bit fmem.bit pmem.@L @H+mem.bit
(pmem7-2 + L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1
Skip if (pmem7-2+L3-2.bit (L1-0)) = 1
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 Skip if (H + mem3-0.bit) = 0
Skip if (fmem.bit) = 1 and clear
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR fmem.bit pmem.@L
Skip if (pmem7-2+L3-2.bit (L1-0)) = 1 and clear
@H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
2 2 2 2 2 2 2 2 2 2
2+S 2 2 2 2 2 2 2 2 2
Skip if (H+mem3-0.bit) = 1 and clear
*1 *4 *5 *1 *4 *5 *1 *4 *5 *1
(@H+mem.bit) = 1
(fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit)
CY CY
CY CY (pmem7-2+L3-2.bit (L1-0))
CY CY
(H+mem3-0.bit) CY CY (fmem.bit) (H+mem3-0.bit)
CY CY (pmem7-2+L3-2.bit (L1-0))
CY CY
38
PD75104A, 75108A
Machine Bytes Cycles -- --
Instructions
Mnemonics
Operand
Operation
Addressing Area
Skip Conditions
Branch
BR
addr
* PD75104A PC11-0 addr The most suitable instruction is selectable from among BRCB ! caddr, and BR $ addr
*6
depending on the assembler. * PD75108A PC12-0 addr
! addr
3
3
* PD75108A PC12-0 addr
$ addr
1
2
* PD75104A PC11-0 addr * PD75108A PC12-0 addr
BRCB
! caddr
2
2
* PD75104A PC11-0 caddr11-0 * PD75108A PC12-0 PC12 + caddr11-0
BR
PCDE
2
3
* PD75104A PC11-0 PC11-8 + DE * PD75108A PC12-0 PC12-8 + DE
PCXA
2
3
* PD75104A PC11-0 PC11-8 + XA * PD75108A PC12-0 PC12-8 + XA
Subroutine/ Stack Control
CALL
! addr
3
3
* PD75104A (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, 0 PC11-0 addr, SP SP-4 * PD75108A (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0 addr, SP SP-4

The most suitable instruction is selectable from among BR ! addr, BRCB ! caddr, and BR $ addr depending on the assembler.

*6 *7 *8 *6

39
PD75104A, 75108A
Machine Bytes Cycles 2 2
Instructions Subroutine/ Stack Control (Cont`d)
Mnemonics
Operand
Operation
Addressing Area
Skip Conditions
CALLF
! faddr
* PD75104A (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, 0 PC11-0 0, faddr, SP SP-4 * PD75108A (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0 00, faddr, SP SP-4
*9
RET
1
3
* PD75104A MBE, RBE, x, x (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4 * PD75108A MBE, RBE, x, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4
RETS
1
3+S
* PD75104A MBE, RBE, x, x (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4, then skip unconditionally * PD75108A MBE, RBE, x, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4, then skip unconditionally
Unconditioned
RETI
1
3
* PD75104A MBE, RBE, x, x (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 * PD75108A MBE, RBE, x, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1)(SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2
PUSH
rp BS
1 2
1 2
POP
rp BS
1 2
1 2
40
PD75104A, 75108A
Machine Bytes Cycles 2 IExxx DI IExxx I/O IN* A, PORTn XA, PORTn OUT* PORTn, A PORTn, XA CPU Control HALT STOP NOP Special SEL RBn MBn GETI taddr 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 2 2 2 2 2 2 2 2 1 2 2 3
Instructions
Mnemonics
Operand
Operation
Addressing Area
Skip Conditions
Interrupt Control
EI
IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0 A PORTn
(n = 0-9, 12-14)
XA PORTn+1,PORTn (n = 4, 6, 8, 12) PORTn A
(n = 2-9, 12-14)
PORTn+1, PORTn XA(n = 4, 6, 8, 12)
Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n (n = 0-3) MBS n (n = 0, 1, 15) * PD75104A * Where TBR instruction, PC11-0 (taddr)3-0+(taddr+1) ......................................................... * Where TCALL instruction, (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, 0 PC11-0 (taddr)3-0+(taddr+1) SP SP-4 ......................................................... * Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) * PD75108A * Where TBR instruction, PC12-0 (taddr)4-0+(taddr+1) ......................................................... * Where TCALL instruction, (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0 (taddr)4-0+(taddr+1) SP SP-4 ......................................................... * Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) ............................. Depends on referenced instruction ............................. Depends on referenced instruction *10
*: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. Remarks: TBR and TCALL instructions are assembler instructions for GETI instruction table definition. 5
41
PD75104A, 75108A
10. APPLICATION EXAMPLES
10.1 VCR CAMERA
PD75108A
Highcurrent output Operation mode LED indicator System control/ editing function INT Servo system control circuit Motor plunger driver circuit, etc. INT On-screen display controller 12 V Audio video system control circuit Battery sensor Key matrix (including message input)
Reel pulse
Comparator input Sensor circuit Exposure sensor Tape start/end sensor Powerdown detector
42
PD75104A, 75108A
11. MASK OPTION SELECTION
PD75108A has the following mask options. Options to be built in can be selected.
(1) Pin
Pin P10 - P13 P40 - P43 P50 - P53 P60 - P63 P70 - P73 P80 - P83 P90 - P93 P120 - P123 P130 - P133 P140 - P143
Mask Option
Pull-down resistor can be built in bitwise.
(2)
Power-ON reset generation circuit, power-ON flag (PONF) One from the following three ways can be selected.
Mask Option Specification Power-On Reset Generator Circuit Provided Not provided Not provided Power-On Flag (PONF) Provided Provided Not provided
Switching Selection (Refer to Fig. 8-1.) SWA ON ON OFF SWB ON OFF OFF Generates automatically Not generate autoamtically -- Internal Reset Signal (RES)
43
PD75104A, 75108A
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Parameter Supply Voltage Input Voltage Symbol VDD VI1 VI2* 1 Other than ports 12 to 14 Ports 12 to 14 w/pull-up resistor Open drain Output Voltage High-Level Output Current Low-Level Output Current
Total of ports 0, 2 to 4, 12 to 14
Conditions
Ratings -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +13 -0.3 to VDD+0.3 -15 -30 Peak rms Peak rms Peak rms 30 15 100 60 100 60 -40 to +85 -65 to +150
Unit V V V V V mA mA mA mA mA mA mA mA C C
VO IOH IOL*2 1 pin All pins 1 pin
Total of ports 5 to 9 Operating Temperature Storage Temperature Topt Tstg
*1: The power supply impedance (pull-up resistor) must be 50 k or higher when a voltage higher than 10 V is applied to ports 12 to 14. 2: rms = Peak value x Duty 5 Note: Even if one of the parametrs exceed its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product.
44
PD75104A, 75108A
OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Recommended Constants
Oscillator Ceramic
Item Oscillation frequency(fXX)* 1
Conditions VDD = Oscillation voltage range
MIN. 2.0
TYP.
MAX. 5.0 *
3
Unit MHz
X1 C1
X2 C2
Oscillation stabiliza- After VDD come to tion time*2 MIN. of oscillation voltage range
4
ms
Crystal
X1 C1 X2 C2
Oscillation frequency (fXX)* 1 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2
2.0 10 30
4.19
5.0 *
3
MHz ms ms
External Clock
X1 X2
X1 input frequency (fX)*1 X1 input high-, low-level widths (tXH, tXL)
2.0
5.0 *3
MHz
PD74HCU04
100
250
ns
*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD has come to MIN. of oscillation voltage range or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fxx 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 s, falling short of the rated minimum value of 0.95 s. Note: When using the oscillation circuit of the system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Also, do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the osccillator circuit at the same potential as VSS. Do not connect the ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 5 5
45
PD75104A, 75108A
RECOMMENDED OSCILLATOR CIRCUITS CONSTANTS
RECOMMENDED CERAMIC OSCILLATORS
External Manufacturer Product Name Capacitance (pF) C1 CSA 2.00MG Murata Mfg. Co., Ltd. CSA 4.19MG CSA 4.19MGU CST 4.19T KBR-2.0MS Kyoto Ceramic Co., Ltd. KBR-4.0MS KBR-4.19MS KBR-4.9152M 30 30 30 Provided 100 33 33 33 C2 30 30 30 Provided 100 33 33 33 Oscillation Voltage Range (V) MIN. 2.7 3.0 2.7 3.0 3.0 3.0 3.0 3.0 MAX. 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0
RECOMMENDED CRYSTAL OSCILLATOR
External Capacitance (pF) C1 Kinseki HC-49/U 22 C2 22 Oscillation Voltage Range (V) MIN. 2.7 MAX. 6.0
Manufacturer
Product Name
Note: Use a crystal oscillator with an equivalent series resistance of 80 or less.
46
PD75104A, 75108A
DC CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Item Symbol VIH1 High-Level Input Voltage VIH2 VIH3 Conditions Other than below Ports 0, 1, TI0, 1, RESET Ports 12 to 14 Pull-up resistor Open drain VIH4 VIL1 Low-Level Input Voltage VIL2 VIL3 X1, X2 Other than below Ports 0, 1, TI0, 1, RESET X1, X2 VDD = 4.5 to 6.0 V,IOH = -1 mA
High-Level Output Voltage
MIN. 0.7VDD 0.8 VDD 0.7 VDD 0.7 VDD VDD-0.5 0 0 0 VDD-1.0 VDD-0.5
TYP.
MAX. VDD VDD VDD 12 VDD 0.3 VDD 0.2 VDD 0.4
Unit V V V V V V V V V V
VOH
IOH = -100 A VDD = 4.5 to 6.0 V
Ports 0, 2 to 9, IOL = 15 mA Ports 12 to 14, IOL = 10 mA
0.35 0.35
2.0 2.0 0.4 0.5 3 20 20 -3 -20 3 20 -3
V V V V
Low-Level Output Voltage
VOL VDD = 4.5 to 6.0 V, IOL = 1.6 mA IOL = 400 A
High-Level Input Leakage Current
ILIH1 ILIH2 ILIH3
VIN = VDD
Other than below X1,X2
A A A A A A A A
VIN = 12 V VIN = 0 V
Ports 12 to 14 (open drain)
Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current
ILIL1 ILIL2 ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 12 V VOUT = 0 V
Other than X1, X2 X1, X2 Other than below
Ports 12 to 14 (open drain)
Internal Pull-Up Resistor
RL
Ports 1, 4 to 9, and 12 to 14 4.19MHz crystal
VDD = 5 V10%
15 10
40
70 80
k k mA mA
IDD1
VDD = 5 V10%* 2 VDD = 3 V10%* 3 HALT mode VDD = 5 V10% VDD = 3 V10%
3 0.55 600 200 0.1
9 1.5 1800 600 10
Supply Current*1
IDD2
oscillator C1 = C2 = 22pF
A A A
IDD3
STOP mode, VDD = 3 V10%
*1: The current flowing into the internal pull-up resistor, power-ON reset circuit (mask option), and comparator circuit is not included. 2: When the high-speed mode is set by setting the processor clock control register (PCC) to 0011. 3: When the low-speed mode is set by setting the PCC to 0000.
47
PD75104A, 75108A
CAPACITANCE (Ta = 25C, VDD = 0 V)
Parameter Input Capacitance Output Capacitance Input/Output Capacitance Symbol CIN COUT CIO f = 1 MHz Pins other than thosemeasured are at 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
COMPARATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 4.5 to 6.0 V)
Parameter Comparison Accuracy Threshold Voltage PTH Input voltage Comparator circuit current dissipation Symbol VACOMP VTH VIPTH PTHM7 is set to "1" 0 0 1 Conditions MIN. TYP. MAX. 100 VDD VDD Unit mV V V mA
POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = -40 to +85C)
Parameter Power-On Reset High-Level Operating Voltage Power-On Reset Low-Level Operating Voltage Supply Voltage Rise Time Supply Voltage Off Time Power-On Reset Circuit Current Dissipation*2
17
Symbol VDDH
Conditions
MIN. 4.5
TYP.
MAX. 6.0
Unit V
VDDL tr toff IDDPR VDD = 5 V10% VDD = 2.5 V
0 10 1 10 2
0.2 *1
V
s
s
100 20
A A
*1: 2 /fXX (31.3 ms at fXX = 4.19 MHz) 2: Current flowing when power-ON reset circuit or power-ON Flag is incorporeated.
V DD
V DDH
V DDL
t off
tr
Note: Apply power gradually and smoothly.
48
PD75104A, 75108A
AC CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Parameter CPU Clock Cycle Time* (Minimum Instruction Execution Time = 1 Machine Cycle) TI0, TI1 Input Frequency TI0, TI1 Input High-/ Low-Level Width Symbol Conditions VDD = 4.5 to 6.0 V tCY 3.8 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V SCK Cycle Time tKCY Input Output Input Output VDD = 4.5 to 6.0 V SCK High-/Low-Level Width tKH, tKL Input Output Input Output SI Setup Time (vs. SCK) SI Hold Time (vs. SCK) SCK SO Output delay Time INT0 to INT4 High-/Low-Level Width RESET Low-Level Width tSIK tKSI VDD = 4.5 to 6.0 V 0 0 0.48 1.8 0.8 0.95 3.2 3.8 0.4
tKCY/2-50
MIN. 0.95
TYP.
MAX. 32 32 1 275
Unit
s s
MHz kHz
fTI tTIH, tTIL
s s s s s s s
ns
1.6
tKCY/2-150
s
ns ns ns 300 1000 ns ns
100 400
tKSO tINTH,
5 tINTL tRSL 5
s s
*: The cycle time of the CPU clock () is determined by the input frequency of the ceramic or crystal oscillator circuit and the set value of the processor clock control register. The tCY vs. VDD characteristics are as shown on the right.
7 6 5 4
t CY [s]
tCY vs. VDD 40 32
Operation guaranteed range
3
2
1
0.5 0 1 2 3 4 V DD [V] 5 6
49
PD75104A, 75108A
AC TIMING MEASURING POINTS (excluding Ports 0, 1, TI0, TI1, X1, X2, and RESET)
0.7 VDD 0.3 VDD
Measuring points
0.7 VDD 0.3 VDD
CLOCK TIMING
1/fX tXL tXH
X1 input
VDD -0.5 0.4
TI INPUT TIMING
1/fTI tTIL tTIH 0.8 VDD 0.2 VDD
TI0, TI1
50
PD75104A, 75108A
SERIAL TRANSFER TIMING
tKCY tKL tKH 0.8 V DD 0.2 V DD
SCK
tSIK
tKSI
0.8 VDD SI Input data 0.2 VDD
tKSO
SO
Output data
INTERRUPT INPUT TIMING
tINTL tINTH
INT0 to INT4
0.8 V DD 0.2 V DD
RESET INPUT TIMING
tRSL
RESET
0.2 VDD
51
PD75104A, 75108A
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = -40 to +85C)
Parameter Data Retention Supply Voltage Data Retention Supply Current*1 Release Signal Set Time Oscillation Stabilization Wait Time*2 Symbol VDDDR IDDDR tSREL tWAIT Released by RESET Released by interrupt request VDDDR = 2.0 V 0 217/fX *3 Conditions MIN. 2.0 0.1 TYP. MAX. 6.0 10 Unit V
A s
ms ms
*1: The current flowing through internal pull-up resistor, power-ON reset circuit (mask option), and comparator circuit is not included 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 Wait time ( ): fXX = 4.19 MHz 2 20/fXX (approx. 250 ms) 2 17/fXX (approx. 31.3 ms) 2 15/fXX (approx. 7.82 ms) 2 13/fXX (approx. 1.95 ms)
DATA RETENTION TIMING
(releasing STOP mode by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution RESET tSREL
tWAIT
52
PD75104A, 75108A
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution Standby release signal (interrupt request) tSREL
tWAIT
53
PD75104A, 75108A
13. CHARACTERISTIC DATA (REFERENCE VALUE)
IDD vs. VDD Characteristics (crystal oscillation)
(Ta = 25C) 5000 High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] HALT mode [0100]
1000 500
Supply current IDD [ A]
100 50
10 5
STOP mode [1000] When power-ON reset circuit and power-ON flag are incorporated. Figure in [ ] indicates set values of PCC. X1 X2 Crystal oscillation 4.194304 MHz 22 pF 22 pF
1 0.5
0
1
2
3 4 5 Supply voltage VDD [V]
6
I DD vs. f XX Characteristics (crystal oscillation)
(VDD = 5.0 V, Ta = 25C) 3.0 Figure in [ ] indicates set values of PCC. X1 X2 C1
Supply current IDD [mA]
High-speed mode [0011]
2.5 C2
2.0
Medium-speed mode [0010]
1.5
Low-speed mode [0000]
1.0
HALT mode [0100] 0.5
0
0
1
2
3
4 f XX [MHz]
5
54
PD75104A, 75108A
I DD vs. V DD Characteristics (ceramic oscillation)
(Ta = 25C) 5000 High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] HALT mode [0100]
1000 500
Supply current IDD [ A]
100 50
10 5
STOP mode [1000] When power-ON reset circuit and power-ON flag are incorporated. Figure in [ ] indicates set values of PCC. X1 X2 Ceramic oscillation 4.19 MHz 30 pF 30 pF
1 0.5
0
1
2
3
4 5 6 Supply voltage VDD [V]
I DD vs. f XX Characteristics (ceramic oscillation)
(VDD = 5.0 V, Ta = 25C) 3.0 Figure in [ ] indicates set values of PCC. X1 X2 C1
Supply current IDD [mA]
High-speed mode [0011]
2.5 C2 Medium-speed mode [0010] 2.0
1.5
Low-speed mode [0000]
1.0 HALT mode [0100] 0.5
0 0 1 2 3 4 f XX [MHz] 5
55
PD75104A, 75108A
I DD vs. f X Characteristics (external clock)
(VDD = 5.0 V, Ta = 25C) 3.0 Figures in [ ] indicates set values of PCC. X1 X2
2.5
PD74HCU04
Supply current IDD [ A]
High-speed mode [0011]
2.0
Medium-speed mode [0010] 1.5
1.0
Low-speed mode [0000]
0.5 HALT mode [0100] 0 0 1 2 3 4 f X [MHz] 5
f TI vs. V DD Characteristics
TIn input frequency f TI [kHz]
1000
500
Operation guaranteed range 100
50
0
1
2
3
4 V DD [V]
5
6
7
56
PD75104A, 75108A
V OL vs. I OL (Ports 0 and 2 to 9) Characteristics
30 V DD = 6 V V DD = 5 V V DD = 4 V
Low-level output current of port 0 and 2 to 9 I OL [mA]
V DD = 3 V 20
10
0
0
1
2 V OL [V]
3
4
VOL vs. IOL (Ports 12 to 14) Characteristics
30 V DD = 6 V V DD = 5 V V DD = 4 V
Low-level output current of ports 12 to 14 I OL [mA]
20
V DD = 3 V
10
0
0
1
2 V OL [V]
3
4
57
PD75104A, 75108A
V OH vs. I OH (Ports 0 and 2 to 9) Characteristics
-15 V DD = 6 V V DD = 5 V
V DD = 4 V
High-level output current of port 0 and 2 to 9 IOH [mA]
-10
V DD = 3 V
-5
0
0
1
2 V DD - V OH [V]
3
4
58
PD75104A, 75108A
14. PACKAGE DRAWINGS
14)
64 PIN PLASTIC QFP (
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J
K
P
N
L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
M
55
Q
59
PD75104A, 75108A
15. RECOMMENDED SOLDERING CONDITIONS
It is recommended that PD75104A, 75106A, and 75108A be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). For other soldering methods and conditions, please consult NEC.
Table 15-1 Soldering Conditions of Surface Mount Type
(1) PD75108AGC - xxx - AB8: 64-pin plastic QFP (
Soldering Method Infrared Reflow VPS Wave Soldering
14 mm)
Symbol for Recommended Condition IR30-00-1 VP15-00-1 WS60-00-1
Soldering Conditions Package peak temperature: 230C, time: 30 seconds max. (210C min.), number of times: 1 Package peak temperature: 215C, time: 40 seconds max. (200C min.), number of times: 1 Soldering bath temperature: 260C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., time: 3 seconds max. (per side)
Pin Partial Heating
--
(2) PD75104AGC - xxx - AB8: 64-pin plastic QFP (
Soldering Method Infrared Reflow
14 mm)
Symbol for Recommended Condition IR30-162-1
Soldering Conditions Package peak temperature: 230C, time: 30 seconds max. * (210C min.), number of times: 1, number of days: 2 days , (afterwards, 16 hours of prebaking at 125C is required.) Package peak temperature: 215C, time: 40 seconds max. * (200C min.), number of times: 1, number of days: 2 days , (afterwards, 16 hours of prebaking at 125C is required.) Soldering bath temperature: 260C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120C max. (package surface temperature), number of days: 2 days , (afterwards, 16 hours of prebaking at 125C is required.)
*
VPS
VP15-162-1
Wave Soldering
WS60-162-1
Pin Partial Heating
Pin temperature: 300C max., time: 3 seconds max. (per side)
--
*: This means the number of days after unpacking the dry pack. Storage conditions are 25C and 65% RH max. Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Notice
A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235C, number of times: 2, and an extended number of days) is also available. For details, consult NEC.
60
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG THIS SERIES PRODUCTS
Item Program Memory
PD75104 PD75106 PD75108 PD75112 PD75116 PD75104A PD75108A PD75P108B PD75P116
* Mask ROM * 0000H-0FFFH * 4096 x 8 bits
* Mask ROM * 0000H-177FH * 6016 x 8 bits
* Mask ROM * 0000H-1F7FH * 8064 x 8 bits
* Mask ROM * 0000H-2F7FH * 12160 x 8 bits
* Mask ROM * 0000H-3F7FH * 16256 x 8 bits
* Mask ROM * 0000H-0FFFH * 4096 x 8 bits
* Mask ROM * 0000H-1F7FH * 8064 x 8 bits
* One-time PROM * One-time PROM * 0000H-1F7FH * 8064 x 8 bits * 0000H-3F7FH * 16256 x 8 bits
Data Memory
320 x 4 bits Bank 0: 256 x 4 Bank 1: 64 x 4
512 x 4 bits Bank 0: 256 x 4 Bank 1: 256 x 4
320 x 4 bits Bank 0: 256 x 4 Bank 1: 64 x 4
512 x 4 bits Bank 0: 256 x 4 Bank 1: 256 x 4
Instruction Set I/O Lines Total I/O * CMOS I/O: 32
Provided with BR !addr instruction except for PD75104 and 75104A 58 * CMOS I/O: 32 (pull-up resistor as mask option: 24) * +12 V withstand open-drain output : 12 (pull-up resistor as mask option) LED direct drive: 44 * CMOS I/O: 32 * +12 V open-drain output: 12 LED direct drive: 44
* +12 V withstand open-drain output: 12 (pull-up resistor as mask option) LED direct drive: 44
Input
* CMOS input: 10 * Comparator input: 4
* CMOS input: 10 (pull-up resistor as mask option: 4) * Comparator input: 4
* CMOS input: 10 * Comparator input: 4
Power-ON Reset Circuit Power-ON Flag Provided (mask option) Not provided
PD75104A, 75108A
Operating Voltage Range Pin Connections Package * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm) 2.7 to 6.0 V Depends on package. Only PD75P116 has VPP pin. * 64-pin plastic QFP ( 14 mm) * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm) 5V 10%
61
PD75104A, 75108A
APPENDIX B. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems using
PD75108A:
Hardware IE-75000-R* 1 IE-75001-R IE-75000-R-EM*2 EP-75108AGC-R EV-9200GC-64 IE Control Program RA75X Relocatable Assembler In-circuit emulator for 75X series Emulation board for IE-75000-R and IE-75001-R Emulation prove for PD75104AGC and 75108AGC. It is provided with a 64pin conversion socket, EV-9200GC-64 Host machine PC-9800 series (MS-DOS IBM PC/AT
TM TM
Software
Ver.3.30 to Ver.5.00A* 3)
(PC DOS
TM
Ver.3.1)
*1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
62
PD75104A, 75108A
APPENDIX C. RELATED DOCUMENTS
5
63
PD75104A, 75108A
[MEMO]
64
PD75104A, 75108A
GENERAL NOTES ON CMOS DEVICES
STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being
handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly .
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to "Processing of Unused Pins" in the documents of each devices.
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application.
65
PD75104A, 75108A
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.
66

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