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CY2291
Three-PLL General Purpose EPROM Programmable Clock Generator
Features Three integrated phase-locked loops EPROM programmability Benefits Generates up to 3 custom frequencies from external sources Easy customization and fast turnaround
Factory-programmable (CY2291) or field-programmable Programming support available for all opportunities (CY2291F) device options Low-skew, low-jitter, high-accuracy outputs Power-management options (Shutdown, OE, Suspend) Frequency select option Smooth slewing on CPUCLK Configurable 3.3V or 5V operation 20-pin SOIC Package Meets critical industry standard timing requirements Supports low-power applications 8 user-selectable frequencies on CPU PLL Allows downstream PLLs to stay locked on CPUCLK output Enables application compatibility Industry-standard packaging saves on board space
Selector Guide
Part Number CY2291 CY2291I CY2291F CY2291FI Outputs 8 8 8 8 Input Frequency Range Output Frequency Range Specifics Factory Programmable Commercial Temperature Factory Programmable Industrial Temperature Field Programmable Commercial Temperature Field Programmable Industrial Temperature 10 MHz-25 MHz (external crystal) 76.923 kHz-100 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-80 MHz (3.3V) 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V) 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V) 10 MHz-25 MHz (external crystal) 76.923 kHz-80 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-60.0 MHz (3.3V)
32XIN 32XOUT XTALIN OSC. XTALOUT S0 S1 S2/SUSPEND UPLL (10 BIT) /1,2,4,8 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96,104 /2,3,4 CLKA CLKB CPLL (8 BIT) /1,2,4 XBUF CPUCLK
Logic Block Diagram
OSC.
32K
MUX
CLKC CLKD
SPLL (8 BIT)
CLKF CONFIG EPROM
SHUTDOWN/ OE
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 June 14, 2000, rev. **
CY2291
Pin Configurations
32XOUT 32K CLKC VDD GND XTALIN XTALOUT XBUF CLKD CPUCLK
CY2291 20-pin SOIC
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 32XIN VBATT SHUTDOWN/OE S2/SUSPEND VDD S1 S0 CLKF CLKA CLKB
Pin Summary
Name 32XOUT 32K CLKC VDD GND XTALIN[1] XTALOUT XBUF CLKD CPUCLK CLKB CLKA CLKF S0 S1 S2/SUSPEND SHUTDOWN/OE VBATT 32XIN
[1, 2]
Pin Number 1 2 3 4, 16 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20
Description 32.768 kHz crystal feedback. 32.768 kHz output (always active if VBATT is present). Configurable clock output C. Voltage supply. Ground. Reference crystal input or external reference clock input. Reference crystal feedback. Buffered reference clock output. Configurable clock output D. CPU frequency clock output. Configurable clock output B. Configurable clock output A. Configurable clock output F. CPU clock select input, bit 0. CPU clock select input, bit 1. CPU clock select input, bit 2. Optionally enables suspend feature when LOW.[3] Places outputs in three-state[4] condition and shuts down chip when LOW. Optionally, only places outputs in three-state[4] condition and does not shut down chip when LOW. Battery supply for 32.768-kHz circuit. 32.768-kHz crystal input.
Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD 17 pF or 18 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). 3. Please refer to application note "Understanding the CY2291, CY2292 and CY2295" for more information. 4. The CY2291 has weak pull-downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.
2
CY2291
Operation
The CY2291 is a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems. All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable clock outputs (CLKA-CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies will have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The CY2291 can be configured for either 5V or 3.3V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10-MHz to 25-MHz crystals, providing additional flexibility. No external components are required with this crystal. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. Customers using the 32-kHz oscillator should connect a 10-M resistor in parallel with the 32-kHz crystal. shutdown is enabled, a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins will be less than 50 A (for Commercial Temp. or 100 A for Industrial Temp.) plus 15 A max. for the 32-kHz subsystem and is typically 10 A. After leaving shutdown mode, the PLLs will have to re-lock. All outputs except 32K have a weak pull-down so that the outputs do not float when three-stated.[4] The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs except 32K can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a three-state condition.[3] The CPUCLK can slew (transition) smoothly between 8 MHz and the maximum output frequency (100 MHz at 5V/80 MHz at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz at 3.3V for Industrial Temp. and for field-programmed parts). This feature is extremely useful in "Green" PC and laptop applications, where reducing the frequency of operation can result in considerable power savings. This feature meets all 486 and Pentium(R) processor slewing requirements.
Output Configuration
The CY2291 has five independent frequency sources on-chip. These are the 32-kHz oscillator, the reference oscillator, and three Phase-Locked Loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) drives the CLKF output and provides fixed output frequencies on the configurable outputs. The SPLL offers the most output frequency divider options. The CPU PLL (CPLL) is controlled by the select inputs (S0-S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The Utility PLL (UPLL) provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources. All configurations are EPROM programmable, providing short sample and production lead times. Please refer to the application note "Understanding the CY2291, CY2292, and CY2295" for information on configuring the part.
CyClocksTM Software
CyClocks is an easy-to-use application that allows you to configure any one of the EPROM programmable clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Please note the output frequency ranges in this data sheet when specifying them in CyClocks to ensure that you stay within the limits. CyClocks also has a power calculation feature that allows you to see the power consumption of your specific configuration. You can download a copy of CyClocks for free on Cypress's website at www.cypress.com.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Programmers is a portable programmer designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670.
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when pulled LOW (the 32-kHz clock output is not affected). If system
3
CY2291
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ............................................... -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V Storage Temperature ................................. -65C to +150C Max. Soldering Temperature (10 sec) ..........................260C Junction Temperature ...................................................150C Package Power Dissipation ...................................... 750 mW Static Discharge Voltage.............................................>2000V (per MIL-STD-883, Method 3015)
Operating Conditions[5]
Parameter VDD VDD VBATT TA CLOAD CLOAD fREF Description Supply Voltage, 5.0V operation Supply Voltage, 3.3V operation Battery Backup Voltage Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient Max. Load Capacitance 5.0V Operation Max. Load Capacitance 3.3V Operation External Reference Crystal External Reference Clock[6, 7, 8] All All All CY2291/CY2291F CY2291I/CY2291FI All All All All 10.0 1 Part Numbers Min. 4.5 3.0 2.0 0 -40 Max. 5.5 3.6 5.5 +70 +85 25 15 25.0 30 Unit V V V C C pF pF MHz MHz
Electrical Characteristics, Commercial 5.0V
Parameter VOH VOL VOH-32 VOL-32 VIH VIL IIH IIL IOZ IDD IDDS IBATT Description HIGH-Level Output Voltage LOW-Level Output Voltage 32.768-kHz HIGH-Level Output Voltage 32.768-kHz LOW-Level Output Voltage LOW-Level Input Voltage Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current Commercial
[10] [9]
Conditions IOH = 4.0 mA IOL = 4.0 mA IOH = 0.5 mA IOL = 0.5 mA
Min. 2.4
Typ.
Max. 0.4
Unit V V V
VBATT 0.5 0.4 2.0 0.8 <1 <1 75 10 5 10 10 250 100 50 15
V V V A A A mA A A
HIGH-Level Input Voltage[9] Except crystal pins Except crystal pins VIN = VDD-0.5V VIN = +0.5V Three-state outputs VDD = V DD Max., 5V operation Shutdown active, excluding VBATT VBATT = 3.0V CY2291/CY2291F
VDD Power Supply Current in Shutdown Mode[10] VBATT Power Supply Current
Notes: 5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 7. Please refer to application note "Crystal Oscillator Topics" for information on AC-coupling the external input reference clock. 8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended that a 150 pull-up resistor to VDD be connected to the Xout pin. 9. Xtal inputs have CMOS thresholds. 10. Load = Max., VIN = 0V or VDD, Typical (-104) configuration, CPUCLK = 66 MHz. Other configurations will vary. Power can be approximated by the following formula (multiply by 0.65 for 3V operation): IDD=10+0.06*(FCPLL+FUPLL+2*FSPLL)+0.27*(FCLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FCLKF +FXBUF).
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CY2291
Electrical Characteristics, Commercial 3.3V
Parameter VOH VOL VOH-32 VOL-32 VIH VIL IIH IIL IOZ IDD IDDS IBATT Description HIGH-Level Output Voltage LOW-Level Output Voltage 32.768-kHz HIGH-Level Output Voltage 32.768-kHz LOW-Level Output Voltage LOW-Level Input Voltage[9] Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] Commercial VDD Power Supply Current in Shutdown Mode[10] VBATT Power Supply Current IOH = 4.0 mA IOL = 4.0 mA IOH = 0.5 mA IOL = 0.5 mA 2.0 0.8 <1 <1 50 10 5 10 10 250 65 50 15 VBATT 0.5 0.4 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V V V A A A mA A A
HIGH-Level Input Voltage[9] Except crystal pins Except crystal pins VIN = VDD-0.5V VIN = +0.5V Three-state outputs VDD = V DD Max., 3.3V operation Shutdown active, excluding VBATT VBATT = 3.0V CY2291/CY2291F
Electrical Characteristics, Industrial 5.0V
Parameter VOH VOL VOH-32 VOL-32 VIH VIL IIH IIL IOZ IDD IDDS IBATT Description HIGH-Level Output Voltage LOW-Level Output Voltage 32.768-kHz HIGH-Level Output Voltage 32.768-kHz LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Input Voltage Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] Industrial VDD Power Supply Current in Shutdown Mode[10]
[9]
Conditions IOH = 4.0 mA IOL = 4.0 mA IOH = 0.5 mA IOL = 0.5 mA Except crystal pins Except crystal pins VIN = VDD-0.5V VIN = +0.5V Three-state outputs VDD = V DD Max., 5V operation Shutdown active, excluding VBATT CY2291I/CY2291FI
Min. 2.4
Typ.
Max. 0.4
Unit V V V
VBATT 0.5 0.4 2.0 0.8 <1 <1 75 10 5 10 10 250 110 100 15
V V V A A A mA A A
VBATT Power Supply Current VBATT = 3.0V
5
CY2291
Electrical Characteristics, Industrial 3.3V
Parameter VOH VOL VOH-32 VOL-32 VIH VIL IIH IIL IOZ IDD IDDS IBATT Description HIGH-Level Output Voltage LOW-Level Output Voltage 32.768-kHz HIGH-Level Output Voltage 32.768-kHz LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Input Voltage Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current Industrial
[10] [9]
Conditions IOH = 4.0 mA IOL = 4.0 mA IOH = 0.5 mA IOL = 0.5 mA Except crystal pins Except crystal pins VIN = VDD-0.5V VIN = +0.5V Three-state outputs VDD = V DD max., 3.3V operation Shutdown active, excluding VBATT VBATT = 3.0V CY2291I/CY2291FI
Min. 2.4
Typ.
Max. 0.4
Unit V V V
VBATT 0.5 0.4 2.0 0.8 <1 <1 50 10 5 10 10 250 70 100 15
V V V A A A mA A A
VDD Power Supply Current in Shutdown Mode[10] VBATT Power Supply Current
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CY2291
Switching Characteristics, Commercial 5.0V
Parameter t1 Name Output Period Description Clock output range, 5V operation CY2291 CY2291F Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHZ Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHZ t3 t4 t5 t6 t7 t8 t9A t9B t9C t9D t10A t10B Rise Time Fall Time Output Disable Time Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Lock Time for UPLL and SPLL Slew Limits Output clock rise time[13] Output clock fall time[13] Time for output to enter three-state mode after SHUTDOWN/OE goes LOW Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3, 12, 15] Frequency transition rate Peak-to-peak period jitter (t9A Max. - t9A min.), % of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B Max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power-Up Lock Time from Power-Up CPU PLL Slew Limits CY2291 CY2291F 8 8 1.0 <0.5 <0.7 <400 <250 <25 <0.25 Min. 10 (100 MHz) 11.1 (90 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 1 1 500 350 50 1 100 90 ns ns ns ns ns MHz/ ms % ns ps ps ms ms MHz MHz Unit ns ns
Notes: 11. XBUF duty cycle depends on XTALIN duty cycle. 12. Measured at 1.4V. 13. Measured between 0.4V and 2.4V. 14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: "Jitter in PLL-Based Systems." 15. CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL.
7
CY2291
Switching Characteristics, Commercial 3.3V
Parameter t1 Name Output Period Description Clock output range, 3.3V operation CY2291 CY2291F Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHZ Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHZ t3 t4 t5 t6 t7 t8 t9A t9B t9C t9D t10A t10B Rise Time Fall Time Output Disable Time Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Lock Time for UPLL and SPLL Slew Limits Output clock rise time[13] Output clock fall time[13] Time for output to enter three-state mode after SHUTDOWN/OE goes LOW Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3, 12, 15] Frequency transition rate Peak-to-peak period jitter (t9A Max. - t9A min.), % of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B Max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power-Up Lock Time from Power-Up CPU PLL Slew Limits CY2291 CY2291F 8 8 1.0 <0.5 <0.7 <400 <250 <25 <0.25 Min. 12.5 (80 MHz) 15 (66.6 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 1 1 500 350 50 1 80 66.6 ns ns ns ns ns MHz/ ms % ns ps ps ms ms MHz MHz Unit ns ns
8
CY2291
Switching Characteristics, Industrial 5.0V
Parameter t1 Name Output Period Description Clock output range, 5V operation CY2291I CY2291FI Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHZ Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHZ t3 t4 t5 t6 t7 t8 t9A t9B t9C t9D t10A t10B Rise Time Fall Time Output Disable Time Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Lock Time for UPLL and SPLL Slew Limits Output clock rise time[13] Output clock fall time[13] Time for output to enter three-state mode after SHUTDOWN/OE goes LOW Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3, 12, 15] Frequency transition rate Peak-to-peak period jitter (t9A Max. - t9A min.), % of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B Max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power-Up Lock Time from Power-Up CPU PLL Slew Limits CY2291I CY2291FI 8 8 1.0 <0.5 <0.7 <400 <250 <25 <0.25 Min. 11.1 (90 MHz) 12.5 (80 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 1 1 500 350 50 1 90 80 ns ns ns ns ns MHz/ ms % ns ps ps ms ms MHz MHz Unit ns ns
9
CY2291
Switching Characteristics, Industrial 3.3V
Parameter t1 Name Output Period Description Clock output range, 3.3V operation CY2291I CY2291FI Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHZ Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHZ t3 t4 t5 t6 t7 t8 t9A t9B t9C t9D t10A t10B Rise Time Fall Time Output Disable Time Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Lock Time for UPLL and SPLL Slew Limits Output clock rise time[13] Output clock fall time[13] Time for output to enter three-state mode after SHUTDOWN/OE goes LOW Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3, 12, 15] Frequency transition rate Peak-to-peak period jitter (t9A Max. - t9A min.), % of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B Max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power-Up Lock Time from Power-Up CPU PLL Slew Limits CY2291I CY2291FI 8 8 1.0 <0.5 <0.7 <400 <250 <25 <0.25 Min. 15 (66.6 MHz) 16.66 (60 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 1 1 500 350 50 1 66.6 60 ns ns ns ns ns MHz/ ms % ns ps ps ms ms MHz MHz Unit ns ns
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t1 t2 OUTPUT t3 t4
10
CY2291
Switching Waveforms (continued)
Output Three-State Timing
[4]
OE t5 ALL THREE-STATE OUTPUTS t6
CLK Outputs Jitter and Skew
t9A CLK OUTPUT t7 RELATED CLK
CPU Frequency Change
SELECT OLD SELECT Fold CPU NEW SELECT STABLE t8 & t10 Fnew
Test Circuit VDD 0.1 F OUTPUTS CLK out CLOAD
VDD 0.1 F GND
11
CY2291
Ordering Information
Ordering Code
CY2291SC-XXX CY2291SL-XXX CY2291F CY2291SI-XXX CY2291FI
Package Name
S5 S5 S5 S5 S5
Package Type
20-Pin SOIC 20-Pin SOIC 20-Pin SOIC 20-Pin SOIC 20-Pin SOIC
Operating Range
Commercial Commercial Commercial Industrial Industrial 5.0V 3.3V
Operating Voltage
3.3V or 5.0V 3.3V or 5.0V 3.3V or 5.0V
Document #: 38-00945-** CyClocks is a trademark of Cypress Semiconductor Corporation. Pentium is a registered trademark of Intel Corporation.
Custom Configuration Request Procedure
The CY229x are EPROM-programmable devices that may be configured in the factory or in the field by a Cypress Field Application Engineer (FAE). The output frequencies requested will be matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submitted to your local Cypress FAE or sales representative. The method to use to request custom configurations is: Use CyClocksTM software. This software automatically calculates the output frequencies that can be generated by the CY229x devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free of charge from the Cypress website (http://www.cypress.com) or from your local sales representative. Once the custom request has been processed you will receive a part number with a 3-digit extension (e.g., CY2292SC-128) specific to the frequencies and pinout of your device. This will be the part number used for samples requests and production orders.
Package Characteristics
Package 20-pin SOIC JA (C/W) 125 JC (C/W) 25 Transistor Count 9271
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CY2291
Package Diagram
20-Lead (300-Mil) Molded SOIC S5
51-85024-A
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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