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K4E170411D, K4E160411D K4E170412D, K4E160412D
CMOS DRAM
4M x 4Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4.194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx4 EDO DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as main memory unit for high level computer, microcomputer and personal computer.
FEATURES
* Part Identification - K4E170411D-B(F) (5V, 4K Ref.) - K4E160411D-B(F) (5V, 2K Ref.) - K4E170412D-B(F) (3.3V, 4K Ref.) - K4E160412D-B(F) (3.3V, 2K Ref.)
* Extended Data Out Mode operation (Fast Page Mode with Extended Data Out) * CAS-before-RAS refresh capability * RAS-only and Hidden refresh capability * Self-refresh capability (L-ver only) * Fast parallel test mode capability * TTL(5V)/LVTTL(3.3V) compatible inputs and outputs * Early Write or output enable controlled write Unit : mW * JEDEC Standard pinout * Available in Plastic SOJ and TSOP(II) packages 2K 605 550 * Single +5V10% power supply (5V product) * Single +3.3V0.3V power supply (3.3V product)
* Active Power Dissipation 3.3V 4K -50 -60 324 288 2K 396 360 4K 495 440 5V
Speed
FUNCTIONAL BLOCK DIAGRAM
* Refresh Cycles Part NO. K4E170411D K4E170412D K4E160411D K4E160412D VCC 5V 3.3V 5V 3.3V 2K 32ms
Refresh Control Refresh Counter Memory Array 4,194,304 x4 Cells
Refresh Refresh period cycle Normal L-ver 4K 64ms 128ms
RAS CAS W
Control Clocks
VBB Generator
Vcc Vss
Data in Refresh Timer Row Decoder Sense Amps & I/O Buffer
DQ0 to DQ3
* Performance Range Speed -50 -60
tRAC
50ns 60ns
tCAC
15ns 17ns
tRC
84ns 104ns
tHPC
20ns 25ns
Remark 5V/3.3V 5V/3.3V
A0-A11 (A0 - A10)*1 A0 - A9 (A0 - A10)*1
Row Address Buffer Col. Address Buffer Column Decoder
Data out Buffer OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
K4E170411D, K4E160411D K4E170412D, K4E160412D
CMOS DRAM
PIN CONFIGURATION (Top Views)
* K4E17(6)0411(2)D-B
* K4E17(6)0411(2)D-F
VCC DQ0 DQ1 W RAS *A11(N.C)
1 2 3 4 5 6
24 23 22 21 20 19
VSS DQ3 DQ2 CAS OE A9
VCC DQ0 DQ1 W RAS *A11(N.C)
1 2 3 4 5 6
24 23 22 21 20 19
VSS DQ3 DQ2 CAS OE A9
A10 A0 A1 A2 A3 VCC
7 8 9 10 11 12
18 17 16 15 14 13
A8 A7 A6 A5 A4 VSS
A10 A0 A1 A2 A3 VCC
7 8 9 10 11 12
18 17 16 15 14 13
A8 A7 A6 A5 A4 VSS
*A11 is N.C for K4E160411(2)D(5V/3.3V, 2K Ref. product) B : 300mil 26(24) SOJ F: 300mil 26(24) TSOP II
Pin Name A0 - A11 A0 - A10 DQ0 - 3 VSS RAS CAS W OE VCC N.C
Pin Function Address Inputs (4K Product) Address Inputs (2K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+5.0V) Power(+3.3V) No Connection (2K Ref. product)
K4E170411D, K4E160411D K4E170412D, K4E160412D
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol 3.3V VIN,VOUT VCC Tstg PD IOS Address -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 Rating 5V
CMOS DRAM
Units -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50 V V C W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min VCC VSS VIH VIL 3.0 0 2.0 -0.3*2 3.3V Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Min 4.5 0 2.4 -1.0*2 5V Typ 5.0 0 Max 5.5 0 VCC+1.0*1 0.8 V V V V Units
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0/20ns(5V), Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max Parameter Input Leakage Current (Any input 0VINVIN+0.3V, all other input pins not under test=0 Volt) 3.3V Output Leakage Current (Data out is disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Input Leakage Current (Any input 0VINVIN+0.5V, all other input pins not under test=0 Volt) 5V Output Leakage Current (Data out is disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL II(L) IO(L) VOH VOL Min -5 -5 2.4 -5 -5 2.4 Max 5 5 0.4 5 5 0.4 Units uA uA V V uA uA V V
K4E170411D, K4E160411D K4E170412D, K4E160412D
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICCS Power Dont care Normal L Dont care Dont care Normal L Dont care L L Speed -50 -60 Dont care -50 -60 -50 -60 Dont care -50 -60 Dont care Dont care Max K4E170412D 90 80 1 1 90 80 80 70 0.5 200 90 80 250 200 K4E160412D 110 100 1 1 110 100 90 80 0.5 200 110 100 250 200 K4E170411D 90 80 2 1 90 80 80 70 1 250 90 80 300 250
CMOS DRAM
K4E160411D 110 100 2 1 110 100 90 80 1 250 110 100 300 250
Units mA mA mA mA mA mA mA mA mA uA mA mA uA uA
ICC1* : Operating Current (RAS and CAS cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.) ICC4* : Hyper Page Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, DQ=Dont care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns ICCS : Self Refresh Current RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3, ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Hyper page mode cycle time, tHPC.
K4E170411D, K4E160411D K4E170412D, K4E160412D
CAPACITANCE (TA=25C, VCC=5V or 3.3V, f=1MHz)
Parameter Input capacitance [A0 ~ A11] Input capacitance [RAS, CAS, W, OE] Output capacitance [DQ0 - DQ3] Symbol CIN1 CIN2 CDQ Min -
CMOS DRAM
Max 5 7 7 Units pF pF pF
AC CHARACTERISTICS (0CTA70C, See note 1,2)
Test condition (5V device) : VCC=5.0V10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V Test condition (3.3V device) : VCC=3.3V0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS OE to output in Low-Z Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Symbol Min -50 Max Min 104 140 50 13 25 3 3 3 2 30 50 13 38 8 20 15 5 0 10 0 8 25 0 0 0 10 10 13 8 10K 37 25 10K 50 13 3 3 3 2 40 60 15 45 10 20 15 5 0 10 0 10 30 0 0 0 10 10 15 10 10K 45 30 10K 50 15 60 15 30 -60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 4 10 3,4,10 3,4,5 3,10 3 6,14 3 2 Units Notes
tRC tRWC tRAC tCAC tAA tCLZ tCEZ tOLZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL
84 116
K4E170411D, K4E160411D K4E170412D, K4E160412D
AC CHARACTERISTICS (Continued)
Parameter Data set-up time Data hold time Refresh period (2K, Normal) Refresh period (4K, Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper Page cycle time Hyper Page read-modify-write cycle time CAS precharge time (Hyper Page cycle) RAS pulse width (Hyper Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper Page Cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Symbol Min -50 Max Min 0 10 32 64 128 0 30 67 42 47 5 10 5 28 20 47 8 50 30 13 13 3 13 10 10 10 10 5 3 3 15 5 5 5 5 100 90 -50 13 13 13 15 3 15 10 10 10 10 5 3 3 15 5 5 5 5 100 110 -50 200K 25 56 10 60 35 0 34 79 49 54 5 10 5 -60
CMOS DRAM
Units Max ns ns 32 64 128 ms ms ms ns ns ns ns ns ns ns ns 35 ns ns ns ns 200K ns ns 15 ns ns 15 ns ns ns ns ns ns ns 15 15 ns ns ns ns ns ns ns us ns ns
Notes 9 9
tDS tDH tREF tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS
0 8
7 7 7 7
3 13 13
6
11 11
6,14 6
15,16,17 15,16,17 15,16,17
K4E170411D, K4E160411D K4E170412D, K4E160412D
TEST MODE CYCLE
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column address to RAS lead time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time Hyper Page cycle time Hyper Page read-modify-write cycle time RAS pulse width (Hyper Page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -50 Max Min 109 145 55 18 30 55 13 18 43 30 35 72 47 52 25 53 55 200K 33 18 18 18 20 20 10K 10K 65 15 20 50 35 39 84 54 59 30 61 65 65 20 35 10K 10K -60 Max
CMOS DRAM
( Note 11 )
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 200K 40 20 ns ns ns ns ns 3 13 13 7 7 7 3,4,10,12 3,4,5,12 3,10,12 Note
tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tCPWD tHPC tHPRWC tRASP tCPA tOEA tOED tOEH
89 121
K4E170411D, K4E160411D K4E170412D, K4E160412D
NOTES
CMOS DRAM
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. tASC6ns, Assume tT = 2.0ns 14. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 15. If tRASS100us, then RAS precharge time must use tRPS instead of tRP. 16. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed within 64ms/32ms before and after self refresh, in order to meet refresh specification. 17. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
K4E170411D, K4E160411D K4E170412D, K4E160412D
READ CYCLE
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tCSH tRCD tRSH tCAS
tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH
tWEZ tAA
OE VIH VIL -
tCEZ tOEZ tOEA
DQ0 ~ DQ3(7) VOH VOL -
tRAC OPEN
tOLZ tCAC tCLZ
tREZ
DATA-OUT
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS VIH VIL -
tRCD tRAD
tRSH tCAS
tCRP
tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tRWL tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ3(7) VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tCSH tRCD tRSH tCAS tCRP
tRAD tRAL tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
OE
VIH VIL -
tOED tDS
tOEH tDH
DATA-IN
DQ0 ~ DQ3(7) VIH VIL -
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tRCD tRAD tRAH
tRSH tCAS
tASR
VIH VIL -
tASC
tCAH tCSH
A
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
W VIH VIL -
tRWL tCWL tWP
tRWD
OE VIH VIL -
tOEA tOLZ tCLZ tCAC tAA tRAC
VALID DATA-OUT
tOED tOEZ tDS tDH
VALID DATA-IN
DQ0 ~ DQ3(7) VI/OH VI/OL -
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
HYPER PAGE READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP
tCSH tCRP
CAS VIH VIL -
tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS
tRCD tCAS tRAD
tASR
A VIH VIL -
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR
tASC
tCAH
tREZ
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRRH tRCH
tCAC tAA tCPA tAA tOCH tOEA tCAC tOEA tOEP
tCAC tAA tCPA
tCPA tCAC tAA tCHO tOEP
OE
VIH VIL -
tOEA tOEZ
VALID DATA-OUT VALID DATA-OUT
DQ0 ~ DQ3(7) VOH VOL -
tRAC
tDOH
VALID DATA-OUT
tOEZ
tOEZ
tOLZ tCLZ
VALID DATA-OUT
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
CAS VIH VIL -
tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS
o
tHPC tCP
tRSH tCAS
tASR
A VIH VIL -
tRAH
tCAH
tASC
tCAH
o o
tASC
tCAH
ROW ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP tCWL
o o o
tWCS
tWCH tWP tCWL tRWL
tWP tCWL
OE
VIH VIL -
DQ0 ~ DQ3(7) VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
HYPER PAGE READ-MODIFY-WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tRSH tHPRWC
tCSH tCRP
tRCD tCAS tRAD tRAH
tCP tCAS tRAL tASC
COL. ADDR COL. ADDR
tCRP
CAS
VIH VIL -
tASR
A VIH VIL ROW ADDR
tASC
tCAH
tCAH
tRCS
W VIH VIL -
tCWL tWP tCWD tAWD tCPWD tOEA tOED
tRWL tCWL tWP
tCWD tAWD tRWD tOEA tCAC tAA tCAC
OE
VIH VIL -
tOED tDH tDS tAA tDH tOEZ tDS
tOEZ
DQ0 ~ DQ3(7) VI/OH VI/OL -
tRAC tCLZ tOLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN
tOLZ
VALID DATA-OUT
VALID DATA-IN
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
HYPER PAGE READ AND WRITE MIXED CYCLE
CMOS DRAM
tRASP
RAS VIH VIL READ(tCAC) READ(tCPA) WRITE READ(tAA)
tRP
tHPC tCP
CAS VIH VIL -
tHPC tCP tCP tCAS tASC
COL. ADDR
tRHCP tHPC tCAS tASC tCAH
COL. ADDR
tRAD tASR tRAH tASC
tCAS tCAH
tCAS tCAH
tCAH
tASC
COLUMN ADDRESS
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRCH
tRCS
tRCH tWCS
tWCH
tRCH
tWPE tCLZ tCPA
OE VIH VIL -
tWED
DQ0 ~ DQ3(7) VI/OH VI/OL -
tOEA tCAC tAA tRAC
tWEZ
tDH tWEZ
VALID
DATA-OUT
tDS tCLZ
VALID DATA-IN
tAA
VALID DATA-OUT
tREZ
VALID DATA-OUT
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC
RAS VIH VIL -
CMOS DRAM
tRP
tRAS tCRP tRPC tCRP
CAS
VIH VIL -
tASR
A VIH VIL -
tRAH
ROW ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Dont care
tRP
RAS VIH VIL -
tRC tRAS
tRP
tRPC tCP tCSR tCHR
tRPC
CAS
VIH VIL -
tWRP
W VIH VIL -
tWRH
DQ0 ~ DQ3(7) VOH VOL -
tCEZ OPEN
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
HIDDEN REFRESH CYCLE ( READ )
CMOS DRAM
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS
tCRP
CAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tRAL tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tWRH
tAA
OE VIH VIL -
tOEA tOLZ tCAC tCEZ tREZ tWEZ tOEZ
DATA-OUT
DQ0 ~ DQ3(7) VOH VOL -
tCLZ tRAC OPEN
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS tCRP
tRCD
tRSH
tCHR
CAS
VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tWRH tWCS
W VIH VIL -
tWRP tWCH tWP
OE
VIH VIL -
tDS
DQ0 ~ DQ3(7) VIH VIL -
tDH
DATA-IN
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Dont care
CMOS DRAM
tRP
RAS VIH VIL -
tRASS
tRPS
tRPC tCP tCHS tCSR
tRPC
CAS
VIH VIL -
DQ0 ~ DQ3(7) VOH VOL -
tCEZ OPEN
W
VIH VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Dont care tRC tRAS tRPC tCP
CAS VIH VIL -
tRP
RAS VIH VIL -
tRP
tRPC tCSR tCHR
tWTS
W VIH VIL -
tWTH
DQ0 ~ DQ3(7) VOH VOL -
tOFF OPEN
Dont care Undefined
K4E170411D, K4E160411D K4E170412D, K4E160412D
PACKAGE DIMENSION
26(24) SOJ 300mil
CMOS DRAM
Units : Inches (millimeters)
#26(24) 0.330 (8.39) 0.340 (8.63) 0.300 (7.62) 0.260 (6.61) 0.280 (7.11) 0.004 (0.10) 0.010 (0.25)
0.006 (0.15) 0.012 (0.30)
0.691 (17.55) MAX 0.670 (17.03) 0.680 (17.28)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53)
26(24) TSOP(II) 300mil
0.148 (3.76) MAX
0.027 (0.69) MIN
Units : Inches (millimeters)
0.355 (9.02) 0.371 (9.42)
0.691 (17.54) MAX 0.671 (17.04) 0.679 (17.24) 0.047 (1.20) MAX 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8
O
0.037 (0.95)
0.050 (1.27)
0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50)
0.300 (7.62)

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