View ICS9248-189_26375.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS9248-189
Advance Information
AMD - K7TM Clock Generator for Mobile System
Recommended Application: VIA K7/KN/KX-133 style chipset Output Features: * 1 - Differential pair open drain CPU clocks * 1 - CPU clock @ 3.3V * 7 - SDRAM @ 3.3V * 8 - PCI @ 3.3V, * 1 - 48MHz, @ 3.3V fixed * 1 - 24/48MHz @ 3.3V * 3 - REF @ 3.3V, 14.318MHz. Features: * Up to 166MHz frequency support * Support power management via hardware select CPU stop, CLOCK stop, PCI stop, and SDRAM stop * Support power management via I2C programing * Spread spectrum for EMI control ( 0.25% to 0.06% center, or 0 to -0.5% or -1.0% down spread) * Uses external 14.318MHz crystal Key Specifications: * CPU - CPU Skew: <175ps * CPU - SDRAM Skew: 125ps * CPU - PCI Skew: 100ps * PCI - PCI Skew: <500ps
Pin Configuration
VDDREF X1 X2 *FS2/PCICLK_F *FS1/PCICLK0 VDDPCI GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 GND VDDPCI PCICLK6 *SDRAM_STOP# *PCI_STOP# BUFFER_IN AVDD GND GND *FS0/48MHZ *SEL24_48#/24_48MHz VDD48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0 REF1 REF2/FS3* GND GND VDD CPUCLK_CS 2 CPUCLKT0 2 CPUCLKC0 CPU_STOP#* CLK_STOP#*/PD# SDRAM0 SDRAM1 VDDSDR GND SDRAM2 SDRAM3 GND VDDSDR SDRAM4 SDRAM5 SDRAM_F SCLK SDATA
1
48-Pin 300mil SSOP & 240mil TSSOP
* Internal Pull-up Resistor of 120K to VDD 1 These outputs have double strength to drive 2 loads. 2 These outputs can be set to 1X or 1.5X strength through I2C
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum
3
Functionality
FS2
48MHz 24_48MHz REF (2:0)
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
CPU 100.00 133.33 100.00 133.33 100.00 133.33 100.00 133.33
ICS9248-189
PCI 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33
S p re a d Pe rc e n t a g e +/- 0.35% Center Spread +/- 0.35% Center Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread +/- 0.6% Center Spread +/- 0.6% Center Spread No Spread No Spread
0 0 0 0 1 1 1 1
CPU DIVDER
Stop
CPUCLK_CS CPUCLKT0 CPUCLKC0
SEL24_48# SDATA SCLK FS (3:0) PD# CPU_STOP# CLK_STOP# PCI_STOP# SDRAM_STOP# BUFFER_IN
Control Logic
PCI DIVDER
Stop
7
PCICLK (6:0) PCICLK_F
Note: For a complete functionality table please see table in page 3.
Power Groups
VDD48 = 48MHz, Fixed PLL VDDA = VDD for Core PLL VDDREF = REF, Xtal
Config. Reg.
SDRAM DIVIDER
Stop
6
SDRAM (5:0) SDRAM_F
9248-189 Rev - 08/10/01 Third party brands and names are the property of their respective owners.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS9248-189
Advance Information
General Description
The ICS9248-189 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides all clocks required for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-189 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Descriptions
PIN NUMBER 1, 6, 14, 24, 30, 35, 43 2 3 4
P I N NA M E VDD X1 X2 FS2
1, 2
TYPE PWR IN OUT IN OUT IN OUT PWR OUT IN IN IN PWR PWR IN OUT IN OUT I/O IN OUT OUT IN
DESCRIPTION Power supply, nominal 3.3V Crystal input, has internal load cap (36pF) and feedback resistor from X2. Crystal output, nominally 14.318MHz. Has internal load cap (36pF). Frequency select pin, latched input Free running PCI clock not affected by PCI_STOP# for power management. Frequency select pin, latched input PCI clock output Ground PCI clock outputs Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input low. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. Input to Fanout Buffers for SDRAM outputs. Supply for core, & CPU 3.3V Analog ground Frequency select pin, latched input 48MHz output clock Logic input to select 24 or 48MHz 24MHz/48MHz clock output Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant Free running SDRAM clock not affected by SDRAM_STOP# for power management. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Powers down chip, active low except XTAL and CPUCLK_T0 & CPUCLKC0. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Only stops CPUCLK_CS "Complementary" clock of differential pair CPU output. This open drain outputs needs an external 1.5V pull-up. "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. CPU clock to the chipset 14.318 Mhz reference clock Frequency select pin, latched Input 14.318 Mhz reference clock
PCICLK_F
FS11, 2 PCICLK0 7, 13, 21, 31, 34, 44, 45 GND 15, 12, 11, 10, 9, 8 PCICLK (6:1)
5
16 17
18 19 20 22 23 25
SDRAM_STOP#1 PCICLK_STOP# BUFFER IN AVDD AGND FS01, 2 48MHz SEL24_48#1, 2 24_48MHz SDATA SCLK SDRAM_F SDRAM (5:0) CLK_STOP#1
1
26
27 28, 29, 32, 33, 36, 37
38
PD#
IN
39 40 41 42 46 47, 48
CPU_STOP#1, CPUCLKC0 CPUCLKT0 CPUCLK_CS REF2 FS31, 2 REF0 (1:0)
IN OUT OUT OUT OUT IN OUT
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-189
Advance Information
Serial Configuration Command Bitmap
Functionality and Frequency Select Register (default = 0)
Bit Bit 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bit 2:1, Bit 6:4
Description CPUCLK PCICLK (MHz) (MHz) 166.00 41.6 160.00 40.0 155.00 38.7 150.00 37.5 145.00 36.2 140.00 35.0 136.00 34.00 130.00 32.5 127.00 31.7 124.00 31.00 120.00 40.00 118.00 39.3 116.00 38.60 115.00 38.30 114.00 38.00 113.00 37.60 112.00 37.30 111.00 37.00 110.00 36.60 108.00 36.00 106.00 35.30 104.00 34.60 102.00 34.00 95.00 31.70 100.00 33.33 133.33 33.33 100.00 33.33 133.33 33.33 100.00 33.33 133.33 33.33 100.00 33.33 133.33 33.33
PWD Spread Precentage OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OF F OFF OFF OFF OFF OF F OF F OF F OFF OFF OFF OFF OFF OFF +/- 0.35% Center Spread +/- 0.35% Center Spread 0 to - 0.50% Down Spread 0 to - 0.50% Down Spread +/- 0.60% Center Spread +/- 0.60% Center Spread OFF OFF
Reserved 00101
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
3
ICS9248-189
Advance Information
Byte 0: CPU, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
38 4 5 22 46 -
PWD
0 0 0 0 0 1 0 0
DESCRIPTION
CLK_STOP# (1 = PD#, 0 = CLK_STOP#) FS2 FS1 FS0 Hardware / Software Frequency selection Reserved FS3 Reserved
PIN#
40, 41 42 41 40
PWD
0 0 0 0 1 1 1 1
DESCRIPTION
Reserved Reserved Reserved Reserved CPUCLKC0/T0 ( 1 = 1X, 0 = 1.5X ) CPUCLK_CS CPUCLKT0 CPUCLKC0
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
15 12 11 10 9 8 5 4
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 PCICLK_F
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
23 22 23 27 28, 29 32, 33 36, 37
PWD
0 0 1 1 1 1 1 1
DESCRIPTION
Reserved SEL24_48# 48MHz 24_48MHz SDRAM_F SDRAM(5:4) SDRAM(3:2) SDRAM(1:0)
Byte 4: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
0 0 0 0 0 0 0 0
DESCRIPTION
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
22 5 4 46 23 46 47 48 X X X X X 1 1 1
DESCRIPTION
FS0 (readback) FS1 (readback) FS2 (readback) FS3 (readback) SEL24_48# (readback) REF2 REF1 REF0
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
4
ICS9248-189
Advance Information
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 7: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
0 0 0 0 0 0 0 0
DESCRIPTION
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
0 0 0 0 0 0 0 0
DESCRIPTION
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: Don't write into this register, writing into this register can cause malfunction
Third party brands and names are the property of their respective owners.
5
ICS9248-189
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL1 VIN = 0 V; Inputs with pull-up resistors Input Low Current IIL2 IDD3.3OP66 CL = 0 pF; Select @ 66MHz Operating Supply IDD3.3OP100 CL = 0 pF; Select @ 100MHz Current IDD3.3OP133 CL = 0 pF; Select @ 133MHz VDD = 3.3 V; Input frequency Fi CIN Logic Inputs 1 Input Capacitance CINX X1 & X2 pins 1 Clk Stabilization TSTAB From VDD = 3.3 V to 1% target Freq. tCPU-SDRAM VT = 50% tCPU-PCI Skew1 tCPU-AGP
1
MIN 2 VSS-0.3 -5 -200
TYP
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 180 mA MHz pF pF ms ps
12 27 -125 -100 -500
14.318
16 5 45 3 125 100 500
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-189
Advance Information
Electrical Characteristics - USB or 48MHz, REF
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50%
MIN 2.4
TYP
16
MAX UNITS V 0.4 V -22 mA mA 4 4 ns ns %
Duty Cycle
45
55
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLKT0/CPUCLKC0 (Open Drain)
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Time
1
SYMBOL ZO VOH2B VOL2B IOL2B tr2B tf2B VDIF VDIF VX dt2B tsk2B tjcyc-cyc2B tjabs2B
CONDITIONS VO = VX Termination to Vpull-up(external) Termination to Vpull-up(external) VOL = 0.3 V VOL = 0.3 V, VOH = 1.2 V VOH = 1.2 V, VOL = 0.3 V Note 2 Note 2 Note 3 VT = 50% VT = 50% VT = VX VT = 50%
MIN
TYP
MAX
UNITS V V mA
1
1.2 0.4
18 0.9 0.9 0.4 0.2 550 45 Vpullup(external) + 0.6 Vpullup(external) + 0.6 1100 55 200 250 +250
ns ns V V mV % ps ps ps
Fall Time1 Differential voltage-AC1 Differential voltage-DC1 Differential Crossover Voltage1 Duty Cycle1 Skew1 Jitter, Cycle-to-cycle1 Jitter, Absolute1
-250
Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpullup(external) = 1.5V, Min = Vpullup (external)/2-150mV; Max=(Vpullup (external)/2)+150mV
Third party brands and names are the property of their respective owners.
7
ICS9248-189
Advance Information
Electrical Characteristics - CPUCLK_CS
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B tf2B
1 1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
TYP
19
MAX UNITS V 0.4 V -19 mA mA 1.6 1.6 ns ns % ps ps ps ps
d t2B1 tsk2B1 tjcyc-cyc2B1 tj1s2B1 tjabs2B1
45
55 175 250 150
-250
+250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 Tsk
1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50% VT = 1.5V
MIN 2.6
TYP
19
MAX UNITS V 0.4 V -16 mA mA 2 2 ns ns % ps
Duty Cycle
1
45
55 500
Skew (window)
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-189
Advance Information
Electrical Characteristics - PCICLK_F
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 Tsk
1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50% VT = 1.5V
MIN 2.6
TYP
12
MAX UNITS V 0.4 V -12 mA mA 2 2 ns ns % ps
Duty Cycle
1
45
55 200
Skew (window)
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50% VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
16
MAX UNITS V 0.4 V -22 mA mA 4 4 ns ns % ns ns
Duty Cycle
45 -1
55 0.5 1
Jitter, One Sigma Jitter, Absolute
1
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-189
Advance Information General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
Third party brands and names are the property of their respective owners.
10
ICS9248-189
Advance Information
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
ICS9248-189
Advance Information
CLK_STOP# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. CLK_STOP# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When CLK_STOP# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP# is considered to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
CLK_STOP#
CPUCLKT CPUCLKC
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-189 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. CLK_STOP# is an input pin which stops all clocks, expcpt XTAL and CPUCLKT0/CPUCLKC0 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
12
ICS9248-189
Advance Information
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-189. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-189. 3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
13
ICS9248-189
Advance Information
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 48
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 15.748 MAX 16.002 MIN .620
D (inch) MAX .630
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9248yF-189-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
14
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS9248-189
Advance Information
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 0.80 0.17 1.20 0.15 1.05 0.27 .002 .032 .007 .047 .006 .041 .011
A A1 A2 b c D E E1 e L N aaa VARIATIONS
0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20
.0035 .008 SEE VARIATIONS 0.319 .236 .244 0.020 BASIC .018 .30 SEE VARIATIONS 0 8 .004
0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 0.10
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
N 48
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
7/6/00 Rev B
MO-153 JEDEC Doc.# 10-0039
Ordering Information
ICS9248yG-189-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
15
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.

▲Up To Search▲

Price & Availability of ICS9248-189

	To Download ICS9248-189 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .