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| KM23C4100D(E)T 4M-Bit (512Kx8 /256Kx16) CMOS MASK ROM FEATURES * Switchable organization 524,288 x 8(byte mode) 262,144 x 16(word mode) * Fast access time : 80ns(Max.) * Supply voltage : single +5V * Current consumption Operating : 50mA(Max.) Standby : 50A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package -. KM23C4100D(E)T : 44-TSOP2-400 CMOS MASK ROM GENERAL DESCRIPTION The KM23C4100D(E)T is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 524,288 x 8 bit(byte mode) or as 262,144 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23C4100D(E)T is packaged in a 44-TSOP2. FUNCTIONAL BLOCK DIAGRAM A17 X BUFFERS AND DECODER MEMORY CELL MATRIX (262,144x16/ 524,288x8) PRODUCT INFORMATION Product KM23C4100DT KM23C4100DET Operating Temp 0C~70C -20C~85C Vcc Range 5.0V Speed (ns) 80 . . . . . . . . A0 A-1 Y BUFFERS AND DECODER SENSE AMP. DATA OUT BUFFERS PIN CONFIGURATION N.C 1 2 3 4 5 6 7 8 9 44 N.C 43 N.C 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 ... CE OE BHE CONTROL LOGIC Q0/Q8 Q7/Q15 N.C A17 A7 A6 A5 A4 A3 A2 A1 10 A0 11 Pin Name A0 - A17 Q0 - Q14 Q15 /A-1 BHE CE OE VCC VSS N.C Pin Function Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power(+5V) Ground No Connection CE 12 VSS 13 OE 14 Q0 Q1 Q9 Q2 Q10 15 17 18 19 20 Q8 16 TSOP 33 BHE 32 VSS 31 Q15/A-1 30 Q7 29 Q14 28 Q6 27 Q13 26 Q5 25 Q12 24 Q4 23 VCC Q3 21 Q11 22 KM23C4100D(E)T KM23C4100D(E)T ABSOLUTE MAXIMUM RATINGS Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Operating Temperature Symbol VIN TBIAS TSTG TA Rating -0.3 to +7.0 -10 to +85 -55 to +150 0 to +70 -20 to +85 CMOS MASK ROM Unit V C C C C Remark KM23C4100DT KM23C4100DET NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum ratin conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS) Item Supply Voltage Supply Voltage Symbol VCC VSS Min 4.5 0 Typ 5.0 0 Max 5.5 0 Unit V V DC CHARACTERISTICS Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400A IOL=2.1mA Test Conditions CE=OE=VIL, all outputs open CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC Min 2.2 -0.3 2.4 Max 50 1 50 10 10 VCC+0.3 0.8 0.4 Unit mA mA A A A V V V V NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. MODE SELECTION CE H L L OE X H L BHE X X H L Q15/A-1 X X Output Input Mode Standby Operating Operating Operating Data High-Z High-Z Q0~Q15 : Dout Q0~Q7 : Dout Q8~Q14 : Hi-Z Power Standby Active Active Active CAPACITANCE(TA=25C, f=1.0MHz) Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V Min8M bit Max 10 10 Unit pF pF NOTE : Capacitance is periodically sampled and not 100% tested. KM23C4100D(E)T AC CHARACTERISTICS(VCC=5V10%, unless otherwise noted.) TEST CONDITIONS Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value CMOS MASK ROM 0.6V to 2.4V 10ns 0.8V and 2.0V 1 TTL Gate and CL=100pF READ CYCLE Item Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change Symbol tRC tACE tAA tOE tDF tOH 0 KM23C4100D(E)T-8 Min 80 80 80 40 20 0 Max KM23C4100D(E)T-10 Min 100 100 100 50 20 0 Max KM23C4100D(E)T-12 Min 120 120 120 60 20 Max Unit ns ns ns ns ns ns TIMING DIAGRAM READ ADD A0~A17 A-1(*1) tACE CE tOE OE tOH DOUT D0~D7 D8~D15(*2) VALID DATA VALID DATA tAA ADD1 tRC ADD2 tDF(*3) NOTES : *1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE=VIL) *2. Word Mode only.(BHE = VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level. KM23C4100D(E)T PACKAGE DIMENSIONS 44-TSOP2-400 CMOS MASK ROM (Unit : mm/inch) 0~8 0.25 ( ) 0.010 #44 #23 0.45 ~0.75 0.018 ~ 0.030 11.760.20 0.4630.008 10.16 0.400 ( 0.50 ) 0.020 #1 #22 1.000.10 0.0390.004 1.20 MAX. 0.047 + 0.10 - 0.05 + 0.004 0.006 - 0.002 0.15 18.81 MAX. 0.741 18.410.10 0.7250.004 ( 0.805 ) 0.032 0.350.10 0.0140.004 0.80 0.0315 0.05 MIN. 0.002 0.10 MAX 0.004 |
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