View M5M44800CJ_29302.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M5M44800CJ,TP-5,-6,-7, M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S -5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BYBY 8-BIT) DYNAMIC RAM FAST PAGE MODE 4194304-BIT (524288-WORD 8-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 524288-word by 8-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for largecapacity memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application.
MITSUBISHI LSIs MITSUBISHI LSIs
PIN CONFIGURATION (TOP VIEW)
(5V)VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 NC 6 W 7 9 RAS 8 A9
28 VSS(0V) 27 DQ8 26 DQ7 25 DQ6 24 DQ5 23 CAS 22 OE 21 NC 20 A8 19 A7 18 A6 17 A5 16 A4 15 VSS(0V)
FEATURES
Type name
M5M44800CXX-5,-5S M5M44800CXX-6,-6S M5M44800CXX-7,-7S
RAS CAS Address OE Cycle Power access access access access time dissipation time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
A0 10 A1 11 A2 12 A3 13 (5V)VCC 14
50 60 70
13 15 20
25 30 35
13 15 20
90 110 130
450 375 325
XX=J,TP
Outline 28P0K(400mil SOJ)
Standard 28pin SOJ, 28pin TSOP (II) Single 5V10% supply Low stand-by power dissipation CMOS lnput level 5.5mW (Max) CMOS Input level 550W (Max) * Operating power dissipation M5M44800Cxx-5,-5S 495mW (Max) M5M44800Cxx-6,-6S 413mW (Max) M5M44800Cxx-7,-7S 358mW (Max) Self refresh capability * Self refresh current 150A(Max) Extended refresh capability Extended refresh current 150A(Max) Fast page mode(1024-column random access),Read-modify-write, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities. Early-write mode, CAS and OE to control output buffer impedance 1024 refresh cycles every 16.4ms (A0 ~A9) 1024 refresh cycles every 128ms (A0 ~A9) * * :Applicable to self refresh version (M5M44800CJ,TP-5S,-6S,-7S :option) only
(5V)VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 NC 6 W A9 7 9 RAS 8 A0 10 A1 11 A2 12 A3 13 (5V)VCC 14
28 VSS(0V) 27 DQ8 26 DQ7 25 DQ6 24 DQ5 23 CAS 22 OE 21 NC 20 A8 19 A7 18 A6 17 A5 16 A4 15 VSS(0V)
Outline 28P3Y-H(400mil TSOP Normal Bend) APPLICATION
Microcomputer memory, Refresh memory for CRT
NC:NO CONNECTION
PIN DESCRIPTION
Pin name A0~A9 DQ1~DQ8 RAS CAS W OE Vcc Vss Function Address inputs Data inputs/outputs Row address strobe input Column address strobe input Write control input Output enable input Power supply (+5V) Ground (0V)
1
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
FUNCTION
In addition to normal read, write, and read-modify-write operations the M5M44800CJ, TP provides a number of other functions, e.g., fast page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation Read Write (Early write) Write (Delayed write) Read-modify-write RAS only refresh Hidden refresh
CAS before RAS (Extended *) refresh
Inputs RAS ACT ACT ACT ACT ACT ACT ACT ACT NAC CAS ACT ACT ACT ACT NAC ACT ACT ACT DNC W NAC ACT ACT ACT DNC DNC DNC DNC DNC OE ACT DNC DNC ACT DNC ACT DNC DNC DNC
Row address Column address
Input/Output APD APD APD APD APD DNC DNC DNC DNC APD APD APD APD DNC DNC DNC DNC DNC Input OPN VLD VLD VLD DNC OPN DNC DNC DNC Output VLD OPN IVD VLD OPN VLD OPN OPN OPN
Refresh YES YES YES YES YES YES YES YES NO
Remark Fast page mode identical
Self refresh * Stand-by
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open
BLOCK DIAGRAM
COLUMN ADDRESS STROBE INPUT CAS ROW ADDRESS RAS STROBE INPUT WRITE CONTROL INPUT W A0~A8
VCC (5V)
CLOCK GENERATOR CIRCUIT
VCC (5V) VSS (0V) VSS (0V) (8) DATA IN BUFFER
COLUMN DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
SENSE REFRESH AMPLIFIER & I /O CONTROL
ADDRESS INPUTS
ROW & COLUMN ADDRESS BUFFER
ROW A0~ A9 DECODER
MEMORY CELL (4194304BITS)
(8) DATA OUT BUFFER
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DATA INPUTS / OUTPUTS
OE OUTPUT ENABLE INPUT
2
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to VSS Ratings -1~7 -1~7 -1~7 50 1000 0~70 -65~150 Unit V V V mA mW C C
Ta=25C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70C, unless otherwise noted)
Symbol VCC VSS VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Min 4.5 0 2.4 -0.5 * * Limits Nom 5.0 0 Max 5.5 0 6.0 0.8
(Note 1)
Unit V V V V
Note 1 : All voltage values are with respect to Vss. * * : VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to VSS.)
ELECTRICAL CHARACTERISTICS (Ta=0~70C, VCC=5V10%, VSS=0V, unless otherwise noted) (Note 2)
Symbol VOH VOL IOZ II ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current
M5M44800C-5,-5S Average supply current M5M44800C-6,-6S from VCC, operating (Note 3,4,5) M5M44800C-7,-7S
Test conditions IOH=-5mA IOL=4.2mA Q floating, 0V VOUT 5.5V 0V VIN +6.0V, Other inputs pins=0V RAS, CAS cycling tRC=tWC=min. output open RAS= CAS =VIH, output open RAS= CAS VCC -0.5V output open RAS cycling, CAS= VIH tRC=min. output open RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. output open
Min 2.4 0 -10 -10
Limits Typ
ICC2
Supply current from VCC, stand-by
(Note 6)
ICC3 (AV)
M5M44800C-5,-5S Average supply current M5M44800C-6,-6S from VCC, RAS only refresh mode (Note 3,5) M5M44800C-7,-7S M5M44800C-5,-5S Average supply current M5M44800C-6,-6S from VCC, Fast Page (Note 3,4,5) M5M44800C-7,-7S Mode M5M44800C-5,-5S Average supply current from VCC, CAS before RAS M5M44800C-6,-6S refresh mode (Note 3,5) M5M44800C-7,-7S
ICC4(AV)
ICC6(AV)
Max Vcc 0.4 10 10 90 75 65 2 1.0 0.1 * 90 75 65 90 75 65 80 65 55
Unit V V A A mA
mA
mA
mA
mA
ICC8(AV) *
Average supply current from VCC, Extended-Refresh mode
RAS cycling CAS 0.2V or CAS before RAS refresh cycling RAS 0.2V or VCC-0.2V CAS 0.2V or VCC-0.2V (Note 6) W 0.2V or VCC-0.2V OE 0.2V or VCC-0.2V A0~A9 0.2V or VCC-0.2V, DQ=open tRC=125s, tRAS=tRASmin~1s (Note 6) RAS=CAS 0.2V output open
150
A
ICC9(AV) *
Note Note Note Note
Average supply current from VCC, Self-Refresh mode
150
A
2: Current flowing into an IC is positive, out is negative. 3: ICC1 (AV), ICC3 (AV), ICC4 (AV) and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column address can be changed once or less while RAS=VIL and CAS=VIH
3
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70C, VCC=5V10%, VSS=0V, unless otherwise noted)
Limits Symbol CI (A) CI (CLK) CI / O Parameter Input capacitance, address inputs Input capacitance, clock inputs Input/Output capacitance, data ports Test conditions VI=VSS f=1MHz VI=25mVrms Min Typ Max 5 7 7 Unit pF pF pF
SWITCHING CHARACTERISTICS (Ta=0~70C, VCC = 5V10%, VSS=0V, unless otherwise noted, see notes 6,13,14)
Limits Symbol tCAC tRAC tAA tCPA tOEA tCLZ tOFF tOEZ Parameter Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE Output low impedance time from CAS low Output disable time after CAS high Output disable time after OE high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 7) (Note 12) (Note 12)
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit ns ns ns ns ns ns ns ns
Min
Max 13 50 25 30 13
Min
Max 15 60 30 35 15
Min
Max 20 70 35 40 20
5 13 13
5 15 15
5 20 20
Note 6:An initial pause of 500s is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh cycles). Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 16.4ms) of RAS inactivity before proper device operation is achieved. Note 7:Measured with a load circuit equivalent to 2TTL loads and 100pF. Note 8:Assumes that tRCD tRCD(max) and tASC tASC(max). Note 9:Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. nOR10:Assumes that tRAD tRAD(max) and tASC tASC(max). Note11:Assumes that tCP tCP(max) and tASC tASC(max). Note12:tOFF(max), tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT 10A ) and is not reference to VOH(min) or VOL(max).
4
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)
(Ta=0~70C, VCC = 5V10%, VSS=0V, unless otherwise noted, see notes 6,13,14) Limits Symbol tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD tT Refresh cycle time Refresh cycle time * RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low 30 18 5 0 10 13 0 0 8 13 0 0 13 13 1 Parameter
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min
Max 16.4 128
Min
Max 16.4 128
Min
Max 16.4 128
(Note 15)
37
(Note 16) (Note 17)
25 7
Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data Transition time Note 13: The timing requirements are assumed tT=5ns.
(Note 18) (Note 18) (Note 19) (Note 19) (Note 20)
50
40 20 5 0 10 15 0 0 10 15 0 0 15 15 1
45
30 10
50
50 20 5 0 10 15 0 0 10 15 0 0 20 20 1
50
35 10
50
Note 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Note 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. Note 16: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. Note 17: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. Note 18: Either tDZC or tDZO must be satisfied. Note 19: Either tCDD or tODD must be satisfied. Note 20: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH Parameter
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns
Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read Setup time before CAS low Read hold time after CAS high Read hold time after RAS high Column address to RAS hold time CAS hold time after OE low RAS hold time after OE low Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
(Note 21) (Note 21)
Min 90 50 13 50 13 0 0 0 25 13 13
Max 10000 10000
Min 110 60 15 60 15 0 0 0 30 15 15
Max 10000 10000
Min 130 70 20 70 20 0 0 0 35 20 20
Max 10000 10000
5
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH Parameter Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low OE hold time after W low
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
(Note 23)
Min 90 50 13 50 13 0 8 13 13 8 0 8 13
Max 10000 10000
Min 110 60 15 60 15 0 10 15 15 10 0 10 15
Max 10000 10000
Min 130 70 20 70 20 0 15 20 20 15 0 15 20
Max 10000 10000
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tWP tDS tDH tOEH Parameter Read write/read modify write cycle time
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit
(Note 22) ns ns 10000 10000 10000 RAS low pulse width 10000 10000 10000 ns CAS low pulse width CAS hold time after RAS low 86 100 120 ns ns RAS hold time after CAS low 49 55 70 0 0 0 Read setup time before CAS low ns (Note 23) 31 35 45 Delay time, CAS low to W low ns (Note 23) 68 80 95 Delay time, RAS low to W low ns (Note 23) Delay time, address to W low 43 50 60 ns 13 15 20 ns CAS hold time after W low 13 15 20 ns RAS hold time after W low ns 8 10 15 Write pulse width ns 0 0 0 Data setup time before CAS low or W low ns Data hold time after CAS low or W low 8 10 15 13 15 20 ns OE hold time after W low Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. Note 23: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD(min), tAWD tAWD(min) and tCPWD tCPWD(min) (for fast page
mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.
Min 126 86 49
Max
Min 150 100 55
Max
Min 180 120 70
Max
6
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Fast Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle)
Symbol tPC tPRWC tRAS tCP tCPRH tCPWD Parameter Fast page mode read/write cycle time Fast page mode read write/read modify write cycle time (Note 25) RAS low pulse width for read or write cycle (Note 26) CAS high pulse width RAS hold time after CAS precharge (Note 23) Delay time, CAS precharge to W low
(Note 24)
Limits
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit ns ns ns ns ns ns
Min 35 71 85 8 30 48
Max
100000 12
Min 40 80 100 10 35 55
Max
Min 45 95 115 10 40 65
Max
100000 15
100000 15
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle. Note 25: tRAS(min) is specified as two cycles of CAS input are performed. Note 26: tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle, Extended Refresh Cycle *
Symbol tCSR tCHR tCAS Parameter CAS setup time before RAS low CAS hold time after RAS low CAS low pulse width
(Note 27)
Limits
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit ns ns ns
Min 5 10 20
Max
Min 5 10 20
Max
Min 5 15 25
Max
Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Self Refresh Cycle *
Symbol tRASS tRPS tCHS
(Note 28)
Limits Parameter CBR self refresh RAS low pulse width CBR self refresh RAS high precharge time CBR self refresh CAS hold time
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit s ns ns
Min 100 90 -50
Max
Min 100 110 -50
Max
Min 100 130 -50
Max
7
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 29)
tRC tRAS VIH RAS VIL tCSH tCRP VIH VIL tRAD tASR A0~A9 VIH VIL tRAH tASC tCAH
ROW ADDRESS
tRP
tRCD tCAS
tRSH
tCRP
CAS
tRAL
tASR
ROW ADDRESS
COLUMN ADDRESS
tRCS VIH W VIL tDZC DQ1~DQ8 (INPUTS) VIH VIL tCAC tAA tCLZ VOH DQ1~DQ8 (OUTPUTS) VOL
Hi-Z DATA VALID Hi-Z
tRRH tRCH
tCDD
tOFF
Hi-Z
tRAC tDZO VIH OE VIL tORH tOEA tOCH
tOEZ tODD
Note 29
Indicates the don't care input. VIH(min)VINVIH(max) or VIL(min)VINVIL(max) Indicates the invalid output.
8
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Write Cycle (Early write)
tWC tRAS RAS VIH VIL tCSH tCRP VIH VIL tASR VIH VIL tRAH tASC tCAH
COLUMN ADDRESS
tRP
tRCD
tRSH tCAS
tCRP
CAS
tASR
A0~A9
ROW ADDRESS
ROW ADDRESS
tWCS VIH W VIL tDS DQ1~DQ8 (INPUTS) VIH
tWCH
tDH
DATA VALID
VIL
VOH DQ1~DQ8 (OUTPUTS) VOL
Hi-Z
VIH OE VIL
9
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Write Cycle (Delayed write) tWC tRAS
RAS VIH VIL
tRP
tCSH tCRP tRCD tCAS tRSH tCRP
CAS
VIH VIL
tASR
VIH VIL
tRAH
tASC
tCAH
tASR
ROW ADDRESS
A0~A9
ROW ADDRESS
COLUMN ADDRESS
tCWL tRCS
VIH W VIL
tRWL tWP
tWCH tDZO
DQ1~DQ8 (INPUTS) VIH VIL
Hi-Z
tDS
tDH
DATA VALID
tCLZ
VOH DQ1~DQ8 (OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO
VIH OE VIL
tOEZ tODD
tOEH
10
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH RAS VIL tCRP tCSH tRCD tRSH tCAS tCRP tRP
CAS
VIH VIL tASR tRAH tRAD tASC tCAH tASR
A0~A9
VIH VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH VIL tDZC DQ1~DQ8 (INPUTS) VIH VIL
Hi-Z
tAWD tCWD tRWD
tCWL tRWL tWP
W
tDS
tDH
DATA VALID
tCAC tAA tCLZ
Hi-Z DATA VALID Hi-Z
VOH DQ1~DQ8 (OUTPUTS) VOL
tRAC tDZO VIH OE VIL
tODD tOEA tOEZ
tOEH
11
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS VIH RAS VIL tCRP VIH VIL tASR tRAH tASR tRPC tCRP tRP
CAS
A0~A9
VIH VIL
ROW ADDRESS
ROW ADDRESS
VIH W VIL
DQ1~DQ8 (INPUTS)
VIH VIL
VOH DQ1~DQ8 (OUTPUTS) VOL
Hi-Z
VIH OE VIL
12
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle, Extended Refresh Cycle *
tRC tRP VIH RAS VIL tRPC CAS VIH VIL tCPN VIH VIL tRCH VIH W VIL tCSR tCHR tRPC tCSR tCHR tRAS tRAS
tRC tRP
tRPC
tCRP
tASR
A0~A9
ROW ADDRESS
COLUMN ADDRESS
tRCS
tCDD DQ1~DQ8 (INPUTS) VIH VIL tOFF VOH DQ1~DQ8 (OUTPUTS) VOL tOEZ tODD VIH OE VIL
Hi-Z Hi-Z
13
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 30)
tRC tRAS VIH RAS VIL tCRP VIH VIL tRAD tASR A0~A9 VIH VIL tRAH tASC tCAH
COLUMN ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
CAS
tASR
ROW ADDRESS
ROW ADDRESS
tRCS tRAL VIH W VIL tDZC DQ1~DQ8 (INPUTS) VIH VIL tCAC tAA tCLZ
Hi-Z DATA VALID Hi-Z
tRRH
tCDD
tOFF
Hi-Z
VOH DQ1~DQ8 (OUTPUTS) VOL
tRAC tDZO VIH OE VIL
tOEA tORH
tOEZ tODD
Note 30: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle described above.
14
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS VIH RAS VIL tCSH tCRP VIH VIL tRAD tASR A0~A9 VIH VIL tRAH tASC tCAH tASC tCAH tCPRH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH
tCAS
tRP
CAS
tASR
ROW ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
COLUMN ADDRESS3
ROW ADDRESS
tRAL tRCS VIH W VIL tDZC DQ1~DQ8 (INPUTS) VIH VIL
Hi-Z
tRCH
tRCS
tRCH
tRCS
tRCH tRRH
tDZC
tDZC
tCDD
Hi-Z
Hi-Z
tCAC tAA tCLZ
Hi-Z
tCAC tOFF tAA tCLZ
Hi-Z
tOFF
DATA VALID-2
tCAC tAA tCLZ
Hi-Z
tOFF
DATA VALID-3
VOH DQ1~DQ8 (OUTPUTS) VOL
tRAC tDZO tOEA
DATA VALID-1
tCPA tOCH tOEZ tOEA
tCPA tOEZ tOEA tOCH
tOEZ
tOCH
VIH OE VIL tDZO tODD tODD tDZO tORH tODD
15
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS VIH RAS VIL tCRP tRCD VIH VIL tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC tCAH tCSH tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
CAS
tASR
A0~A9
ROW ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
COLUMN ADDRESS3
ROW ADDRESS
tWCS VIH W VIL tDS DQ1~DQ8 (INPUTS) VIH VIL
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
tDS
tDH
tDS
tDH
DATA VALID-1
DATA VALID-2
DATA VALID-3
VOH DQ1~DQ8 (OUTPUTS) VOL
Hi-Z
VIH OE VIL
16
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS VIH RAS VIL tCRP VIH VIL tRWL tASR A0~A9 VIH VIL tRAH tASC tCAH
COLUMN ADDRESS1
tRP
tCSH tRCD tCAS tCP
tRSH tPC tCAS
CAS
tASC
tCAH
tCWL
tASR
ROW ADDRESS
ROW ADDRESS
COLUMN ADDRESS2
tRCS VIH W VIL tWCH tDZC DQ1~DQ8 (INPUTS) VIH VIL
Hi-Z
tCWL tWP
tRCS tWP
tWCH tDH
DATA VALID-1
tDS
tDZC tDS
Hi-Z
tDH
DATA VALID-2
tCLZ VOH DQ1~DQ8 (OUTPUTS) VOL
Hi-Z Hi-Z
tCLZ
Hi-Z
tOEZ tDZO VIH OE VIL tODD tDZO
tOEZ tODD tOEH
17
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Fast Page Mode Read-Write, Read-Modify-Write Cycle
tRAS VIH RAS VIL tCSH tCRP CAS VIH VIL tASR VIH VIL tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP tPRWC tCAS
tRP
tRWL
tASR
ROW ADDRESS
A0~A9
ROW ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
tAWD tRCS VIH W VIL tRWD tDZC DQ1~DQ8 (INPUTS) VIH VIL
Hi-Z
tCWD
tCWL tWP
tAWD tRCS tCWD tWP
tWCH tCPWD tDS tCAC tAA tCLZ tDH
DATA VALID-1
tWCH tDH
DATA VALID-2
tDZC
Hi-Z
tDS
tCAC tAA tCLZ
DATA VALID-1
VOH DQ1~DQ8 (OUTPUTS) VOL
Hi-Z
Hi-Z
DATA VALID-2
Hi-Z
tRAC tDZO VIH OE VIL tOEA
tODD tOEZ tDZO
tCPA tOEA
tODD tOEZ tOEH
18
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Self Refresh Cycle * (Note 28)
tRP VIH RAS VIL tRPC CAS VIH VIL tCPN VIH VIL tRCH VIH W VIL tCDD DQ1~DQ8 (INPUTS) VIH VIL tOFF VOH DQ1~DQ8 (OUTPUTS) VOL tOEZ tODD VIH OE VIL
Hi-Z
tRASS
tRPS
tRPC tCSR tCHS tCRP
tASR
COLUMN ROW ADDRESS ADDRESS
A0~A9
tRCS
Hi-Z
19
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Note 28:Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width(tRASS) of RAS signal during self refresh period.
1. Distributed refresh during Read/Write operation (A) Timing diagram
Read/Write Cycle Self Refresh Cycle Read/Write Cycle
tNSD RAS
last refresh cycle
tRASS100s
tSND
first refresh cycle
Table 2
Read/Write Cycle CBR distributed refresh RAS only distributed refresh Read/Write Self Refresh tNSD125s tNSD16s Self Refresh Read/Write tSND125s tSND16s
(B) Definition of distributed refresh tREF tREF/1024 tREF/1024
RAS
refresh cycle read/write cycles refresh cycle refresh cycle read/write cycles
Definition of CBR distributed refresh (Including extended refresh) The CBR distributed refresh performs more than 1024 constant period (125s max.) CBR cycles within 128ms. Definition of RAS only distributed refresh All combinations of nine row address signals (A0~A9) are selected during 1024 constant period (16s max.) RAS only refresh cycles within 16.4ms.
Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within tSND (shown in table 2)
1.2 RAS only distributed refresh Note: Hidden refresh may be used instead of CBR refresh. RAS/CAS refresh may be used instead of RAS only refresh. 1.1 CBR distributed refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSD (shown in table 2). 20
M5M44800CJ,TP-5,-5S:Under development
Switching from read/write operation to self refresh operation. The time interval tNSD from the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16s. Switching from self refresh operation to read/write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16s.
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
2. Burst refresh during Read/Write operation (A) Timing diagram
Read/Write Self Refresh Read/Write
tNSB
tRASS100s
tSNB
RAS
first refresh cycles refresh cycles 1023 cycles refresh cycles 1023 cycles last refresh cycles
Table 3
Read/Write Cycle CBR burst refresh RAS only burst refresh Read/Write Self Refresh tNSB16.4ms Self Refresh Read/Write tSNB16.4ms
tNSB+tSNB16.4ms
(B) Definition of burst refresh
16.4ms
RAS
refresh cycles 1024 cycles read/write cycles
Definition of CBR burst refresh The CBR burst refresh performs more than 1024 continuous CBR cycles within 16.4ms. Definition of RAS only burst refresh All combination of nine row address signals (A0~A9) are selected during 1024 continuous RAS only refresh cycles within 16.4ms. 2.1 CBR burst refresh Switching from read/write operation to self refresh operation. The time interval tNSB from the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16.4ms. Switching from self refresh operation to read/write operation. The time interval tSNB from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period should be set within 16.4ms. 21
M5M44800CJ,TP-5,-5S:Under development
2.2 RAS only burst refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB (shown in table 3). Switching from self refresh operation to read / write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within tSNB (shown in table 3).

▲Up To Search▲

Price & Availability of M5M44800CJ

	To Download M5M44800CJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .