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MC14001B Series B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired.
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14 PDIP-14 P SUFFIX CASE 646 MC140XXBCP AWLYYWW 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 TSSOP-14 DT SUFFIX CASE 948G 1 14 SOEIAJ-14 F SUFFIX CASE 965 1 XX = Specific Device Code A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week MC140XXB AWLYWW 14 0XXB ALYW 140XXB AWLYWW
* Supply Voltage Range = 3.0 Vdc to 18 Vdc * All Outputs Buffered * Capable of Driving Two Low-power TTL Loads or One Low-power * *
Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B Pin-for-Pin Replacements for Corresponding CD4000 Series B Suffix Devices
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 260 Unit V V mA mW C C C
DEVICE INFORMATION
Device MC14001B MC14011B MC14023B MC14025B MC14071B MC14073B MC14081B MC14082B Description Quad 2-Input NOR Gate Quad 2-Input NAND Gate Triple 3-Input NAND Gate Triple 3-Input NOR Gate Quad 2-Input OR Gate Triple 3-Input AND Gate Quad 2-Input AND Gate Dual 4-Input AND Gate
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 1
Publication Order Number: MC14001B/D
MC14001B Series
LOGIC DIAGRAMS
NOR MC14001B Quad 2-Input NOR Gate
1 2
NAND MC14011B Quad 2-Input NAND Gate
1 2 5 6 8 9 12 13
OR MC14071B Quad 2-Input OR Gate
1 2 5 6 8 9 12 13
AND MC14081B Quad 2-Input AND Gate
1 2 5 6 8 9 12 13
3
3
3
3
2 INPUT
5 6 8 9 12 13
4
4
4
4
10
10
10
10
11
11
11
11
MC14025B Triple 3-Input NOR Gate
1 2 8 3 4 5 11 12 13 9
MC14023B Triple 3-Input NAND Gate
1 2 8 3 4 5 11 12 13 9
MC14073B Triple 3-Input AND Gate
1 2 8 3 4 5 11 12 13 9
MC14082B Dual 4-Input AND Gate
2 3 4 5 9 10 11 12
1
3 INPUT
6
6
6
13 NC = 6, 8
10
10
10
VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001B Quad 2-Input NOR Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14011B Quad 2-Input NAND Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14023B Triple 3-Input NAND Gate
IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A
MC14025B Triple 3-Input NOR Gate
IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A
MC14071B Quad 2-Input OR Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14073B Triple 3-Input AND Gate
IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A
MC14081B Quad 2-Input AND Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14082B Dual 4-Input AND Gate
OUTA IN 1A IN 2A IN 3A IN 4A NC VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUTB IN 4B IN 3B IN 2B IN 1B NC
NC = NO CONNECTION
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I II II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III I I I I I I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I I I I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF:
where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Gate, CL = 50 pF)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Voltage Vin = VDD or 0
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)
Vin = 0 or VDD
Characteristic
IT(CL) = IT(50 pF) + (CL - 50) Vfk
"1" Level
"1" Level
"0" Level
Source
Sink
Symbol
VOH
VOL
IOH
VIH
IDD
Cin
IOL
VIL
Iin
IT
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
--
MC14001B Series
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- 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 IT = (0.3 A/kHz) f + IDD/N IT = (0.6 A/kHz) f + IDD/N IT = (0.9 A/kHz) f + IDD/N Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 0.00001 Typ (3.) 0.0005 0.0010 0.0015 - 4.2 - 0.88 - 2.25 - 8.8 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 7.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 Max 7.5 15 30 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF
3
MC14001B Series
B-SERIES GATE SWITCHING TIMES
III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Characteristic Symbol tTLH VDD Vdc Min -- -- -- -- -- -- Typ (7.) 100 50 40 100 50 40 Max 200 100 80 200 100 80 Unit ns Output Rise Time, All B-Series Gates tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/PF) CL + 20 ns Output Fall Time, All B-Series Gates tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns 5.0 10 15 5.0 10 15 tTHL ns Propagation Delay Time MC14001B, MC14011B only tPLH, tPHL = (0.90 ns/pF) CL + 80 ns tPLH, tPHL = (0.36 ns/pF) CL + 32 ns tPLH, tPHL = (0.26 ns/pF) CL + 27 ns All Other 2, 3, and 4 Input Gates tPLH, tPHL = (0.90 ns/pF) CL + 115 ns tPLH, tPHL = (0.36 ns/pF) CL + 47 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 8-Input Gates (MC14068B, MC14078B) tPLH, tPHL = (0.90 ns/pF) CL + 155 ns tPLH, tPHL = (0.36 ns/pF) CL + 62 ns tPLH, tPHL = (0.26 ns/pF) CL + 47 ns tPLH, tPHL ns 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- 125 50 40 160 65 50 200 80 60 250 100 80 300 130 100 350 150 110 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 14 INPUT OUTPUT * CL VDD 20 ns INPUT tPHL OUTPUT INVERTING 90% 50% 10% tTHL tPLH 90% 50% 10% tTLH tPHL 90% 50% 10% tPLH VOH VOL VOH VOL 20 ns VDD 0V PULSE GENERATOR 7 VSS *All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. OUTPUT NON-INVERTING tTLH tTHL
SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
Figure 1. Switching Time Test Circuit and Waveforms
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MC14001B Series
CIRCUIT SCHEMATIC NOR, OR GATES
MC14001B, MC14071B One of Four Gates Shown
VDD 1, 6, 8, 13 * 2, 5, 9, 12 14 VDD
MC14025B One of Three Gates Shown
VDD 1, 3, 11 2, 4, 12 14 3, 4, 10, 11 * VSS VDD
VSS *Inverter omitted in MC14001B
7
VSS VDD
9, 6, 10
8, 5, 13 7 VSS VSS
*Inverter omitted in MC14025B
CIRCUIT SCHEMATIC NAND, AND GATES
MC14023B, MC14073B One of Three Gates Shown
VDD *
MC14011B, MC14081B One of Four Gates Shown
14 VDD
3, 4, 10, 11 2, 4, 12 1, 3, 11 14 VDD 2, 5, 9, 12 1, 6, 8, 13 VSS VDD 9, 6, 10 8, 5, 13 7 VSS *Inverter omitted in MC14023B VSS * 7 VSS *Inverter omitted in MC14011B
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MC14001B Series
TYPICAL B-SERIES GATE CHARACTERISTICS
N-CHANNEL DRAIN CURRENT (SINK)
5.0 - 10 - 9.0 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 4.0 TA = - 55C - 40C + 85C + 25C 2.0 1.0 + 125C - 8.0 - 7.0 - 6.0 - 5.0 - 4.0 - 3.0 - 2.0 - 1.0 0 0 1.0 2.0 3.0 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 5.0 0 0 - 1.0 - 2.0 - 3.0 - 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) - 5.0 + 85C - 40C + 25C TA = - 55C
P-CHANNEL DRAIN CURRENT (SOURCE)
3.0
+ 125C
Figure 2. VGS = 5.0 Vdc
20 18 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 16 14 12 10 8.0 6.0 4.0 2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 9.0 10 TA = - 55C - 40C + 25C + 85C + 125C - 50 - 45 - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5.0 0 0
Figure 3. VGS = - 5.0 Vdc
TA = - 55C - 40C + 25C + 85C + 125C
- 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 4. VGS = 10 Vdc
50 45 40 ID , DRAIN CURRENT (mA) 35 30 25 20 15 10 5.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 18 20 + 125C TA = - 55C - 40C + 25C + 85C ID , DRAIN CURRENT (mA) - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 0
Figure 5. VGS = - 10 Vdc
TA = - 55C - 40C + 25C + 85C + 125C
- 2.0 - 4.0 - 6.0 - 8.0 - 10 - 12 - 14 - 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
- 18 - 20
Figure 6. VGS = 15 Vdc
Figure 7. VGS = - 15 Vdc
These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is 10 mA per pin.
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MC14001B Series
TYPICAL B-SERIES GATE CHARACTERISTICS (cont'd)
VOLTAGE TRANSFER CHARACTERISTICS
V out , OUTPUT VOLTAGE (Vdc)
5.0 4.0 3.0 2.0 1.0 0 0 1.0 2.0
SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR
V out , OUTPUT VOLTAGE (Vdc)
10 8.0 6.0 4.0 2.0 0 0 2.0 4.0
SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND
SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND
3.0 4.0 5.0 Vin, INPUT VOLTAGE (Vdc)
6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc)
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
16 V out , OUTPUT VOLTAGE (Vdc) 14 12 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range from an ideal "1" or "0" input level which does not produce output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a fixed voltage VO are given in the Electrical Characteristics table. VIL and VIH are presented graphically in Figure 11. Guaranteed minimum noise margins for both the "1" and "0" levels =
1.0 V with a 5.0 V supply 2.0 V with a 10.0 V supply 2.5 V with a 15.0 V supply
Figure 10. VDD = 15 Vdc
Vout VO
VDD
Vout VO
VDD
VO VDD 0 VIL VIH Vin
VO VDD 0 VIL VSS = 0 VOLTS DC VIH Vin
(a) Inverting Function
(b) Non-Inverting Function
Figure 11. DC Noise Immunity
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MC14001B Series
PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M
14 8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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MC14001B Series
PACKAGE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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CCC EE CCC EE
SECTION N-N -W-
MC14001B Series
PACKAGE DIMENSIONS
F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965-01 ISSUE O
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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10
MC14001B Series
ORDERING & SHIPPING INFORMATION:
Device MC14001BCP MC14001BD MC14001BDR2 MC14001BDT MC14001BDTR2 Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 TSSOP-14 Shipping 2000 Units per Box 2750 Units per Box 2500 Units / Tape & Reel 96 Units per Rail 96 Units per Rail
ORDERING & SHIPPING INFORMATION:
Device MC14071BCP MC14071BD MC14071BDR2 MC14071BDT MC14071BDTR2 Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 TSSOP-14 Shipping 2000 Units per Box 55 Units per Rail 2500 Units / Tape & Reel 96 Units per Rail 96 Units per Rail
MC14011BCP MC14011BD MC14011BDR2 MC14011BDT MC14011BDTEL MC14011BDTR2
PDIP-14 SOIC-14 SOIC-14 TSSOP-14 TSSOP-14 TSSOP-14
2000 Units per Box 2750 Units per Box 2500 Units / Tape & Reel 96 Units per Rail 2000 Units / Tape & Reel 50 Units per Rail
MC14073BCP MC14073BD MC14073BDR2
PDIP-14 SOIC-14 SOIC-14
2000 Units per Box 55 Units per Rail 2500 Units / Tape & Reel
MC14081BCP MC14081BD MC14081BDR2
PDIP-14 SOIC-14 SOIC-14 TSSOP-14 TSSOP-14
2000 Units per Box 55 Units per Rail 2500 Units / Tape & Reel 96 Units per Rail 2500 Units / Tape & Reel
MC14023BCP MC14023BD MC14023BDR2
PDIP-14 SOIC-14 SOIC-14
2000 Units per Box 2750 Units per Box 2500 Units / Tape & Reel
MC14081BDT MC14081BDTR2
MC14082BCP MC14025BCP MC14025BD MC14025BDR2 PDIP-14 SOIC-14 SOIC-14 2000 Units per Box 2750 Units per Box 2500 Units / Tape & Reel MC14082BD MC14082BDR2
PDIP-14 SOIC-14 SOIC-14
2000 Units per Box 55 Units per Rail 2500 Units / Tape & Reel
For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
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11
MC14001B Series
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local Sales Representative.
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12
MC14001B/D

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