 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| OKI Semiconductor MSM5416258B DESCRIPTION Technical Information 262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO The MSM5416258B is a 262,144-word x 16-bit dynamic RAM fabricated in OKI's CMOS silicon gate technology. The MSM5416258B achieves high integration,high-speed operation,and low-power consumption due to quadruple polysilicon double metal CMOS. The MSM5416258B is available in a 40-pin plastic SOJ. FEATURES * 262,144-word by 16-bit configuration * Single 5V power supply, 10% tolerance * Input :TTL compatible * Output :TTL compatible, 3-state * Refresh : 512 cycles/8ms * Fast page mode with EDO,read modify write capability * Byte wide control: 2 CAS control * CAS before RAS refresh, Hidden refresh, RAS only refresh capability * Package : 40-Pin 400 mil plastic SOJ (SOJ40-P-400) (Product : MSM5416258B-xxJS) xx : indicates speed rank. PRODUCT FAMILY Access Time (Max.) Family MSM5416258B-28 MSM5416258B-30 MSM5416258B-35 Cycle Time (Min.) tRAC 28ns 30ns 35ns tAA 15ns 16ns 19ns tCAC tOEA 9ns 9ns 10ns 9ns 9ns 10ns tRC 48ns 55ns 60ns tHPC 12ns 13ns 13ns Power Dissipation 1485mW 1458mW 1430mW PIN CONFIGURATION ( TOP VIEW ) Vcc DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss Pin Names A0-A8 RAS LCAS,UCAS DQ0-15 WE OE Vcc Vss NC Function Address Input Row Address Strobe Column Address Strobe Data-Input/ Data-Output Write Enable Output Enable Power Supply ( +5V ) Ground ( 0V ) No Connection Note1 : The same power supply voltage must be provided to every Vcc pin, and the same GND voltage level must beprovideded to every Vss pin. 40Pin 400mil SOJ REVISION-2 1997.11.10, specification are subject to change without advanced notice. BLOCK DIAGRAM OE RAS LCAS UCAS Timing Generater WE I/O Controller I/O Controller 8 Output Buffers Input Buffers 8 DQ0~DQ7 Column Address Buffer Internal Address Counter Row Address 9 Buffer Refresh Control Clock 8 9 8 9 Column Decoders Sence amplifier 16 A0~A8 I/O 16 Selector 9 Row Decoders Word Drivers Memory cells 8 Input Buffers Output Buffers 8 DQ8~DQ15 8 8 Vcc On Chip VBB Generater Vss FUNCTION TABLE Input Pin RAS H L L L L L L L L LCAS * H L H L L H L L UCAS * H H L L H L L L WE * * H H H L L L H OE * * L L L H H H H High-Z High-Z DOUT High-Z DOUT DIN Dont Care DIN High-Z DQPin DQ0~DQ7 DQ8~DQ15 High-Z High-Z High-Z DOUT DOUT Dont Care DIN DIN High-Z Functinal Mode Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write - ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Rating Voltage on any pin relative to Vss Short circuit output current Power dissipation Operrating temperrature Storage temperature Symbol Vt Ios PD Topr Tstg Conditions Ta=25C Ta=25C Ta=25C Value -1.0 ~ +7.0 50 1.5 0 ~ +70 -55 ~ +150 Unit V mA W C C Recommended Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Conditions Min. 4.5 0 2.4 -1.0 Typ. 5.0 0 (Ta=0Cto 70C) Max. 5.5 0 6.5 0.8 Unit V V V V Capacitance Parameter Input capacitance (A0~A8) Input capacitance (RAS,LCAS,UCAS,WE,OE) Input / output capacitance (DQ0~DQ15) Symbol CIN1 CIN2 CI/0 (Vcc=5V10%,Ta=25C,f=1MHz) Conditions Typ. Max. 8 8 9 Unit pf pf pf DC CHARACTERISTICS (Vcc=5V10%, Ta=0 to 70C) Parameter Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS only Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (CAS Before RAS Refresh) Symbol VOH VOL ILI ILO Condition IOH= - 1.0mA IOL= 2.0mA 0VVINVcc DQi Disable 0VVo5.5V RAS,CAS Cycling MSM5416258B MSM5416258B MSM5416258B -28 -30 -35 Min. Max. Min. Max. Min. Max. 2.4 0 -10 -10 Vcc 0.4 10 10 2.4 0 -10 -10 Vcc 0.4 10 10 2.4 0 -10 -10 Vcc 0.4 10 10 Unit V V A A Note ICC1 tRC=Min. RAS,CAS = VIH RAS=Cycling CAS=VIH - 270 - 265 - 260 mA 1,2 ICC2 - 3 - 3 - 3 mA 1 ICC3 - 270 - 265 - 260 mA 1,2 tRC=Min. ICC4 RAS=VIL CASCycling 270 265 260 mA 1,3 tHPC=Min. ICC5 RAS=Cycling CAS Befor RAS 270 265 260 mA 1,2 Notes : 1. Icc Max. is specified as Icc for the output open cindition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. AC CHARACTERISTICS Parameter Random read or write cycle time Read/Write cycle time Hyper page mode cycle time (1/2) (Vcc =5V10%, Ta =0~70C) MSM5416258B MSM5416258B -28 -30 Symbol MIN MAX MIN MAX tRC 48 55 tRMW tHPC tPRMW tRAC tCAC tAA tOEA tCPA tCOH tOFF tOEZ tREZ tWEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWEP 17 28 28 7 7 4 5 22 5 10 8 0 6 0 5 21 15 0 0 0 10 19 13 10,000 10,000 100,000 MSM5416258B -35 MIN MAX 60 85 13 45 Unit ns ns ns ns Note 70 12 34 28 9 15 9 17 3 3 3 3 3 2 7 7 7 7 35 8 75 13 35 30 9 16 9 18 3 3 3 3 3 2 18 30 30 7 7 4 5 25 5 11 8 0 6 0 5 22 18 0 0 0 10 22 15 10,000 10,000 100,000 Fast page mode read/write cycle time Access time from RAS Access time from CAS Access time from column address Access time from OE Access time from CAS precharge Data hold after CAS low Output buffer turn-off delay time OE to data output buffer turn-off delay time RAS to data output buffer turn-off delay time WE to data output buffer turn-off delay time Transition time Refresh preiod RAS precharge time RAS pulse width RAS pulse width (Fast page mode) RAS hold time RAS hold time reference to OE CAS precharge time CAS pulse width CAS hold time CAS to RAS precharge time RAS to CAS delay time RAS to column address delay time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address hold time from RAS Column address to RAS lead time Read command set-up time Read command hold time Read command hold time reference to RAS WE pulse width 35 10 19 10 21 3 3 3 3 3 2 20 35 35 8 8 4 5 30 5 13 10 0 7 0 5 25 20 0 0 0 10 26 16 10,000 10,000 100,000 ns ns ns ns ns ns ns ns 7,12,13 7,12 7,13 7,12 17 8 8 8 8 8 8 35 8 8 8 8 8 35 8 ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 12 13 9 9 AC CHARACTERISTICS Parameter Write command set-up time Write command hold time Write command pulse width (2/2) (Vcc=5V10%, Ta=0~70C) MSM5416258B MSM5416258B MSM5416258B -35 -28 -30 Unit Symbol MIN MAX MIN MAX MIN MAX ns tWCS 0 0 0 ns tWCH 5 5 6 tWP tWCR tOEH tCWL tRWL tDZC tDZO tDS tDH tDHR tOED tOCH tCHO tOEP tCWD tAWD tRWD tRPC tCSR tCHR 5 21 5 5 7 0 0 0 5 21 7 5 5 5 18 24 37 0 5 6 5 22 5 5 7 0 0 0 5 22 7 5 5 6 18 27 40 0 6 6 6 26 6 6 8 0 0 0 6 26 8 8 8 8 20 30 45 0 8 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 11 10 10 Note Write command hold time from RAS OE command hold time Write command to CAS lead time Write command to RAS lead time Data to CAS delay time Data to OE delay time Data-in set-up time Data-in hold time Data-in hold time referenced to RAS OE to Data-in delay time OE "L" to CAS "H" lead time CAS "H" to OE "L" lead time Hi-Z command pulse width CAS to WE delay time Column address to WE delay time RAS to WE delay time CAS active delay time from RAS precharge RAS to CAS set-up time (CAS before RAS) RAS to CAS hold time (CAS before RAS) Notes: 1. All voltages are referenced to Vss. 2. This parameter is dependent upon the cycle rate. 3. This parameter is dependent upon the output loading. Specified values are obtained with the output open. 4. An initial pause of 200s is required after power-up, followed by any 8RAS cycles. (Example: RAS-only-refresh) before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8CAS before RAS cycles instead of 8RAS cycles are required. 5. The AC characteristics assume tT=5ns. 6. VIH (Min.)and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 7. Data outputs are measured with a load of 30 pF. DOUT reference levels: V OH/VOL=1.8V/1.4V. 8. tREZ (Max.), tOFF (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the outputs achieve the open circuit condition and are not referebced to output voltage levels. This parameter is sampled and not 100 % tested. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to CAS leadind edge of early write cycles and to WE leading edge in OE-controlled write cycles and read-modify-write cycles. 11. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCStWCS (Min.), the cycle is an early write cycle and the data out pins will remain open circuit throughout the entire cycle. If tRWDtRWD (Min.), tCWDtCWD (Min.) and tAWDtAWD (Min.), the cycle is a read-modifywrite cycle and the data out will contain data read from the selected cell. If neither or the above sets of conditions is satisfied, the condition of the data out is indetermunate. 12. Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCDC. 13. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 14. Input levels at the AC testing are 3.0V/0V. 15. Addresses (A0 - A8) may be changed two times or less while RAS =V IL. 16. Addresses (A0 - A8) may be changed once or less while CAS =V IH and RAS =VIL. 17. This is guaranteed by design. ( tCOH=tCAC - output transition time). This parameter is not 100 % tested. 18. This parameter is dependent upon the number of address transitions. Specified values are measured with a maximum of two transitions per address cycle in Fast Page Mode. READ CYCLE (RAS output control ) tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS UCAS LCAS tAR tRAD tASR tRAH tASC ROW tRAL tCAH A0-8 COLUMN tRCS tRCH tRRH tROH tOEA tOEZ WE OE tCAC tAA tOFF VALID DATA tOFF HZ tRAC DQ0-7 DQ8-15 HZ VALID DATA : "H" or "L" READ CYCLE (CAS output control ) tRC tRAS tRP RAS tCSH tCRP tRCD tAR tRAD tASR tRAH tASC tCAH tRSH tCAS UCAS LCAS tRAL A0-A8 ROW COLUMN tRCS tRRH WE tROH tOEA tOEZ OE tCAC tOFF tAA HZ tRAC DQ0-7 VALID DATA DQ8-15 HZ VALID DATA : "H" or "L" EARLY WRITE CYCLE (LCAS and UCAS active) tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS LCAS UCAS tASR tAR tRAD tRAH tASC tCAH tRAL A0-8 ROW COLUMN tCWL tRWL tWP WE tWCR tWCS tWCH OE tDHR tDS tDH DQ0-7 VALID DATA tDS tDH DQ8-15 VALID DATA : "H" or "L" LATE WRITE CYCLE (LCAS and UCAS active) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS LCAS UCAS tASR tRCD tAR tRAD tRAH tASC tCAH tRAL A0-8 ROW tRCS COLUMN tCWL tRWL tWP WE tWCR tOEH OE tDS tDH DQ0-7 VALID DATA tDS tDH DQ8-15 VALID DATA : "H" or "L" READ MODIFY WRITE CYCLE (LCAS and UCAS active) tRMW tRAS tRP RAS tCSH tCRP tRCD tAR tRAD tASR tRAH tASC tCAH tRSH tCAS LCAS UCAS tRAL A0-8 ROW COLUMN tAWD tRCS tCWL tRWL tWP WE tRWD tCWD tDZO tOEA tOEZ tOEH O E tCAC tOED tDS tDH DQ07 tRAC tDZC OUT IN tDS tDH IN DQ8-15 OUT : "H" or "L" FAST PAGE MODE READ CYCLE with Extended Data Out tRC tRASP tRP RAS tCRP tCSH tCAS tPC tCAS tRSH tCAS LCAS UCAS tRCD tCP tCP tAR tRAD tASR tRAH tASC tCAH tASC tCAH tASC tRAL tCAH COLUMN tRCH tRRH A0-8 ROW tRCS COLUMN COLUMN WE tOEA OE tCAC tAA tCAC tCOH VALID DATA tCPA tRAC tAA VALID DATA tCAC tCOH VALID DATA tCPA tAA VALID DATA VALID DATA tOEZ tREZ VALID DATA tOEZ tREZ DQ0-7 HZ DQ8-15 HZ : "H" or "L" FAST PAGE MODE READ Hi-Z OPERATION tRC tRASP tRP RAS tCRP tAR tCSH tRCD tCAS tRAD tASR tRAH tASC tCAH tASC tCAH tASC tCAH tASC tCAH tCP tCAS tHPC tCP tCAS tCP tCAS tRAL tRSH tCRP LCAS UCAS A0-8 ROW COLUMN tRCS COLUMN COLUMN tRCH COLUMN tRRH tRCS tRCH WE tRAC tOEA tCAC tAA tCAC tAA tCPA tDOH tOEZ VALID DATA tCHO tOEP tCAC tAA tOEA tOEZ tOEA VALID DATA tWEZ VALID DATA tCAC tAA tREZ tOEP tOCH tWEP OE DQ0-7 VALID DATA VALID DATA DQ8-15 VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA : "H" or "L" FAST PAGE MODE EARLY WRITE CYCLE tRC tRASP tRP RAS tCRP tCSH tRCD tCAS tCP tPC tCAS tCP LCAS UCAS tRSH tCAS tAR tRAD tASR tRAH tASC ROW tCAH tASC tCAH tASC tRAL tCAH A0-8 COLUMN tCWL tWCS tWCH tWP COLUMN tCWL tWCS tWCH tWP COLUMN tCWL tWCS tWCH tWP WE OE tDS tDH tDS tDH Input Data tDS tDH Input Data DQ0-7 DQ8-1 5 Input Data tDS tDH Input Data tDS tDH Input Data tDS tDH Input Data : "H" or "L" FAST PAGE MODE READ MODIFY WRITE CYCLE tRC tRASP tRP RAS tCRP tRCD tCAS tCP tPRMW tCAS tCP tRSH tCAS LCAS UCAS tAR tRAD tASR tRAH tASC ROW @ tCAH tASC tCAH COLUMN tASC tRAL tCAH COLUMN tCWL tAWD tCWD tWP tOEA tOEZ A0-8 COLUMN tCWL tAWD tCWD tWP tOEA tOEZ tCWL tAWD tCWD tWP tOEA tOEZ WE tRCS OE tCAC tAA tDS tCAC tAA IN tDH tDH tDS tCAC tDH tAA tDS OUT IN DQ0-7 OUT OUT IN tCAC tAA tDS tDH tCAC tAA tDS tDH tCAC tAA tDS tDH DQ8-15 OUT IN OUT IN OUT IN : "H" or "L" CAS BEFORE RAS REFRESH CYCLE tRP tRC tRAS tRP RAS tRPC tCSR tCHR tRPC INHIBIT FALLING TRANSITION LCAS UCAS A0-8 WE OE tOFF DQ0-7 tOFF HZ DQ8-15 HZ : "H" or "L" HIDDEN REFRESH CYCLE tRC tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR LCAS UCAS tAR tRAD tRAL tASR tRAH tASC tCAH ROW COLUMN tRCS tRRH tROH tOEA tOEZ A0-8 WE OE tRAC tCAC tAA VALID DATA tCAC tAA VALID DATA tOFF tOFF DQ0-7 HZ tRAC DQ8-15 HZ : "H" or "L" RAS ONLY REFRESH CYCLE tRC tRAS tRP RAS tCRP tRPC LCAS UCAS tASR tRAH ROW A0-8 WE OE HZ HZ DQ0-7 DQ8-15 : "H" or "L" PACKAGE OUTLINES AND DIMENSIONS (Unit: mm) SOJ40-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) SOJ42-P-400-1.27 Epoxy resin 42 alloy Solder plating 5mm or more 1.70 TYP. Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5mm or more 1.86 TYP. 20/20 |
Price & Availability of MSM5416258B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |