![]() |
|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI49FCT3805D 3.3V, 2 x 1:5 CMOS Clock Driver Features Low output skew: <270ps Switching frequency of 133 MHz Fast output rise/fall time: <1.5ns Low propagation delay: <3.0ns Low input capacitance: <6.0pF Balanced CMOS outputs Industrial Temperature: 40C to +85C 3.3V 10% operation Packages available: 20-pin 300-mil wide SOIC (S) 20-pin 150-mil wide QSOP (Q) 20-pin 209-mil wide SSOP (H) Description Pericom Semiconductors PI49FCT series of logic circuits are produced using the Companys advanced submicron CMOS technology to achieve fast speed, low skew, fast slew rate, and low propagation delay for most computing and communication applications. The PI49FCT3805D is composed of non-inverting drivers. The outputs are configured into 2 groups of one-in, five-out with independent output enable. Group B has an extra MON output. Excellent output signals to power and ground ratio minimize power and ground noise and also improves output performance. Logic Block Diagram OEA 5 INA OA0-4 Pin Configuration VCC OA0 OA1 OA2 5 1 2 3 4 20 19 18 17 VCCB OB0 OB1 OB2 GNDB OB3 OB4 MON OEB INB GNDA OB0-4 INB OEB 20-Pin 5 H,Q,S 16 15 14 13 12 11 OA3 OA4 GNDQ OEA 6 7 8 9 10 MON INA Product Pin Description Pin Name OEA, OEB INA, INB OAN, OBN MON GND VCC Description Hi-Z State Output Enable Inputs (Active LOW) Clock Inputs Clock Outputs Monitor Output Ground Power Truth Table(1) Inputs OEA, OEB INA, INB L L L H H L H H Note: 1. H = High Voltage Level L = Low Voltage Level Z = High Impedance Outputs OAN, OBN MON L L H H Z L Z H 1 PS8492 08/10/00 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI49FCT3805D 3.3V, 2 x 1:5 CMOS Clock Driver Capacitance (TA = 25C, f = 1 MHz) Parame te rs CIN COUT De s cription Input Capacitance Output Capacitance Te s t Conditions VIN =0V VOUT =0V Typ 3.0 M ax. 4 6 Units pF Note: 1. This parameter is determined by device characterization but is not production tested. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................. 65C to +150C Ambient Temperature with Power Applied ............................. 40C to +85C Supply Voltage to Ground Potential (Inputs & VCC Only) ............0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & I/O Only) .. 0.5V to +VCC +0.5V DC Input Voltage ...................................................................... 0.5V to +4.6V DC Output Current ............................................................................... 120 mA Power Dissipation .................................................................................... 0.5W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Range Ambient Temperature = -40C to +85C, VCC = 3.3V 0.3V DC Electrical Characteristics (Over the Operating Range) Symbol VO H De s cription O utput high voltage VC C = Min. VIN = VIL or VIH Output low voltage VC C = Min. VIN = VIL or VIH Input high voltage Input low voltage Input high current Input low current High impedance output current Clamp diode voltage Output HIGH(4) current O utput LO W(4) current Short circuit(5)current Te s t Conditions (1) IO H = 0.1mA IO H = 8mA IO H = 12mA IO H = 0.1mA IO H = 8mA IO H = 12mA LO W logic HIGH logic VC C = Max., VIN = VC C VC C = Max., VIN = GND VC C = Max, all outputs disabled VC C = Min., IIN = 18mA VO UT = 1.5V, VIN = VIL or VIH, VC C = 0V VO UT = 1.5V, VIN = VIL or VIH, VC C = 0V VC C = Max. VO UT = VC C VO UT = GND M in. VC C - 0.2 2.4(3) 2.4(3) 2.0 0.5 45 50 60 Typ.(2) 3.0 3.0 0.2 0.3 0.7 74 90 135 M ax. 0.2 0.4 0.4 5.5 0.8 1 1 1 1 1.2 180 200 240 mA V A V Units VO L VIH VIL IIH IIL IO ZH IO ZL VIK IO H IO L IO S Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient and maximum loading. 3. VOH = VCC 0.6V at rated current. 4. This parameter is determined by device characterization but is not production tested. 5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 2 PS8492 08/10/00 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI49FCT3805D 3.3V, 2 x 1:5 CMOS Clock Driver Power Supply Characteristics Parameters Description ICC ICC ICCD Quiescent Power Supply Current Supply Current per Inputs @ TTL HIGH Supply Current per Input per MHz(4) VCC = Max. VCC = Max. VCC = Max., Outputs Open OEA or OEB = GND Per Output Toggling 50% Duty Cycle VCC = Max., Outputs Open fO = 10 MHZ 50% Duty Cycle OEA or OEB = GND Mon. Outputs Toggling VCC = Max., Outputs Open fO = 2.5 MHZ 50% Duty Cycle OEA or OEB = GND Eleven Outputs Toggling Test Conditions(1) VIN = GND or VCC VIN = VCC - 0.6V(3) VIN = VCC VIN = GND Min. -- -- -- Typ(2) 0.1 110 0.09 Max. 30 300 0.16 Units A A mA/ MHZ IC VIN = VCC VIN = GND VIN = VCC - 0.6V VIN = GND VIN = VCC VIN = GND VIN = VCC - 0.6V VIN = GND -- 1.3 9.0(5) -- 1.3 10.0(5) mA -- 4.4 6.0 (5) -- 4.4 7.0(5) Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input (VIN = VCC - 0.6V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fONO) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = VCC - 0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 3 PS8492 08/10/00 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI49FCT3805D 3.3V, 2 x 1:5 CMOS Clock Driver Switching Characteristics over Operating Range Symbol De s cription Propagation Delay A to Bn Rise/Fall Time 0.4V to 2.4V 2.4V to 0.4V Pulse Skew Output Skew Package Skew Condition Reference Voltage = 1.5V M ax.(2) 3.0 Units Switch Position Te s t Disable LOW Enable LOW Disable HIGH Enable HIGH Switch 6V GND Open tPLH tPHL tR/tF tSK (p) tSK (o) tSK (t) CL = 15pF CL = 15pF Reference 1.5V Reference 1.5V Reference 1.5V 1.5 0.27 0.27 0.55 5.2 133 MHz ns All Other Inputs Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tZL, tZH, Enable/Disable tLZ, tHZ Time FM A X Input Frequency Note: 1. Lumped load, CL = 15pF 2. These parameters are guaranteed by design 3. Series Resistor loading = 33ohms (See Test Circuit) Tests Circuit for 133 MHz Enable/Disable Time Test Set-Up 6V VCC S VCC Pulse Generator f = 125MHz 50 33 D.U.T. CL 15pF Pulse Generator 50 D.U.T. CL 15pF 33 500 500 4 PS8492 08/10/00 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI49FCT3805D 3.3V, 2 x 1:5 CMOS Clock Driver Switching Waveforms Propagation Delay 3V Input tPLH Output tPHL VOH 1.5V VOL 1.5V 0V Output Skew tSK(o) 3V Input tPLHx Ox tSK(o) tSK(o) 1.5V 0V tPHLx VOH 1.5V VOL VOH Oy tPLHy 1.5V VOL tPHLy Enable and Disable Times Enable OE tPZL Output Normally Low Output Normally High 3.0V Switch Closed tPZH Switch Open 1.5V 0V 0V 1.5V 0.3V tPHZ 0.3V VOH Output Disable 3V 1.5V 0V tPLZ 3.0V Input tSK(o) = | tPLHy - tPLHx | or | tPHLy - tPHLx | Pulse Skew tSK(p) 3V 1.5V 0V tPLH tPHL VOH 1.5V VOL tSK(p) = | tPHL - tPLH | VOL Package Skew tSK(t) 3V Input tPLH1 Package 1 Output tSK(t) tSK(t) 1.5V 0V tPHL1 VOH 1.5V VOL VOH Package 2 Output tPLH2 1.5V VOL tPHL2 tSK(t) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | 5 PS8492 08/10/00 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI49FCT3805D 3.3V, 2 x 1:5 CMOS Clock Driver 20-Pin 300-mil wide SOIC (S) 20 .2914 .2992 7.40 7.60 .010 .029 0.254 x 45 0.737 1 .496 12.60 .511 12.99 .0091 .0125 0.41 .016 1.27 .050 .0926 .1043 2.35 2.65 SEATING PLANE .394 .419 10.00 10.65 0.23 0.32 0-8 .020 0.508 REF .030 0.762 .050 BSC 1.27 .013 .020 0.33 0.51 .0040 .0118 0.10 0.30 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 20-Pin 150-mil wide QSOP (Q) 20 .150 .157 3.81 3.99 .015 x 45 0.38 1 .337 8.56 .344 8.74 .016 .050 .053 1.35 .069 1.75 SEATING PLANE 0.41 1.27 .007 .010 0.178 0.254 .058 REF 1.47 .228 .244 5.79 6.19 .025 BSC 0.635 .004 0.101 .010 0.254 .008 0.203 .012 0.305 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 6 PS8492 08/10/00 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI49FCT3805D 3.3V, 2 x 1:5 CMOS Clock Driver 20-Pin 209-mil wide SSOP (H) 20 .197 .220 5.00 5.60 1 .272 .295 6.90 7.50 .078 2.00 Max SEATING PLANE .002 Min 0.050 .004 .009 0.09 0.25 0.55 .022 0.95 .037 .291 .322 7.40 8.20 .0256 BSC 0.65 .0098 Max. 0.25 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Orde ring Code PI49FCT3805DH PI49FCT3805DQ PI49FCT3805DS Part M arking PI49FCT3805HD PI49FCT3805Q D PI49FCT3805SD Package Type 20- pin 209 mil SSO P 20- pin 150 mil Q SO P 20- pin 300 mil SSIC Industrial Rating Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 7 PS8492 08/10/00 |
Price & Availability of PI49FCT3805D
![]() |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |