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PRELIMINARY
Z89331 CP95TEL1400
PRELIMINARY CUSTOMERPROCUREMENTSPECIFICATION
Z89331
OTPDIGITAL TELEVISIONCONTROLLER
FEATURES
n Part Number
Z89331
*General-Purpose
ROM (KB)
24
RAM* (Bytes)
640
Speed (MHz)
12
n n n
Serial Interfacing I2C Port Fully Customized Character Set Character-Control and Closed-Caption Modes Keypad User Control TV Tuner Serial Interface Direct Video Signals Low-EMI Option
n n n n
42-Pin SDIP Package n 4.75- to 5.25-Volt Operating Range n 0C to +70C Temperature Range n One-Time Programmable n
GENERAL DESCRIPTION
The Z89331 One-Time Programmable (OTP) Digital Television Controller is designed to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities. The Z89331 features a Z89C00 RISC processor core that controls on-board peripheral functions and registers using the standard processor instruction set. Character attributes can be controlled through two modes: the on-screen display Character-Control Mode and the Closed-Caption Mode. The Character-Control Mode provides access to the full set of attribute controls, allowing the modification of attributes on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Closed-caption text can be decoded directly from the composite video signal and displayed on-screen with the assistance of the processor's digital signal processing (DSP) capabilities. The fully customized 512 character set, formatted in two 256 character banks, can be displayed with a host of display attributes that include underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency. Serial interfacing with the television tuner is provided through the tuner serial port. Other serial devices, such as digital channel tunning adjustments, may be accessed through the industry-standard I2C port. User control can be monitored through the keypad port, or the 16-bit remote control capture register. functions such as color and volume can be controlled by eight 8-bit pulse width modulated scanning Receiver directly ports.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
CP95TEL1400 11/95
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PRELIMINARY
Z89331 CP95TEL1400
GENERAL DESCRIPTION (Continued)
Capture IRIN ADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Control XTAL1 XTAL2 LPF HSYNC VSYNC /Reset CPU RAM 640 x 16
Address
Port 17 Port 00 Port 05 Port 04
PWM PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 PWM10 Port1 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19
Note: Dotted pin functions not available on 42-pin device.
I2C
SCL SCD OSD V1 V2 V3 BLANK HALFBLNK
ROM Addr
Port 01/11 Port 02/12
Register Addr/Data
Z89C00 Core
Port0F
Data
ROM Data
ROM 12K x 16 16K x 16 24K x 16
Functional Block Diagram
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PRELIMINARY
Z89331 CP95TEL1400
PWM10 PWM9 PWM5 PWM4 PWM3 PWM2 PWM1 Port 03 Port 04/ADC4 Port 05/ADC3 Port 00/ADC2 Port 17/ADC1 GND Port 10/R<0> Port 06/Counter Port 18/G<0> Port 13/G<1> Port 14/B<0> Port 15/B<1> Port 16/SCLK Port 0F/HalfBlnk
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36
Port12/I2MSD Port 11/12MSC Port 02/I2SSD Port 01/I2SSC Port 09 Port 08/R<1> IRIN Port 07/CSync VCC /Reset XTAL2 XTAL1 ANGND LPF CVI/ADC0 VSync HSync VBlank V1 V2 V3
Z89331 42-Pin Shrink DIP
35 34 33 32 31 30 29 28 27 26 25 24 23 22
42-Pin Shrink DIP Pin Configuration
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PRELIMINARY
Z89331 CP95TEL1400
PIN DESCRIPTIONS Z89331
Pin Name VCC GND IRIN ADC[5:0] a PWM9 Z89331 42-Pin SDIP 34 13,30 36 -,9,10,11,12,2,8 1,2 Configuration Direction Reset PWR PWR I AI OD PWR PWR I I O
Function +5 V 0V Infrared Remote Capture Input 4-Bit Analog to Digital Converter Input b 14-Bit Pulse Width Modulator Output 8-Bit Pulse Width Modulator Output Bit Programmable Input/Output Ports Bit Programmable Input/Output Ports I2C Clock I/O I2C Data I/O I2C Clock I/O I2C Data I/O Crystal Oscillator Input Crystal Oscillator Output Loop Filter H_Sync V_Sync Device Reset OSD Video Output (Typically Drive B, G, and R Outputs) OSD Blank Output OSD Half Blank Output R[1:0],G[1:0], and B[1:0] Outputs of the RGB Matrix Internal Processor SCLK
PWM[8:1]c Port0[F:0]d
Port1[9:0] e
-,-,-,3,4 5,6,7 21,-,-,-,-,-, 38,37,35,-,-, 15,8,40,39,11 -,16,12,20, 19,18,17,42, 41,14 41 42 39 40 31 32 29 26 27 33 22,23,24 25 21 37,14,17, 16,19,18 20
OD B
OD I
B
I
MSSCLf MSSCD g SSCL h SSCD i XTAL1 XTAL2 LPF HSYNC VSYNC /RESET V[3:1] Blank Half Blankh RGB Digital Outputs i SCLKk
BOD BOD BOD BOD AI AO AB B B I O O O O O I I I AI AO AB I I I O O I I I
Notes: a) ADC1 input is shared with Port 17, ADC2 input Pin is shared with Port 00. ADC3 input pin is shared with Port 05 and ADC4 input pin is shared with Port 04. b) ADC0 and ADC5 have a clamp circuit that facilitates Composite video input. c) PWM[8,7] is not available on the 42-pin DIP version. d) Port0[F:A] is not available on the 42-pin DIP version.
e) f) g) h) i) k)
Port19 is not available on the 42-pin DIP version. SCL I/O pin is shared with Port01 or Port11. SCD I/O pin is shared with Port02 or Port12. Half Blank output is a function shared with Port0F. Digital RGB outputs and the internal SCLK are shared with Port1[5:0]. Internal processor SCLK is shared with Port16.
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PRELIMINARY
Z89331 CP95TEL1400
V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25 V
VCC = 5.25 V Output Voltage Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 Settling Time 70% of DC Level, 10pf Load Limit 3.9 V +/- 0.3 V 3.0 V +/- 0.3 V 1.8 V +/- 0.3 V 0.6 V +/- 0.3 V < 50 nsec
V1, V2, V3 ANALOG OUTPUT Specifications VCC = 4.75V
VCC = 4.75V Output Voltage Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 Settling Time 70% of DC Level, 10pf Load Limit 3.5 V +/- 0.3 V 2.6 V +/- 0.3 V 1.6 V +/- 0.3 V 0.5 V +/- 0.3 V < 50 nsec
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PRELIMINARY
Z89331 CP95TEL1400
DC CHARACTERISTICS TA = 0C to + 70C; VCC = + 4.75 V to + 5.25V
Symbol VIL VIH VHY VPU VOL Parameter Input Voltage Low Input Voltage High TA = 0 to + 70C Min Max 0 0.7 VCC 0.2 VCC VCC 13.2 0.4 0.4 0.4 -80 3.0 3.0 Typical @ 25C 1.48 3.0 0.8 0.16 0.19 0.19 4.75 -46 0.01 0.02 Units V V V V V V V V A A A [2] IOL = 1.00 mA IOL = mA, [1] IOL =0.75 mA, [2] IOH = -0.75 mA VRL = 0 V 0 V, VCC 0 V, VCC Conditions
Schmitt Hysteresis 0.1 V CC Maximum Pull-Up Voltage Output Voltage Low
VOH IIR IIL IOL
Output Voltage High Reset Input Current Input Leakage Tri-State Leakage
V CC -0.4 -3.0 -3.0
Note: [1] Port 0, 1 [2] PWM Open-Drain
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PRELIMINARY
Z89331 CP95TEL1400
Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-con-
formance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues.
(c) 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
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