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 PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
1
Z89332
DIGITAL TELEVISION CONTROLLER
FEATURES
Device Z89332 ROM (KW) 24 RAM* (Words) 640 PWM (8-Bit) 8 Voltage Range 4.5 to 5.5V
s s s s s s
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Fully Customized Character Set Character-Control and Closed-Caption Modes Keypad User Control TV Tuner Serial Interface Direct Video Signals Speed: 12 MHz
Note: *General-Purpose s
42-Pin SDIP and 48-Pin Ceramic Packages with 42- to 48-Pin Adapter Socket 0C to +70C Temperature Range
s
GENERAL DESCRIPTION
The Z89332 Digital Television Controller is designed to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities. The television controller features a Z89C00 RISC processor core that controls the on-board peripheral functions and registers using the standard processor instruction set. Character attributes can be controlled through two modes: the on-screen display Character-Control Mode and the Closed-Caption Mode. The Character-Control Mode provides access to the full set of attribute controls, allowing the modification of attributes on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Closed-caption text can be decoded directly from the composite video signal and displayed on-screen with the assistance of the processor's digital signal processing (DSP) capabilities. The fully customized 512 character set, formatted in two 256 character banks, can be displayed with a host of display attributes that include underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency. Serial interfacing with the television tuner is provided through the tuner serial port. Other serial devices, such as digital channel tunning adjustments, may be accessed through the industry-standard I2C port. User control can be monitored through the keypad scanning port, or the 16-bit remote control capture register. Receiver functions such as color and volume can be directly controlled by eight 8-bit pulse width modulated ports. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
CP96TEL0607
PRELIMINARY
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Z89332 Digital Television Controller
GENERAL DESCRIPTION (Continued)
Capture IRIN ADC Port 17 Port 00 ADC0 ADC1 ADC2 ADC3 ADC4 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0F
PWM PWM1 PWM2 PWM3 PWM4 PWM5 PWM9 PWM10
Port1 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18
Control XTAL1 XTAL2 LPF HSYNC VSYNC /Reset CPU RAM 640 x 16
Address ROM Addr Data
Register Addr/Data
OSD V1 V2 V3 VBLANK HALFBLNK ROM 24K x 16
Port0F
ROM Data
Figure 1. Functional Block Diagram
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CP96TEL0607
Z89332 Digital Television Controller
PIN DESCRIPTION
PWM10 PWM9 PWM5 PWM4 PWM3 PWM2 PWM1 Port03 Port04/ADC4 Port05/ADC3 Port00/ADC2 Port17/ADC1 GND Port10/R<0> Port06/Counter Port18/G<0> Port13/G<1> Port14/B<0> Port15/B<1> Port16/SCLK Port0F/HalfBlnk
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Z89332 Shrink DIP
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Port12/I2MSD P11/I2MSC Port02/I2SSD Port01/I2SSC Port09 Port08/R<1> IRIN Port07/CSync Vcc /Reset XTAL2 XTAL1 ANGND LPF CVI/ADC0 VSync HSync VBlank V1 V2 V3
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Figure 2. 42-Pin Shrink DIP and 48-Pin Ceramic Pin Configurations with 42- to 48-Pin Adapter Footprint
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Z89332 Digital Television Controller Table 1. 42-Pin SDIP Pin Identification Name VCC GND IRIN Function + 5 Volts Z89332 34 Direction PWR PWR I AI O OD/O* B Reset - - I I O O I [1] Notes
0 Volts 13, 30 Infrared Remote Capture 36 Input ADC[4:0] 4-Bit A/D Converter Input 9, 10, 11, 12, 28 PWM10, PWM9 14-Bit Pulse Width 1, 2 Modulator Output PWM[5:1] 8-Bit Pulse Width Modulator 3, 4, 5, 6, 7 Output Port0[F:0] Bit Programmable 21, -, -, -, -, -, 38, 37, Input/Output Ports 35, -, -, 15, 8, 40, 39, 11 Port1[8:0] Bit Programmable 16, 12, 20, 19, 18, 17, Input/Output Ports 42, 41, 14 2 SCL 39 or 41 I C Clock I/O SCD XTAL1 XTAL2 LPF HSYNC VSYNC /Reset V[3:1] I2C Data I/O Crystal Oscillator Input Crystal Oscillator Output Loop Filter H_SYNC V_SYNC Device Reset OSD Video Output Typically Drive B, G, and R Outputs 40 or 42 31 32 29 26 27 33 22, 23, 24
B BOD BOD AI AO AB B B I O
I [2] [3] I O O I I I O
Blank OSD Blank Output 25 HalfBlank OSD Half-Blank Outpu 21 RGB Digital R[1:0], G[1:0], and B[1:0] 37, 14, 17, 16, 19, 18 Outputs Outputs of the RGB Matrix SCLK Internal Processor SCLK 20 Notes: 1) Port 0 [E:A] is not available on the 42-pin SDIP version. 2) SCL I/O pin is shared with Port 0 or Port 11. 3) SCD I/O pin is shared with Port 02 or Port 12. 4) Half Blank output is a function shared with Port 0F. 5) Digital RGB outputs and the internal SCLK are shared with Port 1 [5:0]. 6) Internal processor SCLK is shared with Port 16. * PWM outputs are push/pull in Revision Z89332EA and later.
O O O O
O [4] [5] [6]
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PRELIMINARY
CP96TEL0607
Z89332 Digital Television Controller
V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25V and VCC = 4.75V
VCC = 5.25V Output Voltage Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 70% of DC Level, 10 pF Load Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 70% of DC Level, 10 pF Load Limit 4.2V 0.4V 45% - 0.15V to 55% of actual data = 11 value 0.60 V 0.4V 74% to 89% of actual data = 11 value < 50 nsec Limit 3.6V 0.4V 45% - 0.15V to 55% of actual data = 11 value 0.60V 0.4V 74% to 89% of actual data = 11 value < 50 nsec
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Setting Time VCC = 4.75V Output Voltage
Setting Time
Z893XX 32.768kHz 10 M 10 pF XTAL1
XTAL2
68 K 47 pF
Figure 3. 32K Oscillator Recommended Circuit
Z893XX
510 0.1 F
47 F
Figure 4. Recommended Low Pass Filter Circuit
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PRELIMINARY
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Z89332 Digital Television Controller
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VID VIA VO VO VO Parameter Power Supply Voltage Input Voltage Input Voltage Output Voltage Output Voltage Output Voltage Min 0 -0.3 -0.3 -0.3 -0.3 -0.3 Max 7 VCC +0.3 VCC +0.3 VCC +0.3 VCC +8 VCC +0.3 V Units V V V V Digital Inputs Analog Inputs (A/D0...A/D4) All Push-Pull Digital Output Open-Drain PWM Outputs (PWM1...PWM8) Push/Pull PWM Outputs (PWM1...PWM8) = Z89332EA and Later Revisions One Pin All Pins One Pin All Pins Conditions
IOH IOH IOL IOL TA TA
Output Current High Output Current High Output Current Low Output Current Low Operating Temperature Storage Temperature 0 -65
-10 -100 20 200 70 150
mA mA mA mA C C
DC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5V to + 5.5V; FOSC = 32.768 KHz
Symbol VIL VIH VPU VOL VOH VXL VXH VHY IIR IIL ICC IADC IADC Parameter Input Voltage Low Input Voltage High Max. Pull-Up Voltage Output Voltage Low Output Voltage High Input Voltage XTAL1 Low Input Voltage XTAL1 High Schmitt Hysteresis Reset Input Current Input Leakage Supply Current Input Current Input Current -3.0 VCC -2.0 3.0 0.75 150 3.0 100 0.5 10 VCC -0.4 0.3 VCC Min 0 0.7 VCC Max 0.2 VCC VCC VCC +0.3 0.4 0.16 4.75 1.0 3.5 0.5 90 0.01 60 Typical 0.4 3.6 Units V V V V V V V V A A mA mA A AE Revision CC,CA,EA & Later Rev. All Pins @ IOL = 1 mA @ IOL = 0.75 mA External Clock Generator Driven On XTAL1 Input Pin VRL = 0V @ 0V and VCC Conditions
Notes: A) The Z89332 should not be operated for extended periods with the crystal oscillator disconnected, except in the defined power-down modes. In the event that the Z89332 is operated with the oscillator disconnected, the device may draw higher than typical current. B) Each line of the on-screen display can consist of any number of characters, up to a maximum of 30 characters.
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PRELIMINARY
CP96TEL0607
Z89332 Digital Television Controller
AC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5V to 5.5V; FOSC = 32.768 KHz
Symbol T PC TRC,TFC TDPOR Parameter Input Clock Period Clock Input Rise and Fall Power-On Reset Delay 0.8 Min 16 Max 100 Typical 32 12 1.2 Units S S Sec
1
AC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5V to 5.5V; FOSC = 32.768 KHz
Symbol TWRES TDHS TDVS TDES TDOS TWHVS Parameter Power-On Reset Min. Width H_Sync Incoming Signal Width V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width 5.5 0.15 -12 20 Min Max 5 TPC 12.5 1.5 +12 44 2.0 11 1.0 0 32 0.5 Typical Units S S mS S S S
Note: All timing of the I2C bus interface are defined by related specifications of the I2C bus interface.
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PRELIMINARY
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Z89332 Digital Television Controller
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CP96TEL0607


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