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CXB1456R
VGA/SVGA/XGA 24-bit Receiver
Description CXB1456R is the 1 chip deserializer for VGA/SVGA/ XGA 24-bit color digital RGB, and meet to the Gigabit Video Interface specification. Features * 1 chip receiver for serial transmission of 24-bit color VGA/SVGA/XGA picture * On chip PLL circuit for data and clock recovery * On chip panel mode automatically selectable circuit * TTL compatible I/O * Support 1 pixel/shiftclock mode with 1 chip and 2 pixel/shiftclock mode with 2 chip * +3.3V single power supply * Low power consumption * 64pin plastic LQFP package with body size 10mm x 10mm Application Gigabit video interface Structure Bi-CMOS IC
TESTEXN REFRQN REFRQP SDATAN SDATAP TESTDT PANEL1 VEEA REXT LPFB LPFA VCCA VEES
64 pin LQFP (Plastic)
Absolute Maximum Ratings * Supply voltage Vcc * Storage temperature Tstg * Allowable power dissipation PD
4.2 -65 to +150 650
V C mW
Recommended Operating Condition * Supply voltage 3.3 0.3 * Operating temperature Topr 0 to +80
V C
Block Digagram & Pin out
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PANEL0
LOS
CE
CNTL 49 DE 50 SFTCLK 51 GND 52 VDD 53 VEE 54 VCC 55 HSYNC 56 VSYNC 57 B7 58 B6 59 GND 60 VDD 61 B5 62 B4 63 VDD 64 Decoder Serial to Parallel Converter CDR PLL
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CLKPOL R0 R1 GND VDD VEE VCC R2 R3 R4 R5 GND VDD R6 R7 GND
1 GND
2 B3
3 B2
4 B1
5 B0
6 G7
7 G6
8 VDD
9 10 11 12 13 14 15 16 GND G5 G4 G3 G2 G1 G0 VDD
Fig. 1. Block Diagram & Pin out
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98Y04C9X-PS
CXB1456R
Pin List Table 1. Power/Ground Pin name VDD GND VCC VEE VCCA VEEA VEES Pin number 8, 16, 20, 28, 53, 61, 64 1, 9, 17, 21, 29, 52, 60 26, 55 27, 54 44 45 46 Descriptions MOS power supply, should be connected to 3.3V 0.3V MOS ground, connected to 0V ECL power supply, connected to 3.3V 0.3V ECL ground, connected to 0V Analog power supply, connected to 3.3V 0.3V Analog ground, connected to 0V Substrate GND, connected to 0V
Table 2. Digital Signals Pin name Pin number 51 Type Descriptions Shift clock, for the data fetch at falling or rising edge Equivalent circuit
SFTCLK RED (7 to 0)
TTL out
GRN (7 to 0)
BLU (7 to 0)
18, 19, 22, 23, 24, 25, 30, 31 6, 7, 10, TTL out 11, 12, 13, 14, 15 58, 59, 62, 63, 2, 3, 4, 5 56 57 49 50 36 TTL out TTL out TTL out TTL out TTL out TTL in TTL in TTL in TTL in
VDD
Pixel data
TTL-OUT
HSYNC VSYNC CNTL DE LOS
Hsync data Vsync data Control data Display enable data Los of signal Panel mode select switch Trigger edge select switch
TTL-IN VCCA
GND
PANEL (1, 0) 35, 34 CLKPOL CE TESTEXN TESTDT 32 38 43, 37
VDD
Chip enable Reversed for TEST under fabrication
VEES GND
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CXB1456R
Table 2. Digital Signals (Cont.) Pin name Pin number Type Descriptions
VCCA
Equivalent circuit
SDATAP/N
40, 41
Rx
Serial input
SDATAP/N REFRQP/N
VDD
REFRQP/N
39, 42
Rx
Refclk request
VEEA GND
Table 3. Special Pin name Pin number Descriptions
VCC
Equivalent circuit
REXT
33
External Register
REXT VDD VEE GND
VCCA
LPFA LPFB
LPFA/B
47, 48
External loop filter
VDD VEEA GND
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CXB1456R
Electrical characteristics Table 4. Absolute Maximum Rating Description Power supply voltage TTL DC input voltage TTL output current (High) TTL output current (Low) Serial input pin voltage REFREQ output pin voltage Storage temperature Symbol VCC VI_T IOH_T IOL_T Vsdin VRQout Tstg Min. -0.3 -0.5 -10 0 -0.5 0.5 -65 Typ. Max. 4.2 4.6 0 10 VCC + 0.5 VCC + 0.5 150 Unit V V mA ' mA V V C Comments
Table 5. Recommended Operating Conditions Description Power supply voltage Ambient temperature Symbol VCC Ta Min. 3.0 0 Typ. 3.3 Max. 3.6 80 Unit V C Comments
Table 6. DC Characteristics (Under the recommended conditons. See Tab. 5) Description Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Symbol VIH_T VIL_T IIH_T IIL_T VOH_T VOL_T -0.1 7.8 VCC - 0.4 -0.5 138 77 0 -10 2.4 0.4 +0.1 11 VCC + 0.2 +0.5 173 104 Min. 2 0 Typ. Max. VCC 0.8 10 Unit V V A A V V mA mA V V mA mA VIN = VCC VIN = 0 IOH = -3mA IOL = 3mA See Fig. 3, 4 REXT = 5.6k Common mode voltage Differential voltage CL = 8pF, f = 65MHz See Fig. 9, 10 Conditions
Output HIGH current (REFREQ) IOH_RQ Output LOW current (REFREQ) Input dynamic range (SDATA) Input dynamic range (SDATA) Worst Case Supply current 16 Grayscale ICC IOL_RQ VIM_SD VID_SD
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CXB1456R
VDD/VCC/VCCA CXB1456R VCC 37 TESTDT 38 CE 43 TESTEXN REFRQN 42 REFRQP 39
50
50
A
150
A
150
GND/VEE/VEEA
Fig. 3. IOH_RQ and IOL_RQ DC measurement
TESTDT
CE
TESTEXN
Fig. 4. IOH_RQ and IOL_RQ DC measurement setting
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CXB1456R
Table 7. AC Characteristics (Under the recommended conditons. See Tab. 5) Description Minimum SFTCLK frequency Maximum SFTCLK frequency SFTCLK duty factor Pixel/Sync/Cntl/DE setup to SFTCLK Symbol Fsftclk Dsftclk Min. 65.0 35 17 9 4.5 16 9 4.5 5 3 5 3 0.5 20 0.5 0.15 65 Typ. Max. 25.0 Unit MHz MHz % ns ns ns ns ns ns ns ns ns ns s s s s Vth = 1.4V, CL = 8pF Vth = 1.4V, CL = 8pF 25MHz 40MHz 65MHz Vth = 1.4V, CL = 8pF 25MHz 40MHz 65MHz 0.8V to 2.0V, CL = 8pF 2.0V to 0.8V, CL = 8pF 0.8V to 2.0V, CL = 8pF 2.0V to 0.8V, CL = 8pF Conditions
Tsetup
Pixel/Sync/Cntl/DE hold to SFTCLK SFTCLK rise time SFTCLK fall time Pixel/Sync/Cntl/DE rise time Pixel/Sync/Cntl/DE fall time CLOCK mode assert time CLOCK mode deassert time LOS signal assert time LOS signal deassert time
Thold
Torc Tofc Tord Tord TAclk TDclk TAlos TDlos
VDD/VCC/VCCA
VCC CXB1456R
TTLout Cprobe
CL' GND/VEE/VEEA CL' + Cprobe = 8pF
oscilloscope
Fig. 5. Pixel/Sync/Cntl/DE waveform measurement
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CXB1456R
Timing Chart
1/Fsftclk
2.0V SFTCLK 0.8V Torc Setup/hold time is referred from rising edge in CLKPOL = GND falling edge in CLKPOL = VDD REDxx GRNxx BLUxx H/Vsync CNTL DE Tofc Dsftclk/Fsftclk Vth
Tsetup
Thold Tord 2.0V 0.8V Tofd
Fig. 6. TTL output timing
Pixel Sync/Cntl/DE
error
SftClk TAclk REFRQP REFRQN
Indefinite
Indefinite TDclk
SDATAP SDATAN
Fig. 7. Refclk request timing
SDATAP SDATAN TDlos
NRZ data TAlos
LOS
Fig. 8. Idle mode timing
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CXB1456R
SFTCLK
f
RGB <7, 5, 3, 1>
f/2
RGB <6, 4, 2, 0>
f/2
Fig. 9. Worst case test pattern
SFTCLK RGB <7> RGB <6> RGB <5> RGB <4> RGB <3> RGB <2> RGB <1> RGB <0>
f f/16 f/8 f/4 f/2 Fix Low Fix Low Fix Low Fix Low
Fig. 10. 16 Grayscale test pattern
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CXB1456R
CLKPOL Pin Control The CLKPOL pin is used to select the SFTCLK trigger edge. (See Table 8.) The CLKPOL pin is open High-impedance TTL input, and this should not be left open for use. (See Fig. 12. Recommended application circuit.) Table 8. SFTCLK Polarity CLKPOL L H Receiver operation trigger Rising edge Falling edge
PANEL1 and 0 Pin Control The PANEL1 and 0 pins are used to select the panel mode. (See Table 9.) For the normal use, the all frequencies of SFTCLK (25MHz to 65MHz) can be covered by fixing both PANEL1 and 0 to High. The PANEL1 and 0 pins are open High-impedance TTL inputs, and they should not be left open for use. (See Fig. 12. Recommended application circuit.) Table 9. Panel Mode PANEL1 L L H H PANEL0 L H L H Supporting panel size VGA (640 x 480) SVGA (800 x 600) XGA (1024 x 768) VGA to XGA Shift Clock 25MHz 40MHz 65MHz 25MHz to 65MHz Serial rate 750Mbps 1200Mbps 1950Mbps 750Mbps to 1950Mbps
CE Pin Control The CE pin is used to select the standby mode. (See Table 10.) The CE pin is open High-impedance TTL input, and this should not be left open for use. (See Fig. 12. Recommended application circuit.) Table 10 CE L H Operation mode Standby mode, all TTL outputs fixed to Low (excluding LOS) Normal mode
Test Pin Control The TESTEXN and TESTDT pins are for test only. Select normal mode. (See Table 11.) The TESTEXN and TESTDT pins are open High-impedance TTL inputs, and they should not be left open for use. Table 11. Test mode TESTEXN L H TESTDT X X Operation mode Test mode Normal mode
LOS Pin Output The LOS pin shows the absence of proper level of SDATA signal. The LOS pin is High when the connector is disconnected or the transmitter is idle. The LOS pin is TTL output. -9-
CXB1456R
Applications CXB1456R GVIF receiver is applied to the digital RGB signal transmission for P/C with LCD monitor Video on demand system Monitoring system Graphical controller Projector Digital TV monitor Car navigation system with GVIF transmitter, CXB1455R.
CXB1455R GVIF Transmitter 8 8 8 4
RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/ DE/CNTL SHIFTCLOCK
Parallel to Serial Converter
Encoder
Cable Driver
PLL
STP or Twin axial
Serial to Parallel Converter
Decoder
8 8 8
RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/ DE/CNTL SHIFTCLOCK
PLL CXB1456R GVIF Receiver
Fig. 11. Block Diagram of GVIF transceiver chip set
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CXB1456R
Application Cicuit
Differential cable (1) CHIP RESISTOR (1%) (2) CHIP CAPACITOR (3) FORMED BY THE PRINTED CIRCUIT PATTERN (L = 0.5 to 1.0mm/W = 0.5 to 1.0mm)
VCC 0.1 to 0.4n (3) E 33 16V 0.1 to 0.4n (3) 0.1 to 0.4n (3) 150 (1) 330 150 (1) Connector
0.1 (2) 470p (2) 47 (1) 47 (1) 48 LPFB 47 LPFA 46 VEES 45 VEEA 44 VCCA
100 (1) 47p (2) 40 39 SDATAP REFRQP
43 TESTEXN
47p (2) 42 41 REFRQN SDATAN
5.6k (1) 38 CE 37 TESTDT 36 LOS 35 PANEL1 34 PANEL0 33 REXT 330 VCC 330 SW1 H: FALLING EDGE TRIGGER L: RISING EDGE TRIGGER
49 CNTL 50 DE
32 CLKPOL R0 31 R1 30 GND 29 VDD 28 VEE 27 VCC 26 R2 25 E 0.1 (2) VCC 0.1 (2)
51 SFTCLK 0.1 (2) VCC 52 GND 53 VDD 54 VEE 0.1 (2) E 55 VCC 56 HSYNC CXB1456R 57 VSYNC 58 B7 59 B6 0.1 (2) VCC 62 B5 VCC 63 B4 GND GND 64 VDD VDD VDD 60 GND 61 VDD
R3 24 R4 23 R5 22 GND 21 VDD 20 VCC R6 19 R7 18 GND 17 G5 G4 G3 G2 G1 G0 0.1 (2)
G7 6
1 0.1 (2)
2
3
4
5
G6 7
B3
B2
B1
B0
8 VCC
9
10
11
12
13
14
15
16 0.1 (2) VCC
0.1 (2)
CNTL SFTCLK HSYNC VSYNC DE
76543210 MSB LSB BLUE DATA
76543210 MSB LSB GREEN DATA
76543210 MSB LSB RED DATA
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Fig. 12. Recommended application circuit
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CXB1456R
L2 doesn't have plane in this area
TESTEXN
48
REFRQN
SDATAN
SDATAP
REFRQP
TESTDT
PANEL1
PANEL0
LPFB
LPFA
VEES
VCCA
VEEA
49
CNTL DE
CE
LOS
REXT
SFTCLK
G G
GND VDD VEE
E
VCC HSYNC VSYNC B7 B6 GND VDD D D D D D D D D
G B5 B4 64 VDD GND B3 B2 B1 B0 G7 G6 GND G5 G4 G3 G2 G1 VDD G0 VDD R6 R7 GND G 17
G 1 16
Fig. 14. Recommended Printed Circuit Board Pattern - 12 -

E D Chip capacitor Chip resistor G 33 CLKPOL R0 R1 GND VDD G VEE VCC R2 R3 R4 R5 GND VDD G E G 32 G
, , , , , , , ,
Recommended Printed Circuit Board Structure Fig. 13. Recommended Printed Circuit Board Structure Recommended Printed Circuit Board Pattern POWER and special signal routing example
0.5mm G
L1 : Cu plate (18m) + solder coat l1 : Fiber-glass epoxy core (0.3mm) L2 : Cu plate (36m) l2 : Fiber-glass epoxy core (0.8mm) L3 : Cu plate (36m) l3 : Fiber-glass epoxy core (0.3mm) L4 : Cu plate (18m) + solder coat
Through hole to the GND plane (L2) Through hole to the VCC plane (L3)
Through hole to the VDD plane (L3)

CXB1456R
Micro Strip Line For maximum performance, the impedance between the pins SDDATAP/N of the LSI and the footprint of the connector should be 50 using a micro strip line. 50 impedance can be reached when using 0.5mm width pattern lines on L1 using this circuit board structure. The length of the lines should be identical and throughhole should not be used. L2 is recommended as the large ground plane. Terminators Terminators (100 resistor) should be located as close to the LSI as possible. Filter Devices and Reference Registors Capacitors and resistors which are connected to LPFA/B and REXT are filters and reference resistors. The region of Layer 2 (L2) is under the device and conductive patterns. The ground plane should be taken off in order to reduce parasitic capacitors. Bypass Capacitors Bypass capacitors (0.1F SMD type) should be located as close to the pins as possible. Refer to the recommendation.
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CXB1456R
Recommendation for Cable and Connector Characteristics The GVIF system uses terminators at both ends (transmitter and receiver), a cable equalizer and a small amplitude differential signal. In order to solve the problems of high speed data transmission such as signal reflection, reduce the signal level and EMI. In order to achieve the best solution, note the following:
Tx termination 50 Tx termination 100 Tx LSI Rx LSI
Microstrip line (50)
Foot print
Connector
Cable (diff. 100)
Connector
Foot print
Microstrip line (50)
It is important to note the following issues for a good data transmission system: * Good impedance matching Differential impedance should be fit to the recommended template on the next page. * Cable loss should be small and the loss curve should be smooth. Maximum loss should be less than 6dB at 1GHz. See the next page. * Skew of POS/NEG (differential signal) should be small Less than 12% of 1-bit time or 160ps@VGA, 100ps@SVGA, 60ps@XGA. * Good EMI performance cable and connectors. In order to satisfy these issues, the recommendations are as follows: * Use the differential cable which provides good controlled impedance, low loss and good skew matching. A shielded twisted pair (STP) cable is recommended. * Use a low reflectance connector. * To minimize interference from other signals, high speed signal lengths should be identical. * Use double shielded cable.
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CXB1456R
Recommended Transmission Path : Differential impedance template
Zo () 150 110 106 94 90 75
< 500ps
< 500ps
Microstrip line
Foot print
Connector
Connector
Foot print
Microstrip line
Recommended Transmission Path : Attennation Characteristics
Loss
< 6dB 2dB Measured curve
Fitting curve Frequency 1GHz
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CXB1456R
TTL output waveform with CL = 8pF
SFTCLK 65MHz TTL output
B0 T 65Mbps TTL output
1.00V/div
1.00V/div
5ns/div
SFTCLK Power spectrum
ATTEN 10dB RL 0dBm 10dB/
CENTER 65.00MHz D
CENTER 65.00MHz RBW 100kHz
VBW 100kHz
SPAN 10.00MHz SWP 50.0ms
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CXB1456R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 0.2 48 49 10.0 0.1 33 32
A 64 1 0.5 16 0.13 M + 0.2 1.5 - 0.1 17 (0.22) + 0.08 0.18 - 0.03
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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0.5 0.2
(11.0)

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