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| ICX059CL Diagonal 6mm (Type 1/3) CCD Image Sensor for CCIR Black-and-White Video Camera Description The ICX059CL is an interline CCD solid-state image sensor suitable for CCIR black-and-white video cameras. Compared with the current product ICX059AL, sensitivity is improved drastcally through the adoption of Super HAD CCD technology. This chip features a field period readout system and an electronic shutter with variable charge-storage time. Features * High sensitivity (+4dB at F8, +3dB at F1.2 compared with ICX059AL) * High resolution, low smear and low dark current * Excellent antiblooming characteristics * Continuous variable-speed shutter * Horizontal register: 5V drive * Reset gate: 5V drive Device Structure * Interline CCD image sensor * Image size: * Number of effective pixels: * Number of total pixels: * Chip size: * Unit cell size: * Optical black: * Number of dummy bits: * Substrate material: 3 Pin 9 16 pin DIP (Plastic) Pin 1 2 V 12 H 40 Diagonal 6mm (Type 1/3) Optical black position 752 (H) x 582 (V) approx. 440K pixels (Top View) 795 (H) x 596 (V) approx. 470K pixels 6.00mm (H) x 4.96mm (V) 6.50m (H) x 6.25m (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels Horizontal 22 Vertical 1 (even field only) Silicon Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E97X22A99 ICX059CL VOUT VGG VSS GND V2 8 7 6 5 V1 V3 2 4 3 Vertical register Note) Horizontal register Note) 9 10 11 12 13 14 15 16 : Photo sensor SUB VDD RG GND LH1 Pin Description Pin No. Symbol 1 2 3 4 5 6 7 8 V4 V3 V2 V1 GND VGG VSS VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Output amplifier gate bias Output amplifier source Signal output Pin No. Symbol 9 10 11 12 13 14 15 16 VDD GND SUB VL RG LH1 H1 H2 H1 H2 VL V4 1 Block Diagram and Pin Configuration (Top View) Description Output amplifier drain supply GND Substrate (Overflow drain) Protective transistor bias Reset gate clock Horizontal register final stage transfer clock Horizontal register transfer clock Horizontal register transfer clock Absolute Maximum Ratings Item Substrate voltage SUB - GND Supply voltage VDD, VOUT, VSS - GND VDD, VOUT, VSS - SUB Vertical clock input voltage V1, V2, V3, V4 - GND V1, V2, V3, V4 - SUB Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H1, H2 - V4 H1, H2, LH1, RG, VGG - GND H1, H2, LH1, RG, VGG - SUB VL - SUB V1, V2, V3, V4, VDD, VOUT - VL RG - VL VGG, VSS, H1, H2, LH1 - VL Storage temperature Operating temperature 1 +27V (Max.) when clock width < 10s, clock duty factor < 0.1%. -2- Ratings -0.3 to +55 -0.3 to +18 -55 to +10 -15 to +20 to +10 to +15 to +17 -17 to +17 -10 to +15 -55 to +10 -65 to +0.3 -0.3 to +30 -0.3 to +24 -0.3 to +20 -30 to +80 -10 to +60 Unit V V V V V V V V V V V V V V C C 1 Remarks ICX059CL Bias Conditions Item Output amplifier drain voltage Output amplifier gate voltage Output amplifier source Substrate voltage adjustment range Fluctuation range after substrate voltage adjustment Reset gate clock voltage adjustment range Fluctuation range after reset gate clock voltage adjustment Protective transistor bias Symbol VDD VGG VSS VSUB VSUB VRGL VRGL VL 9.0 -3 1.0 -3 2 Min. 14.55 3.8 Typ. 15.0 4.2 Max. 15.45 4.65 Unit V V 5% V % V % 1, 6 1 Remarks Grounded with 820 resistor 18.5 +3 4.0 +3 DC Characteristics Item Output amplifier drain current Input current Input current Symbol IDD IIN1 IIN2 Min. Typ. 5 1 10 Max. Unit mA A A 3 4 Remarks 1 Indications of substrate voltage (VSUB) * reset gate clock voltage (VRGL) setting value. The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. Fluctuation range after adjustment is 3%. VSUB code VRGL code one character indication one character indication VRGL code VSUB code Code and optimal setting correspond to each other as follows. 1 2 3 4 5 6 7 VRGL code Optimal setting VSUB code Optimal setting 1.0 1.5 2.0 2.5 3.0 3.5 4.0 E f G h J K L m N P Q R S T U V W X Y Z 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 ICX059CL Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage | VVH1 - VVH2 | VVH3 - VVH VVH4 - VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage Reset gate clock voltage VH, VLH VHL, VLHL VRG VRGLH - VRGLL 22.5 23.5 4.75 -0.05 4.5 5.0 0 5.0 -0.25 -0.25 Min. 14.55 -0.05 -0.2 -9.0 7.8 Typ. 15.0 0 0 -8.5 8.5 Max. 15.45 0.05 0.05 -8.0 9.05 0.1 0.1 0.1 0.5 0.5 0.5 0.5 5.25 0.05 5.5 0.8 24.5 Unit V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 5 High-level coupling High-level coupling Low-level coupling Low-level coupling 5 5 6 Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks Substrate clock voltage VSUB 5 The horizontal final stage transfer clock input pin LH1 is connected to the horizontal transfer clock input pin H1. 6 The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image sensor has not significance. Item Reset gate clock voltage Symbol VRGL VRG Min. -0.2 8.5 Typ. 0 9.0 Max. 0.2 9.5 Unit V V Waveform diagram 4 4 Remarks -4- ICX059CL Clock Equivalent Circuit Constant Item Capacitance between vertical transfer clock and GND Symbol CV1, CV3 CV2, CV4 CV12, CV34 Capacitance between vertical transfer clocks CV23, CV41 CV13 CV24 Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between horizontal final stage transfer clock and GND Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor CH1, CH2 CHH CLH CRG CSUB R1, R2, R3, R4 RGND RH Min. Typ. 1000 560 470 390 180 100 47 51 8 8 270 80 15 15 Max. Unit pF pF pF pF pF pF pF pF pF pF pF Remarks V1 CV12 V2 R1 R2 RH H1 RH H2 CHH CV23 CV13 CH1 CH2 CV1 CV41 CV24 CV2 CV4 RGND CV3 R4 CV34 R3 V4 V3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit -5- ICX059CL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II M VVT 10% 0% tr twh tf 0V M 2 (2) Vertical transfer clock waveform V1 VVHH V3 VVHH VVHH VVHL VVHL VVH3 VVHH VVH1 VVH VVHL VVH VVHL VVL1 VVLH VVL3 VVLH VVLL VVL VVLL VVL V2 VVHH VVHH V4 VVH VVHH VVHH VVH VVHL VVH2 VVHL VVHL VVH4 VVHL VVL2 VVLH VVLH VVLL VVL VVL4 VVLL VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) -6- ICX059CL (3) Horizontal transfer clock waveform tr twh tf 90% VH 10% VHL twl (4) Reset gate clock waveform tr twh tf VRGH twl Point A RG waveform VRGLH VRGL VRGLL VRG VRGL + 0.5V LH1 waveform 2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH - VRGL -7- ICX059CL (5) Substrate clock waveform 100% 90% M VSUB 10% 0% M 2 tf VSUB tr twh Clock Switching Characteristics Note) Because the horizontal final stage transfer clock LH1 is connected to the horizontal transfer clock H1, specifications will be the same as H1. Item Symbol VT V1, V2, V3, V4 H1, LH1 H2 18 21 24 26 6.41 6.41 11 13 51 19.5 26 19 24 10 17.5 10 0.01 0.01 3 0.5 15 twh twl tr tf Unit Remarks s During readout Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock Vertical transfer clock Horizontal transfer clock During imaging 2.3 2.5 0.5 15 0.5 250 ns 1 10 17.5 10 0.01 0.01 3 0.5 15 ns 2 During H1, LH1 parallel-serial H2 conversion RG SUB s ns s During drain charge Reset gate clock Substrate clock 1.5 1.8 1 When vertical transfer clock driver CXD1267AN is used. 2 tf tr - 2ns, and the cross-point voltage (VCR) for the H1 * LH1 rising side of the H1 * LH1 and H2 waveforms must be at least 2.5V. Item Horizontal transfer clock Symbol H1 * LH1, H2 two Min. 16 Typ. 20 Max. Unit ns Remarks 3 3 The overlap period for twh and twl of horizontal transfer clocks H1 * LH1 and H2 is two. -8- ICX059CL Image Sensor Characteristics Item Sensitivity Saturation signal Smear Video signal shading Dark signal Dark signal shading Flicker Lag Symbol S Vsat Sm SH Vdt Vdt F Lag Min. 360 540 0.002 0.007 20 25 2 1 2 0.5 Typ. 460 Max. Unit mV mV % % % mV mV % % Measurement method 1 2 3 4 4 5 6 7 8 (Ta = 25C) Remarks Ta = 60C Zone 0 and I Zone 0 to II' Ta = 60C Ta = 60C Zone Definition of Video Signal Shading 752 (H) 12 12 8 H 8 V 10 H 8 582 (V) Zone 0, I Zone II, II' V 10 6 Ignored region Effective pixel region -9- ICX059CL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the substrate voltage and the reset gate clock voltage are set to the values indicated on the device, and the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs x 250 [mV] 50 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of the signal output, 200mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value VSm [mV] of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 x x x 100 [%] (1/10V method conversion value) 200 500 10 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax - Vmin)/200 x 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. - 10 - ICX059CL 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (Vf [mV]). Then substitute the value into the following formula. F = (Vf/200) x 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) x 100 [%] FLD SG1 Light Strobe light timing Signal output 200mV Output Vlag (lag) - 11 - Drive Circuit 15V 100k 20 19 18 17 16 15 14 13 22/16V 39k 100k 820 47/6.3V 12 3.3/16V 1/35V 0.1 -8.5V 0.1 0.1 1 5V VSUB 0.1 2 3 XSUB 4 XV2 5 6 CXD1267AN XV1 XSG1 7 8 XV3 9 XSG2 11 22/20V 1 2 3 45 67 8 100 1/6.3V XV4 10 V3 V4 V2 V1 VGG VSS GND VOUT H1 LH1 GND H2 H2 16 15 14 13 12 11 10 RG VL SUB 9 2200p 0.01 1M H1 2SA1175 100k 10k 10/16V VDD - 12 - ICX059 (BOTTOM VIEW) 0.01 2SK523 3.9k [A] CCD OUT 3.3/20V 47k 0.1 RG ICX059CL ICX059CL Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics) 1.0 0.9 0.8 0.7 Relative Response 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 Wave Length [nm] 800 900 1000 Sensor Readout Clock Timing Chart HD V1 V2 Odd Field V3 V4 41.6 0.2 1.6 2.5 2.5 2.5 2.5 V1 V2 Even Field V3 V4 Unit : s - 13 - Drive Timing Chart (Vertical Sync) FLD VD BLK HD 15 10 20 25 310 315 325 320 620 SG1 - 14 - 246 135 246 135 582 581 SG2 V1 V2 V3 V4 135 246 1 35 246 CCD OUT CLP1 625 1 2 3 4 5 581 582 330 335 340 ICX059CL Drive Timing Chart (Horizontal Sync) HD BLK H1/LH1 1 2 3 5 10 10 40 20 22 1 2 3 1 2 3 20 H2 10 745 RG SHP - 15 - SHD V1 V2 V3 V4 CLP1 SUB 750 752 1 3 5 20 30 ICX059CL ICX059CL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Cover glass 50N Plastic package Compressive strength 50N 1.2Nm Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. - 16 - ICX059CL c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to the other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. - 17 - Package Outline Unit: mm 16pin DIP (450mil) A 0 to 9 6.1 9 16 D ~ 2.5 C 11.43 8.4 5.7 V 2-R0.5 ~ 2.5 H 9.5 11.4 0.1 0.5 B' 3.1 0.3 M 1.27 3.5 0.3 - 18 - 1.2 2.5 1. "A" is the center of the effective image area. 3.35 0.15 9.2 ~ 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 3. The bottom "C" of the package, and the top of the cover glass "D" are the height reference. 4. The center of the effective image area relative to "B" and "B'" is (H, V) = (6.1, 5.7) 0.15mm. 5. The rotation angle of the effective image area relative to H and V is 1. 6. The height from the bottom "C" to the effective image area is 1.41 0.10mm. The height from the top of the cover glass "D" to the effective image area is 1.94 0.15mm. 7. The tilt of the effective image area relative to the bottom "C" is less than 50m. The tilt of the effective image area relative to the top "D" of the cover glass is less than 50m. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. 0.69 1.27 0.46 0.3 (For the first pin only) PACKAGE STRUCTURE PACKAGE MATERIAL Plastic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42 ALLOY ICX059CL PACKAGE WEIGHT 0.9g 0.25 1.2 11.6 10.3 12.2 0.1 8 1 2.5 B |
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