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Preliminary W78C33B 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C33B microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the market. It is functional compatible with the industry standard 80C32 microcontroller series except the one extra 4-bit bit-addressable I/O port (Port 4). The W78C33B contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters, and a serial port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256 bytes of RAM, and the device supports ROMless operation for application programs. The W78C33B microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
FEATURES
* 8-bit CMOS microcontroller * Fully static design * Low standby current at full supply voltage * DC-40 MHz operation * 256 bytes of on-chip scratchpad RAM * ROMless operation * 64K bytes program memory address space * 64K bytes data memory address space * Four 8-bit bidirectional ports * One extra 4-bit bidirectional port * Three 16-bit timer/counters * One full duplex serial port * Boolean processor * Six-source, two-level interrupt capability * Built-in power management * Packages:
- PLCC 44: W78C33BP-24/40 - QFP 44: W78C33BF-24/40 - TQFP 44: W78C33BM-24/40
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Publication Release Date: June 1998 Revision A1
Preliminary W78C33B
PIN CONFIGURATIONS
44-Pin PLCC (W78C33BP)
T 2 E X , PPPP 1111 .... 4321 A D 0 , P P 4V0 .C. 2C0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3
T 2 , P 1 . 0
P1.5 P1.6 P1.7 RST RXD, P3.0 P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 10 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS. . L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 35 34 33 32 31 30 29 28 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
44-Pin QFP/TQFP (W78C33BF/W78C33BM)
T 2 E X , PPPP 1111 .... 4321 T 2 , P 1 . 0 A D 0 , P P 4V0 .C. 2C0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3
P1.5 P1.6 P1.7 RST RXD, P3.0 P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
1 2 3 4 5
6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS. . L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
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Preliminary W78C33B
PIN DESCRIPTION
P0.0-P0.7
Port 0, Bits 0 through 7. Port 0 is a bi-directional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory.
P1.0-P1.7
Port 1, Bits 0 through 7. Port 1 is a bi-directional I/O port with internal pull-ups. Pins P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0-P2.7
Port 2, Bits 0 through 7. Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.
P3.0-P3.7
Port 3, Bits 0 through 7. Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate functions, which are described below:
PIN P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
ALTERNATE FUNCTION RXD Serial Receive Data TXD Serial Transmit Data INT0 External Interrupt 0 INT1 External Interrupt 1 T0 Timer 0 Input T1 Timer 1 Input WR Data Write Strobe RD Data Read Strobe
P4.0-P4.3
Port 4, Bits 0 through 3. Port 4 is a bi-directional I/O port with internal pull-ups.
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM. This pin should be kept low for all W78C33B operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor.
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Publication Release Date: June 1998 Revision A1
Preliminary W78C33B
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high state during reset with a weak pull-up.
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0 address/data bus during fetch and MOVC operations. PSEN goes to a high state during reset with a weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VCC
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
P1.0 ~ P1.7
Port 1 Port 1 Latch ACC Interrupt T1 Timer 2 Timer 0 Timer 1 UART PSW ALU Stack Pointer T2
B
Port 0 Latch Port 0
P0.0 ~ P0.7
DPTR Temp Reg. PC
Incrementor
Addr. Reg.
P3.0 ~ P3.7
Port 3
Port 3 Latch Instruction Decoder & Sequencer
SFR RAM Address
256 bytes RAM & SFR Port 2
Bus & Clock Controller
Port 2 Latch
P2.0 ~ P2.7
P4.0 ~ P4.3
Port 4
Port 4 Latch
Oscillator
Reset Block
Power control
XTAL1
XTAL2 ALE PSEN
RST
VCC
GND
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Preliminary W78C33B
FUNCTIONAL DESCRIPTION
The W78C33B architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different instruction and references both a 64K program address space and a 64K data storage space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature of the W78C33B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
Clock
The W78C33B is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78C33B relatively insensitive to duty cycle variations in the clock. Crystal Oscillator The W78C33B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts.
Power Management
Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is by a reset.
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Publication Release Date: June 1998 Revision A1
Preliminary W78C33B
Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C33B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. 2. PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1. Example: P4 MOV MOV SETB CLR REG A, P4 P4.0 P4.1 0D8H ; Output data "A" through P4.0-P4.3. ; Read P4 status to Accumulator. ; Set bit P4.0 ; Clear bit P4.1 P4, #0AH
ABSOLUTE MAXIMUM RATINGS
PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VCC-VSS VIN TA TST MIN. -0.3 VSS -0.3 0 -55 MAX. +7.0 VCC +0.3 70 +150 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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Preliminary W78C33B
DC CHARACTERISTICS
(VDD-VSS = 5V 10%, TA = 25C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3, P4 Input Current RST Input Leakage Current P0, EA Logic 1 to 0 Transition Current P1, P2, P3, P4 Input Low Voltage P0, P1, P2, P3, P4, EA Input Low Voltage RST Input Low Voltage XTAL1[*4] Input High Voltage P0, P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1 [*4] Output Low Voltage P1, P2, P3, P4
SYM. VDD IDD IIDLE IPWDN IIN1 IIN2 ILK ITL [*4]
SPECIFICATION MIN. 4.5 -50 -10 -10 -500 MAX. 5.5 20 6 50 +10 +300 +10 -200
UNIT V mA mA A A A A A
TEST CONDITIONS
No load VDD = 5.5V Idle mode VDD = 5.5V Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V 0V VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 VOL1
0 0 0 2.4 3.5 3.5 -
0.8 0.8 0.8 VDD +0.2 VDD +0.2 VDD +0.2 0.45
V V V V V V V
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Publication Release Date: June 1998 Revision A1
Preliminary W78C33B
DC Characteristics, continued
PARAMETER Output Low Voltage P0, ALE, PSEN [*3] Sink Current P1, P2, P3, P4 Sink Current P0, ALE, PSEN Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN [*3] Source Current P1, P2, P3, P4 Source Current P0, ALE, PSEN
Notes:
SYM. VOL2 ISK1 ISK2 VOH1 VOH2 ISR1 ISR2
SPECIFICATION MIN. 4 10 2.4 2.4 -120 -10 MAX. 0.45 8 14 -180 -14
UNIT V mA mA V V A mA
TEST CONDITIONS VDD = 4.5V IOL = +4mA VDD = 4.5V Vs = 0.45V VDD = 4.5V Vs = 0.45V VDD = 4.5V IOH = -100 A VDD = 4.5V IOH = -400 A VDD = 4.5V Vs = 2.4V VDD = 4.5V Vs = 2.4V
*1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 K. *3. P0, ALE and /PSEN are tested in the external access mode. *4. XTAL1 is a CMOS input. *5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN approximates to 2V.
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a 20 nS variation. The numbers below represent the performance expected from a 1.2 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
T CH F OP, TCP TCL
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Preliminary W78C33B
Continued
PARAMETER Operating Speed Clock Period Clock High Clock Low
SYMBOL FOP TCP TCH TCL
MIN. 0 25 10 10
TYP. -
MAX. 40 -
UNIT MHz nS nS nS
NOTES 1 2 3 3
Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER Address Valid to ALE Low Address Hold after ALE Low ALE Low to PSEN Low PSEN Low to Data Valid Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width SYMBOL TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW MIN. 1 TCP- 1 TCP- 1 TCP- 0 0 2 TCP- 3 TCP- TYP. 1Tcp 2 TCP 3 TCP MAX. 1Tcp+ 2 TCP 1 TCP 1 TCP UNIT nS nS nS nS nS nS nS nS 4 4 NOTES 4 1, 4 4 2 3
PSEN Pulse Width
Notes: 1. P0.0-P0.7, P2.0-P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "" ( due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER ALE Low to RD Low RD Low to Data Valid Data Hold after RD High Data Float after RD High RD Pulse Width SYMBOL TDAR TDDA TDDH TDDZ TDRD MIN. 3 TCP- 0 0 6 TCP- TYP. 6 TCP MAX. 3 TCP+ 4 TCP 2 TCP 2 TCP UNIT nS nS nS nS nS 2 NOTES 1, 2 1
Notes: 1. Data memory access time is 8 TCP. 2. "" (due to buffer driving delay and wire loading) is 20 nS.
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Publication Release Date: June 1998 Revision A1
Preliminary W78C33B
Data Write Cycle
PARAMETER ALE Low to WR Low Data Valid to WR Low Data Hold from WR High WR Pulse Width SYMBOL TDAW TDAD TDWD TDWR MIN. 3 TCP- 1 TCP- 1 TCP- 6 TCP- TYP. 6 TCP MAX. 3 TCP+ UNIT nS nS nS nS
Note: "" ( due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE SYMBOL TPDS TPDH TPDA MIN. 1 TCP 0 1 TCP TYP. MAX. UNIT nS nS nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference.
TIMING WAVEFORMS
Program Fetch Cycle
S1 XTAL1 TALW ALE T APL PSEN TPSW T AAS PORT 2 T AAH PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 T PDA TPDH, TPDZ S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
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Preliminary W78C33B
Timing Waveforms, continued
Data Read Cycle
S4 XTAL1 ALE PSEN PORT 2 A0-A7 PORT 0 TDAR RD TDRD TDDA TDDH, TDDZ A8-A15 DATA S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
Data Write Cycle
S4 XTAL1 ALE PSEN PORT 2 PORT 0 WR
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA OUT
TDAD
TDWD
TDAW
TDWR
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Publication Release Date: June 1998 Revision A1
Preliminary W78C33B
Timing Waveforms, continued
Port Access Cycle
S5 XTAL1
S6
S1
ALE TPDS PORT INPUT SAMPLE TPDH TPDA DATA OUT
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Preliminary W78C33B
TYPICAL APPLICATION CIRCUIT
Using External Program Memory and Crystal
VCC
35 21
EA XTAL1
10 u
CRYSTAL
R 20 XTAL2 10 RST
8.2 K C1 C2
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
43 AD0 42 AD1 41 AD2 40 AD3 39 AD4 38 AD5 37 AD6 36 AD7 24 25 26 27 28 29 30 31 19 18 32 33 13 11 A8 A9 A10 A11 A12 A13 A14 A15
AD0 3 AD1 4 AD2 7 AD3 8 AD413 AD514 AD617 AD718 GND 1
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 A0 5 A1 6 A2 9 A3 12 A4 15 A5 16 A6 19 A7
14 15 16 17 2 3 4 5 6 7 8 9 23 34 1 12
INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P4.0 P4.1 P4.2 P4.3 W78C33BP
OC 11 G 74LS373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A1427 A15 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
GND20 CE 22 OE 27512
44-pin PLCC
Figure A
CRYSTAL 16 MHz 24 MHz 33 MHz 40 MHz
C1 30P 15P 10P 5P
C2 30P 15P 10P 5P
R 6.8K 6.8K
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
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Publication Release Date: June 1998 Revision A1
Preliminary W78C33B
PACKAGE DIMENSIONS
44-pin PLCC
HD D
6 1 44 40
Symbol
7 39
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.185 0.020 0.145 0.026 0.016 0.008 0.648 0.648 0.150 0.028 0.018 0.010 0.653 0.653 0.155 0.032 0.022 0.014 0.658 0.658 0.508 3.683 0.66 0.406 0.203 16.46 16.46 3.81 0.711 0.457 0.254 16.59 16.59 3.937 0.813 0.559 0.356 16.71 16.71 4.699
E
HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.050 0.590 0.590 0.680 0.680 0.090
BSC 0.630 0.630 0.700 0.700 0.110 0.004
1.27 14.99 14.99 17.27 17.27 2.296
BSC 16.00 16.00 17.78 17.78 2.794 0.10
0.610 0.610 0.690 0.690 0.100
15.49 15.49 17.53 17.53 2.54
L A2 A
e
Seating Plane GD
b b1
A1 y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
44-pin QFP
HD D
Dimension in inch
Dimension in mm
Symbol
44 34
Min. Nom. Max.
--0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 --0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 --0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003 0 7
Min. Nom.
--0.05 1.90 0.25 0.101 9.9 9.9 0.635 12.95 12.95 0.65 1.295 --0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2 0.8 1.6
Max.
--0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08
1
33
E HE
11
12
e
b
22
A A1 A2 b c D E e HD HE L L1 y
Notes:
c
0
7
A2 A A1 L L1 Detail F
Seating Plane
See Detail F
y
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec.
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Preliminary W78C33B
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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Publication Release Date: June 1998 Revision A1

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