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W83194BR-39B STEP-LESS 3-DIMM CLOCK
1.0 GENERAL DESCRIPTION
The W83194BR-39B is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel Pentium II or Pentium III. W83194BR-39B provides 64 CPU/PCI frequencies which are selectable with smooth transitions by hardware or software. W83194BR-39B also provides 13 SDRAM clocks controlled by the none-delay buffer_in pin. The W83194BR-39B provides step-less frequency programming by controlling the VCO freq. and the programmable PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.
The W83194BR-39B accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at 0.5% or 0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots(ISA, PCI, CPU, DIMM) is not recommend.
2.0 PRODUCT FEATURES
* * * * * * Supports PentiumTM II and !!! CPU with I2C. 2 CPU clocks (one free-running CPU clock) 13 SDRAM clocks for 3 DIMMs 6 PCI synchronous clocks One IOAPIC clock for multiprocessor support Optional single or mixed supply: (Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 = 3.3V, VddL1 = VddL2 = 2.5V) < 250ps skew among CPU and SDRAM clocks < 250ps skew among PCI clocks < 5ns propagation delay SDRAM from buffer input Skew from CPU (earlier) to PCI clock 1 to 4ns, center 2.6ns. Smooth frequency switch with selections from 66 MHz to 200 MHz CPU Step-less frequency programming by controlling the VCO freq. and the clock output divisor ratio I2C 2-Wire serial interface and I2C read back 0.25% or 0.5% spread spectrum function to reduce EMI in freq. table mode Programmable spread spectrum in the M/N step-less mode Programmable registers to enable/stop each output and select modes MODE pin for power Management RESET# out when watch dog timer time out One 48 MHz for USB & one 24 MHz for super I/O
* * * * * * * * * * * * *
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Publication Release Date: June 2000 Revision 0.46
W83194BR-39B
PRELIMINARY
* 48-pin SSOP package
3.0 PIN CONFIGURATION
Vddq1 * PD#/REF0^ Vss Xin Xout Vddq2 PCICLK_F/MODE0* PCICLK0^/FS3& Vss PCICLK1^ PCICLK2^ PCICLK3^ PCICLK4 Vddq2 BUFFER IN Vss SDRAM11 SDRAM10 Vddq3 SDRAM 9 SDRAM 8 Vss SDATA* SDCLK*
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VddL1 IOAPIC REF1/FS2* Vss CPUCLK_F CPUCLK1 VddL2 RESET$ SDRAM12 Vss SDRAM 0 SDRAM 1 Vddq3 SDRAM 2 SDRAM 3 Vss SDRAM 4 SDRAM 5 Vddq3 SDRAM 6 SDRAM 7 Vddq4 48MHz/FS0* 24MHz/FS1*
* :internal 120K pull-high &:Internal 120K pull-down ^ :1.5X strength #: active low $ :open drain
4.0 PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low
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Publication Release Date: June 2000 Revision 0.46
W83194BR-39B
PRELIMINARY
& - Internal 120K pull-down * - Internal 120k pull-up
4.1 Crystal I/O
SYMBOL Xin Xout PIN 4 5 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally.
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL CPUCLK_F CPUCLK1 PIN 44 43 I/O OUT OUT FUNCTION Free running CPU clock. Not affected by PD# Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Powered by VddL2. Low if PD# is low. RESET# (open drain, 4ms low active pulse when Watch Dog time out) High drive buffered output of the crystal, and is powered by VddL1. SDRAM clock outputs. Fanout buffer outputs from BUFFER IN pin.(Controlled by chipset) Free running PCI clock during normal operation. Latched Input. *Mode0=1, Pin 2 is REF0; *Mode0=0, Pin2 is PD# Low skew (< 250ps) PCI clock outputs. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU and PCI clocks. Low skew (< 250ps) PCI clock outputs. PCICLK 0:3 are double strength pins PCICLK 4 is not. Inputs to fanout for SDRAM outputs.
RESET# IOAPIC SDRAM [ 0:12]
41 47 17,18,20,21,28 ,29,31,32,34, 35,37,38,40 7
OD OUT OUT
PCICLK_F/ *MODE0 PCICLK0^/FS3&
I/O
8
I/O
PCICLK [1:3]^ PCICLK 4 BUFFER IN
10,11,12,13
OUT
15
IN
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Publication Release Date: June 2000 Revision 0.46
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PRELIMINARY
4.3 I2C Control Interface
SYMBOL SDATA* SDCLK* PIN 23 24 I/O I/O IN FUNCTION Serial data of I2C 2-wire control interface Serial clock of I2C 2-wire control interface
4.4 Fixed Frequency Outputs
SYMBOL REF0^ / PD# PIN 2 I/O I/O FUNCTION 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads.(pin7 *Mode0=1) Halt all clocks at logic 0 level, when input low (pin7 *Mode0=0) REF1 / FS2* 46 I/O 14.318MHz reference clock. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 24MHz / FS1* 25 I/O 24MHz output clock. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz / FS0* 26 I/O 48MHz output for USB during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks.
4.5 Power Pins
SYMBOL Vddq1 VddL1 VddL2 Vddq2 Vddq3 Vddq4 Vss PIN 1 48 42 6, 14 19, 30, 36 27 FUNCTION Power supply for Ref [0:1] crystal and core logic. Power supply for IOAPIC output, either 2.5V or 3.3V. Power supply for CPUCLK[0:3], either 2.5V or 3.3V. Power supply for PCICLK_F, PCICLK[0:4], 3.3V. Power supply for SDRAM[0:12], and CPU PLL core, nominal 3.3V. Power for 24 & 48MHz output buffers and fixed PLL core.
3,9,16,22,33,39,45 Circuit Ground.
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PRELIMINARY 5.0 FREQUENCY BY HARDWARE
FS3
FS2
FS1
FS0
CPU(MHz) 80.00 75.00 83.30 66.82 103.00 112.00 68.01 100.23 120.00 115.00 120.00 105.00 140.00 155.00 124.00 133.30
SDRAM(MHz) 80.00 75.00 83.30 66.82 103.00 112.00 68.01 100.23 120.00 115.00 120.00 105.00 140.00 155.00 124.00 133.30
PCI(MHz) 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 30.00 38.33 40.00 35.00 35.00 38.75 31.00 33.30
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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W83194BR-39B
PRELIMINARY
6.0 MODE PIN -POWER MANAGEMENT INPUT CONTROL
MODE0, Pin7 (Latched Input)
0 1
PIN 2
PD# (Input) REF0 (Output)
7.0 FUNCTION DESCRIPTION
7.1 2-WIRE I2C CONTROL INTERFACE
The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194BR-39Binitializes with default register settings. Use of the 2-wire control interface is then optional. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a " start" condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an " acknowledge" (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller :
Clock Address A(6:0) & R/W
Ack
8 bits dummy Command code
Ack
8 bits dummy Byte count
Ack
Byte0,1,2... until Stop
Set R/W to 1 when ?ead back" , the data sequence is as follows :
Clock Address A(6:0) & R/W
Ack
Byte 0
Ack
Byte 1
Ack
Byte2, 3, 4... until Stop
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PRELIMINARY
7.2 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the default state at true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the sequence described below (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. FREQUENCY BY SOFTWARE
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
CPU(MHz) 80.00 75.00 83.30 66.82 103.00 112.00 68.01 100.23 120.00 115.00 120.00 105.00 140.00 155.00 124.00 133.30 160.00 127.00 130.00 135.00 136.00 137.00 139.00 140.00 141.00 142.00 143.00
SDRAM(MHz) 80.00 75.00 83.30 66.82 103.00 112.00 68.01 100.23 120.00 115.00 120.00 105.00 140.00 155.00 124.00 133.30 160.00 127.00 130.00 135.00 136.00 137.00 139.00 140.00 141.00 142.00 143.00
PCI(MHz) 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 30.00 38.33 40.00 35.00 35.00 38.75 31.00 33.30 40.00 31.75 32.50 33.75 34.00 34.25 34.75 35.00 35.25 35.50 35.75
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PRELIMINARY
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 144.00 145.00 146.00 148.00 149.00 CPU(MHz) 151.00 152.00 153.00 154.00 155.00 156.00 157.00 158.00 159.00 162.00 163.00 164.00 165.00 167.00 168.00 169.00 170.00 172.00 174.00 176.00 178.00 180.00 182.00 184.00 186.00 188.00 190.00 192.00 194.00 144.00 145.00 146.00 148.00 149.00 SDRAM(MHz) 151.00 152.00 153.00 154.00 155.00 156.00 157.00 158.00 159.00 162.00 163.00 164.00 165.00 167.00 168.00 169.00 170.00 172.00 174.00 176.00 178.00 180.00 182.00 184.00 186.00 188.00 190.00 192.00 194.00 36.00 36.25 36.50 37.00 37.25 PCI(MHz) 37.75 38.00 38.25 38.50 38.75 39.00 39.25 39.50 39.75 40.50 32.60 32.80 33.00 33.40 33.60 33.80 34.00 34.40 34.80 35.20 35.60 36.00 36.40 36.80 37.20 37.60 38.00 38.40 38.80
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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PRELIMINARY
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 196.00 198.00 200.00 196.00 198.00 200.00 39.20 39.60 40.00
7.2.1 Register 0: CPU Frequency Select Register (default = 0)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description SSEL5 (for frequency table selection by software via I2C) SSEL4 (for frequency table selection by software via I2C) SSEL3 (for frequency table selection by software via I2C) SSEL2 (for frequency table selection by software via I2C) SSEL1 (for frequency table selection by software via I2C) SSEL0 (for frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit 7:2 0 = Running 1 = Tristate all outputs
7.2.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 0 0 1 1 1 1 Pin 40 43 44 Reserved Reserved 0 = Normal 1 = Spread Spectrum enabled 0 = 0.25% Spread Spectrum Modulation 1 = 0.5% Spread Spectrum Modulation SDRAM12 (Active / Inactive) Reserved CPUCLK1 (Active / Inactive) CPUCLK_F (Active / Inactive) Description
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Publication Release Date: June 2000 Revision 0.46
W83194BR-39B
PRELIMINARY
7.2.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 7 14 12 11 10 8 Reserved PCICLK_F (Active / Inactive) Reserved PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLk1 (Active / Inactive) PCICLK0 (Active / Inactive) Description
7.2.4 Register 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped )
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 46 2 26 25 47 21,20,18,17 32,31,29,28 38,37,35,34 REF1 (Active / Inactive) REF0 (Active / Inactive) 48MHz (Active / Inactive) 24MHz (Active / Inactive) IOAPIC (Active / Inactive) SDRAM(8:11) (Active / Inactive) SDRAM(4:7) (Active / Inactive) SDRAM(0:3) (Active / Inactive) Description
7.2.5 Register 4: Reserved Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 @PowerUp 1 X X X X Pin Reserved Latched FS3# Latched FS2# Latched FS1# Latched FS0# Publication Release Date: June 2000 Revision 0.46 Description
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W83194BR-39B
PRELIMINARY
2 1 0 1 1 1 Reserved Reserved Reserved
7.2.6 Register 5: Reserved Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 1 1 Pin Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
7.2.7 Register 6~11: M/N step-less mode control registers 7.2.12 Register 11: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 1 0 0 0 1 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description
7.2.13 Register 12: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 @PowerUp 0 1 0 1 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Description
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PRELIMINARY
2 1 0 0 0 1 Winbond Version ID Winbond Version ID Winbond Version ID
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W83194BR-39B
PRELIMINARY 8.0 SPECIFICATIONS
8.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Vdd , VIN TSTG TB TA Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature Rating - 0.5 V to + 7.0 V - 65C to + 150C - 55C to + 125C 0C to + 70C
8.2 AC CHARACTERISTICS
Vdd = Vddq3 = 3.3V 5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V , TA = 0C to +70C Parameter Output Duty Cycle CPU/SDRAM to PCI Offset Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion VRBE 0.7 2.1 V tTLH tTHL Vover 0.7 1.5 V 0.4 1.6 ns 15 pF Load on CPU and PCI outputs 22 at source of 8 inch PCB run to 15 pF load Ring Back must not enter this range. BWJ 500 KHz tJA 500 ps tOFF tSKEW tCCJ Symbol Min 45 1 Typ 50 2.6 Max 55 4 250 250 Units % ns ps ps Test Conditions Measured at 1.5V 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V
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PRELIMINARY
8.3 DC CHARACTERISTICS
Vdd = Vddq3 = 3.3V 5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V , TA = 0C to +70C Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4 mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current for Vdd + Vddq3 Dynamic Supply Current for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b PCI Stop Current for Vdd + Vddq3 IPD3 mA ICPUS2 mA Same as above ICPUS3 mA Same as above Idd2 mA Ioz Idd3 10 A mA CPU = 66.6 MHz PCI = 33.3 Mhz with load Same as above VOH 2.4 Vdc All outputs using 3.3V power Symbol VIL VIH IIL IIH VOL 2.0 -66 5 0.4 Min Typ Max 0.8 Units Vdc Vdc A A Vdc All outputs Test Conditions
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Publication Release Date: June 2000 Revision 0.46
W83194BR-39B
PRELIMINARY
8.4 BUFFER CHARACTERISTICS
8.4.1 TYPE 1 BUFFER FOR CPU CLOCK
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.4 1.6 27 Min -27 -27 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 2.0V Vout = 1.2 V Vout = 0.3 V 10pF Load 20pF Load
8.4.2 TYPE 2 BUFFER FOR IOAPIC
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.7 V and 1.7 V Rise/Fall Time Max Between 0.7 V and 1.7 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.4 1.8 28 -29 Min Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.4 V Vout = 2.7 V Vout = 1.0 V Vout = 0.2 V 10pF Load 20pF Load
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Publication Release Date: June 2000 Revision 0.46
W83194BR-39B
PRELIMINARY 8.4.3 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 1.0 4.0 29 Min -29 -23 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135V Vout = 1.95 V Vout = 0.4 V 10pF Load 20pF Load
8.4.4 TYPE 4 BUFFER FOR SDRAM (0:12)
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 1.3 53 -46 Min Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.65 V Vout = 3.135 V Vout = 1.65 V Vout = 0.4 V 20pF Load 30pF Load
8.4.5 TYPE 5 BUFFER FOR PCICLK(0:4,F)
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 2.0 30 38 Min -33 -33 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 15pF Load 30pF Load
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Publication Release Date: June 2000 Revision 0.46
W83194BR-39B
PRELIMINARY
9.0 OPERATION OF DUAL FUCTION PINS
Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins is latched into their appropriate internal registers. Once the correct information is properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
2.5V
Vdd
#7 PCICLK_F/MODE #46 REF1/FS2 #25 24/FS1 #26 48/FS0
Output tri-state
Output pull-low
Within 3ms
Input All other clocks
Output tri-state
Output
Output pull-low
Each of these pins has a large pull-up resistor ( 250 k @3.3V ) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 k resistor is recommended to be connected to Vdd if logic 1 is expected. Otherwise, there should be direct connection to ground if a logic 0 is desired. The 10 k resistor should be placed before the serious terminating resistor. Note that these logic will only be latched at initial power on. If optional EMI reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. These capacitors have typical values ranging from 4.7pF to 22pF.
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W83194BR-39B
PRELIMINARY
Vdd
10k Device Pin 10k
Series Terminating Resistor
Clock Trace EMI Reducing Cap Optional
Ground
Ground
Programming Header
Vdd Pad
Ground Pad Series Terminating Resistor
10k Device Pin
Clock Trace EMI Reducing Cap Optional Ground
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Publication Release Date: June 2000 Revision 0.46
W83194BR-39B
PRELIMINARY 10.0 ORDERING INFORMATION
Part Number W83194BR-39B Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
11.0 HOW TO READ THE TOP MARKING
W83194BR-39B 28051234 814GBA
1st line: Winbond logo and the type number: W83194BR-39B 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR B: Winbond internal use code A: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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W83194BR-39B
PRELIMINARY 12.0 PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
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Publication Release Date: June 2000 Revision 0.46

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