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 W83782D Winbond H/W Monitoring IC
W83782D Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 n.a. n.a. P.40 P.42 98/7 99/4 99/4 0.5 0.55 0.55 Dates Version Version on Web n.a. n.a. A1 A1 Main Contents All the version before 0.50 are for internal use. First publication. Add the content of Diode Selection Register Index 59h(Bank0) Add the content of VBAT Monitor Control Register Index 5Dh (Bank0)
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Preliminary W83782D
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ............................................................................................1 2. FEATURES.......................................................................................................................2
2.1 MONITORING ITEMS .........................................................................................................................2 2.2 ACTIONS ENABLING .........................................................................................................................2 2.3 GENERAL ............................................................................................................................................2 2.4 PACKAGE ............................................................................................................................................2
3. KEY SPECIFICATIONS .................................................................................................3 4. PIN CONFIGURATION ..................................................................................................3 5. PIN DESCRIPTION.........................................................................................................4 6. FUNCTIONAL DESCRIPTION......................................................................................7
6.1 GENERAL DESCRIPTION...................................................................................................................7 6.2 ACCESS INTERFACE..........................................................................................................................7 6.2.1 ISA interface .................................................................................................................................7 6.2.2 I2C interface..................................................................................................................................9 6.2.3 The first serial bus access timing are shown as follow:...................................................................9 6.2.4 The serial bus timing of the temperature 2 and 3 is shown as follow: ...........................................11 6.3 ANALOG INPUTS ..............................................................................................................................14 6.3.1 Monitor over 4.096V voltage: ......................................................................................................15 6.3.2 Monitor negative voltage: ............................................................................................................15 6.3.3 Monitor temperature from thermistor:..........................................................................................16 6.3.4 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904 .................16 6.4 FAN SPEED COUNT AND FAN SPEED CONTROL.........................................................................17 6.4.1 Fan speed count ...........................................................................................................................17 6.4.2 Fan speed control.........................................................................................................................19
-I-
Publication Release Date: April 1999 Version A1
Preliminary W83782D
6.5 TEMPERATURE MEASUREMENT MACHINE ................................................................................20 6.5.1 The W83782D temperature sensor 1 SMI# interrupt has two modes: ...........................................21 6.5.2 The W83782D temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. ....................................................................................................22 6.5.3 The W83782D temperature sensor 2 and 3 Over-Temperature (OVT) has two modes, and they are programmed at Bank1 and Bank2 CR[52h] bit1 . These two bits needs to be programmed the same value. ...........................................................................................................................................23
7. REGISTERS AND RAM ...............................................................................................24
7.1 ADDRESS REGISTER (PORT X5H) ..................................................................................................24 7.2 DATA REGISTER (PORT X6H) .........................................................................................................25 7.3 CONFIGURATION REGISTER 3/4 INDEX 40H...................................................................................26 7.4 INTERRUPT STATUS REGISTER 13/4 INDEX 41H............................................................................26 7.5 INTERRUPT STATUS REGISTER 2 3/4 INDEX 42H...........................................................................27 7.6 SMI# MASK REGISTER 1 3/4 INDEX 43H..........................................................................................28 7.7 SMI# MASK REGISTER 2 3/4 INDEX 44H..........................................................................................28 7.8 RESERVED REGISTER 3/4 INDEX 45H..............................................................................................29 7.9 CHASSIS CLEAR REGISTER -- INDEX 46H ....................................................................................29 7.10 VID/FAN DIVISOR REGISTER 3/4 INDEX 47H................................................................................29 7.11 SERIAL BUS ADDRESS REGISTER 3/4 INDEX 48H........................................................................30 7.12 VALUE RAM 3/4 INDEX 20H- 3FH OR 60H - 7FH (AUTO-INCREMENT).......................................31 7.13 VOLTAGE ID (VID4) & DEVICE ID - 49H .....................................................................................33 7.14 TEMPERATURE 2 AND TEMPERATURE 3 SERIAL BUS ADDRESS REGISTER--INDEX 4AH.33 7.15 PIN CONTROL REGISTER - INDEX 4BH .......................................................................................34 7.16 IRQ#/OVT# PROPERTY SELECT - INDEX 4CH.............................................................................35 7.17 FAN IN/OUT AND BEEP/GPO# CONTROL REGISTER - INDEX 4DH..........................................36 7.18 REGISTER 50H ~ 5FH BANK SELECT - INDEX 4EH (NO AUTO INCREASE) ............................37
- II -
Preliminary W83782D
7.19 WINBOND VENDOR ID - INDEX 4FH (NO AUTO INCREASE)....................................................37 7.20 WINBOND TEST REGISTER -- INDEX 50H - 55H (BANK 0) .......................................................38 7.21 BEEP CONTROL REGISTER 1-- INDEX 56H (BANK 0) ................................................................38 7.22 BEEP CONTROL REGISTER 2-- INDEX 57H (BANK 0) ................................................................39 7.23 CHIP ID -- INDEX 58H (BANK 0)....................................................................................................40 7.24 DIODE SELECTION REGISTER -- INDEX 59H (BANK 0)............................................................40 7.25 PWMOUT2 CONTROL -- INDEX 5AH (BANK 0) .......................................................................40-A 7.26 PWMOUT1 CONTROL -- INDEX 5BH (BANK 0) ...........................................................................41 7.27 PWMOUT1/2 CLOCK SELECT -- INDEX 5CH (BANK 0) ..............................................................41 7.28 VBAT MONITOR CONTROL REGISTER -- INDEX 5DH (BANK 0)..............................................42 7.29 PWMOUT3 CONTROL -- INDEX 5EH (BANK 0) ...........................................................................43 7.30 PWMOUT4 CONTROL -- INDEX 5FH (BANK 0)............................................................................43 7.31 TEMPERATURE SENSOR 2 TEMPERATURE (HIGH BYTE) REGISTER - INDEX 50H (BANK1)44 7.32 TEMPERATURE SENSOR 2 TEMPERATURE (LOW BYTE) REGISTER - INDEX 51H (BANK1)44 7.33 TEMPERATURE SENSOR 2 CONFIGURATION REGISTER - INDEX 52H (BANK1)...................45 7.34 TEMPERATURE SENSOR 2 HYSTERESIS (HIGH BYTE) REGISTER - INDEX 53H (BANK 1) ..46 7.35 TEMPERATURE SENSOR 2 HYSTERESIS (LOW BYTE) REGISTER - INDEX 54H (BANK 1) ...46 7.36 TEMPERATURE SENSOR 2 OVER-TEMPERATURE (HIGH BYTE) REGISTER - INDEX 55H (BANK 1) ............................................................................................................................................47 7.37 TEMPERATURE SENSOR 2 OVER-TEMPERATURE (LOW BYTE) REGISTER - INDEX 56H (BANK 1) ............................................................................................................................................47 7.38 TEMPERATURE SENSOR 3 TEMPERATURE (HIGH BYTE) REGISTER - INDEX 50H (BANK2)48 7.39 TEMPERATURE SENSOR 3 TEMPERATURE (LOW BYTE) REGISTER - INDEX 51H (BANK2)48 7.40 TEMPERATURE SENSOR 3 CONFIGURATION REGISTER - INDEX 52H (BANK 2)..................48 7.41 TEMPERATURE SENSOR 3 HYSTERESIS (HIGH BYTE) REGISTER - INDEX 53H (BANK 2) ..49 7.42 TEMPERATURE SENSOR 3 HYSTERESIS (LOW BYTE) REGISTER - INDEX 54H (BANK 2) ...49 7.43 TEMPERATURE SENSOR 3 OVER-TEMPERATURE (HIGH BYTE) REGISTER - INDEX 55H (BANK 2) ............................................................................................................................................50 7.44 TEMPERATURE SENSOR 3 OVER-TEMPERATURE (LOW BYTE) REGISTER - INDEX 56H (BANK 2) ............................................................................................................................................50 7.45 INTERRUPT STATUS REGISTER 33/4 INDEX 50H (BANK4)..........................................................51 7.46 SMI# MASK REGISTER 3 3/4 INDEX 51H (BANK 4).......................................................................51 7.47 BEEP CONTROL REGISTER 3-- INDEX 53H (BANK 4) ................................................................52 7.48 RESERVED REGISTER - INDEX 54H--58H (BANK 4)...................................................................52
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Publication Release Date: April 1999 Version A1
Preliminary W83782D
7.49 REAL TIME HARDWARE STATUS REGISTER I -- INDEX 59H (BANK 4)..................................53 7.50 REAL TIME HARDWARE STATUS REGISTER II -- INDEX 5AH (BANK 4)................................54 7.51 REAL TIME HARDWARE STATUS REGISTER III -- INDEX 5BH (BANK 4)...............................54 7.52 PWMOUT3/4 CLOCK SELECT -- INDEX 5CH (BANK 4) ..............................................................55 7.53 VALUE RAM 23/4 INDEX 50H - INDEX 5AH (AUTO-INCREMENT) (BANK 5)............................56 7.54 WINBOND TEST REGISTER - INDEX 50H (BANK 6) ...................................................................56
8. SPECIFICATIONS ........................................................................................................57
8.1 ABSOLUTE MAXIMUM RATINGS...................................................................................................57 8.2 DC CHARACTERISTICS ...................................................................................................................57 8.3 AC Characteristics...............................................................................................................................59 8.3.1 ISA Read/Write Interface Timing ................................................................................................59 8.3.2 Serial Bus Timing Diagram .........................................................................................................60
9. HOW TO READ THE TOP MARKING ......................................................................61 10. PACKAGE DIMENTIONS..........................................................................................62 11. APPLICATION CIRCUIT OF WINBOND W83782D / 781D ...................................63
- IV -
Priliminary W83782D WINBOND H/W MONITORING IC
1. GENERAL DESCRIPTION
W83782D is an evolving version of W83782D --- Winbond's most popular hardware status monitoring IC. The W83782D can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83782D provides both ISA and I2CTM serial bus interface. An 8-bit analog-to-digital converter (ADC) was built inside W83782D. The W83782D can simultaneously monitor 9 analog voltage inputs, 2 fan tachometer inputs, 3 remote temperature, one case-open detection signal. The remote temperature sensing can be performed by thermistors, or 2N3904 NPN-type transistors, or directly from IntelTM Deschutes CPU thermal diode output. Also the W83782D provides: 4 PWM (pulse width modulation) outputs for the fan speed control; beep tone output for warning; SMI#, OVT#, GPO# signals for system protection events. Through the application software or BIOS, the users can read all the monitored parameters of system from time to time. And a pop-up warning can be also activated when the monitored item was out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, or IntelTM LDCM (LanDesk Client Management), or other management application software. Also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters is out of the preset range. Additionally, 5 VID inputs are provided to read the VID of CPU (i.e. PentiumTM II) if applicable. This is to provide the Vcore voltage correction automatically. Also W83782D uniquely provides an optional feature: early stage (before BIOS was loaded) beep warning. This is to detect if the fatal elements present --- Vcore or +3.3V voltage fail, and the system can not be boomed up. Also there are 3 specific pins to provide selectable address setting for application of multiple devices (up to 8 devices) wired through I2CTM interface.
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
2. FEATURES
2.1 Monitoring Items
* 3 thermal inputs from remote thermistors or 2N3904 NPN-type transistors or PentiumTM II (Deschutes) thermal diode output * 9 voltage inputs --- typical for Vcore, +3.3V, +12V, -12V, +5V, -5V, +5V Vsb, Vbat, and one reserved * 3 fan speed monitoring inputs * Case open detection input * WATCHDOG comparison of all monitored values * Programmable hysteresis and setting points (alarm thresholds) for all monitored items
2.2 Actions Enabling
* Beep tone warning * 4 PWM (pulse width modulation) outputs for fan speed control (3 are MUX optional) --- Total up to 3 sets of fan speed monitoring and controlling * Issue SMI#, OVT#, GPO# signals to activate system protection * Warning signal pop-up in application software
2.3 General
* * * * ISA and I2CTM serial bus interface 5 VID input pins for CUP Vcore identification (for PentiumTM II) Initial power fault beep (for +3.3V, Vcore) Master reset input to W83782D
* Independent power plane of digital Vcc and analog Vcc (inputs to IC) * 3 pins (IA0, IA1, IA2) to provide selectable address setting for application of multiple devices (up 2 TM to 8 devices) wired through I C interface * IntelTM LDCM (DMI driver 2.0) support TM * Acer ADM (DMI driver 2.0) support * Winbond hardware monitoring application software (Hardware DoctorTM ) support, for both Windows 95/98 and Windows NT 4.0/5.0 * Input clock rate optional for 24, 48, 14.318 Mhz * 5V Vcc operation
2.4 Package
* 48-pin LQFP
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Preliminary W83782D
3. KEY SPECIFICATIONS
* Voltage monitoring accuracy * Monitoring Temperature Range and Accuracy - 40C to +120C * Supply Voltage * Operating Supply Current * ADC Resolution 3C(Max) 5V 5 mA typ. 8 Bits 1% (Max)
4. PIN CONFIGURATION
B E E P / GV PI OD #3
V C O R E A
V+ ++ I 3.3 5 12 12 V VV NI IIV RN NN I N 0
V B A T
55G VVN SID BNA
36
25 24
VREF VTIN3/PIITD3 VTIN2/PIITD2 VTIN1/PIITD1 VID0 OVT# ARDMSEL SMI# SA2/IA2 SA1/IA1 SA0/IA0 CS#
37
W83782D
48 1 12
13
VID2 PWMTOUT1 SD A SC L FAN1IO FAN2IO FAN3IO/PWMOUT2 VID4 CASEOPEN MR GND D VCC
I O R #
I O W #
CD DDD D D L7 6543 2 K I N
D 1 / P W M O U T 4
D 0 / P W M O U T 3
V I D 1
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
5. PIN DESCRIPTION
I/O12t I/O12ts OUT12 AOUT OD12 INt INts AIN - TTL level bi-directional pin with 12 mA source-sink capability - TTL level and schmitt trigger - Output pin with 12 mA source-sink capability - Output pin(Analog) - Open-drain output pin with 12 mA sink capability - TTL level input pin - TTL level input pin and schmitt trigger - Input pin(Analog)
PIN NAME IOR# IOW# CLKIN D7~D2
PIN NO. 1 2 3 4-9
TYPE IN t s IN t s IN t I/O12t
DESCRIPTION An active low standard ISA bus I/O Read Control. An active low standard ISA bus I/O Write Control. System clock input. Can select 48MHz or 24MHz or 14.318MHz. The default is 24MHz. Bi-directional ISA bus Data lines. D0 corresponds to the low order bit, with D7 the high order bit. These pins are activated if pin ADRMSEL=0. Bi-directional ISA bus Data lines. This pin is activated if pin ADRMSEL=0. / Fan speed control PWM output. This pin is activated if pin ADRMSEL=1. Bi-directional ISA bus Data lines. This pin is activated if pin ADRMSEL=0. / Fan speed control PWM output. This pin is activated if pin ADRMSEL=1. Voltage Supply readouts from P6. This value is read in the VID/Fan Divisor Register. +5V VCC power. Bypass with the parallel combination of 10F (electrolytic or tantalum) and 0.1F (ceramic) bypass capacitors. Internally connected to all digital circuitry. Master reset input. CASE OPEN detection . An active low input from an external device when case is opened. This signal can be latched if pin VBAT is connect to battery, even W83782D is power off. Voltage Supply readouts from P6. This value is read in the bit <0> of Device ID Register.
D1 / PWMOUT4 D0 / PWMOUT3 VID1 VCC (+5V) GNDD MR CASEOPEN#
10
I/O12t OUT12
11
I/O12t OUT12
12 13 14 15 16
INt POWER DGROUND IN t s INt
VID4
17
IN t
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Preliminary W83782D
Pin Discription, continued
PIN NAME FAN3IO/ PWMOUT2 FAN2IOFAN1IO SCL SDA PWMOUT1 VID2 VID3 BEEP/GPO# GNDA -5VIN 5VSB VBAT -12VIN +12VIN +5VIN +3.3VIN VINR0 VCOREA VREF VTIN3 / PIITD3
PIN NO. 18 19-20
TYPE I/O12t I/O12t
DESCRIPTION 0V to +5V amplitude fan tachometer input. / Fan speed control PWM output. 0V to +5V amplitude fan tachometer input / Fan on-off control output. These multi-functional pins can be programmable input or output.
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
INt s OD12 OUT12 IN t IN t OD12 AGROUND AIN AIN AIN AIN AIN AIN AIN AIN AIN AOUT AIN
Serial Bus Clock. Serial Bus bi-directional Data. Fan speed control PWM output. Voltage Supply readouts from P6. This value is read in the VID/Fan Divisor Register. Voltage Supply readouts from P6. This value is read in the VID/Fan Divisor Register. Beep (Default) / General purpose output This multi-functional pin is programmable. Internally connected to all analog circuitry. The ground reference for all analog inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. (This pin should be connected to 3V BATTERY.) 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. This pin is Analog Vcc and connects internal monitor channel IN3 with fixed scale. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. Reference Voltage. Thermistor 3 terminal input.(Default) / PentiumTM II diode 3 input. This multi-functional pin is programmable.
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
Pin Discription, continued
PIN NAME VTIN2 / PIITD2 VTIN1 / PIITD1 VID0 OVT# ADRMSEL
PIN NO. 39
TYPE AIN
DESCRIPTION Thermistor 2 terminal input. (Default)/ PentiumTM II diode 2 input. This multi-functional pin is programmable.
40
AIN
Thermistor 1 terminal input. (Default)/ PentiumTM II diode 1 input. This multi-functional pin is programmable.
41 42 43
IN t OD12 INt
Voltage Supply readouts from P6. This value is read in the VID/Fan Divisor Register. Over temperature Shutdown Output. Pin 45--47 mode selection. 0 = The 3 lowest order bits of ISA Address Bus.(Default, internal pull-down 47K ohm) 1 = 7 bit I2CTM address setting pin.(bit2 - bit0)
SMI#
44
OD12
System Management Interrupt (open drain). This output is enabled when Bit 1 in the Configuration Register is set to 1. The default state is disabled. The three lowest order bits of the 16-bit ISA Address Bus. A0 corresponds to the lowest order bit. (Default, when ARDMSEL =0 or left open ) The hardware setting pin of 7 bit I2CTM serial address bit2, bit1 and bit0 at CR[48h]. (When ARDMSEL =1) Chip Select input from an external decoder which decodes high order address bits on the ISA Address Bus. This is an active low input.
SA2-SA0
45-47
INt
IA2,IA1,IA0 CS# 48
INt IN t
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Preliminary W83782D
6. FUNCTIONAL DESCRIPTION
6.1 General Description
The W83782D provides 7 analog positive inputs, 3 fan speed monitors, at most 4 sets for fan PWM (Pulse Width Modulation) control, 3 thermal inputs from remote thermistors or 2N3904 transistors or PentiumTM II (Deschutes) thermal diode outputs, case open detection and beep function output when the monitor value exceed the set limit value including voltage, temperature, or fan counter. When start the monitor function on the chip, the watch dog machine monitor every function and store the value to registers. If the monitor value exceeds the limit value, the interrupt status will be set to 1.
6.2 Access Interface
The W83782D provides two interface for microprocessor to read/write internal registers. 6.2.1 ISA interface The first interface uses ISA Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The high byte (from ISA address bus bit15~bit3) of these ports is decoded by Chip Select (CS#), the general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: W83782D Index register port. Port 296h: Data port. The register structure is showed as the Figure 1.
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
Configuration Register 40h SMI# Status/Mask Registers 41h, 42h, 44h, 45h VID<3:0>/Fan Divisor Register 47h Serial Bus Address 48h Monitor Value Registers 20h~3Fh and 60h~7Fh (auto-increment) VID<4>/Device ID 49h Temperature 2, 3 Serial Bus Address 4Ah Control Register 4Bh~4Dh Select Bank for 50h~5Fh Reg. 4Eh Winbond Vendor ID 4Fh BANK 0 R-T Table Value BEEP Control Register Winbond Test Register 50h~58h
ISA Data Bus
ISA Address Bus
Port 5h
Index Register
Port 6h Data Register
BANK 1 Temperature 2 Control/Staus Registers 50h~56h BANK 2 Temperature 3 Control/Staus Registers 50h~56h BANK 4 Additional Control/Staus Registers 50h~5Ch BANK 5 Additional Limit Value & Value RAM 50h~57h
Figure 1. ISA interface access diagram
-8-
Preliminary W83782D
6.2.2 I2C interface The second interface uses I2C Serial Bus. In the W83782D has three serial bus address. That is, the first address defined at CR[48h] can read/write all registers excluding Bank 1 and Bank 2 temperature sensor 2/3 registers. The second address defined at CR[4Ah] bit2-0 only read/write temperature sensor 2 registers, and the third address defined at CR[4Ah] bit6-4 only can access (read/write) temperature sensor 3 registers. The first serial bus address of W83782D has 3 hardware setting bits set by pin47-45 when pin 43 is set to high. The address is 00101[pin45][pin46][pin47]. If pin45=1, pin46=1, pin47=0, for example, the content of CR[48h] is 00101110. If CR[4Ah] bit 2-0 is XXX , the temperature sensor 2 serial address is 1001XXXG, in which G is the read/write bit. If CR[4Ah] bit 6-4 is YYY , the temperature sensor 3 serial address is 1001YYYG, in which G is the read/write bit.
6.2.3 The first serial bus access timing are shown as follow: (a) Serial bus write to internal address register followed by the data byte
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 781D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 781D
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
7 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0
8
Ack by 781D
Stop by Master
Frame 3 Data Byte
Figure 2. Serial Bus Write to Internal Address Register followed by the Data Byte
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
(b) Serial bus write to internal address register only
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 781D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 781D Stop by Master
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
Figure 3. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 781D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by Master Stop by Master
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
Figure 4. Serial Bus Write to Internal Address Register Only
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Preliminary W83782D
6.2.4 The serial bus timing of the temperature 2 and 3 is shown as follow: (a) Typical 2-byte read from preset pointer location (Temp, TOS, THYST)
0 SCL SDA
Start By Master
7
8
0
0
1
0
1
1
0
1
R/W
Ack by 782D
D7
... ...
7
8
0
D1
D0
Ack by Master
D7
... ...
7
D1
D0
Ack by Master Stop by Master
Frame 1 Serial Bus Address Byte
Frame 2 MSB Data Byte
Frame 3 LSB Data Byte
Figure 5. Typical 2-Byte Read From Preset Pointer Location
(b) Typical pointer set followed by immediate read for 2-byte register (Temp, TOS, THYST)
0 SCL SDA
Start By Master
7
8
0
4
1
0
0
1
A2
A1
A0
R/W
Ack by 782D
0
0
0
0
0
0
D1
D0
Ack by 782D
Frame 1 Serial Bus Address Byte
Frame 2 Pointer Byte
0 SCL SDA
Start By Master
7
8
0
1
0
0
1
A2
A1
A0
R/W
Ack by 782D
D7
... ...
7
8
0
D1
D0
Ack by Master
D7
... ...
7
D1
D0
No Ack by Master Stop by Master
Frame 3 Serial Bus Address Byte 0
Frame 4 MSB Data Byte
Frame 5 LSB Data Byte
Figure 6. Typical Pointer Set Followed by Immediate Read for 2-Byte Register
(c) Typical read 1-byte from configuration register with preset pointer
0 SCL SDA
Start By Master
7
8
0
7
8
1
0
0
1
A2
A1
A0
R/W
Ack by 782D
D7
D6
D5
D4
D3
D2
D1
D0
No Ack by Master Stop by Master
Frame 1 Serial Bus Address Byte
Frame 2 Data Byte
Figure 7. Typical 1-Byte Read From Configuration With Preset Pointer
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
(d) Typical pointer set followed by immediate read from configuration register
0 SCL SDA
Start By Master
7
8
0
4
7
8 ...
1
0
0
1
A2
A1
A0
R/W
Ack by 782D
0
0
0
0
0
0
D1
D0
Ack by 782D
...
Frame 1 Serial Bus Address Byte
Frame 2 Pointer Byte
0 SCL (Cont..) SDA (Cont..)
Repea Start By Master
7
8
0
7
8
1
0
0
1
A2
A1
A0
R/W
Ack by 782D
D7
D6
D5
D4
D3
D2
D1
D0
No Ack by Master Stop by Master
Frame 3 Serial Bus Address Byte
Frame 4 MSB Data Byte
Figure 8. Typical Pointor Set Followed by Immediate Read from Temp 2/3 Configuration Register
(e) Temperature 2/3 configuration register Write
0 SCL SDA
Start By Master
7
8
0
4
7
8
1
0
0
1
A2
A1
A0
R/W
0
Ack by 782D
0
0
0
0
0
0
D1
D0
Ack by 782D
Frame 1 Serial Bus Address Byte
Frame 2 Pointer Byte
0 SCL (Cont...) SDA (Cont...) 0 0 0 D4 D3 D2 D1
7
8
D0
Ack by 782D Stop by Master
Frame 3 Configuration Data Byte
Figure 9. Configuration Register Write
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Preliminary W83782D
(f)
Temperature 2/3 TOS and THYST write
0 SCL SDA
Start By Master
7
8
0
4
7
8
1
0
0
1
A2
A1
A0
R/W
Ack by 782D
0
0
0
0
0
0
D1
D0
Ack by 782D
Frame 1 Serial Bus Address Byte
Frame 2 Pointer Byte
0 SCL (Cont...) SDA (Cont...) D7 D6 D5 D4 D3 D2 D1
7
8
0
7
8
D0
Ack by 781D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 782D Stop by Master
Frame 3 MSB Data Byte
Frame 4 LSB Data Byte
Figure 10. Configuration Register Write
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
6.3 Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage ,+3.3V and battery voltage can directly connected to these analog inputs. The 5VSB and +12V inputs should be reduced a factor with external resistors so as to obtain the input range. As Figure 11 shows.
+2.5VINA Positive Inputs +2.5VINB +3.3VIN VDD(+5V) VBAT R1 V1 R2 R4 12VIN R3 V2 Positive Input 5VSB
Pin 36 Pin 35 Pin 34 Pin 33 Pin 30 Pin 32 Pin 29 8-bit ADC with 16mV LSB
R5 V3 Negative Input V4 R7
N12VIN N5VIN
Pin 31 Pin 28
R8 R 10K, 1%
R6
VREF VTIN3 Pin 38 Pin 39 Pin 40
Pin 37
Typical Thermister Connection R THM 10K, 25 C
VTIN2 VTIN1
**The Connections of VTIN1 and VTIN2 are same as VTIN3
Figure 11.
- 14 -
Preliminary W83782D
6.3.1 Monitor over 4.096V voltage: The input voltage +12VIN can be expressed as following equation.
12VIN = V1 x
R2 R1 + R 2
The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of +12VIN can be subject to less than 4.096V for the maximun input range of the 8-bit ADC. Similarly, the node voltage of 5VSB (measure standby power VSB for ATX power supply) also can be evaluated by using two series resistors R3 and R4 which real value can be 5.1K ohms and 7.5K ohms so as to obtain the 5VSB is limited to less than 4.096V. The Pin 33 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83782D and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The value of two serial resistors are 34K ohms and 50K ohms so that input voltage to ADC is 2.98V which is less than 4.096V of ADC maximum input voltage. The express equation can represent as follows.
Vin = V C C x
50 K 50 K + 34 K
2 .98V
where VCC is set to 5V.
6.3.2 Monitor negative voltage: The negative voltage should be connected two series resistors and a positive voltage VREF (is equal to 3.6V). In the Figure 11, the voltage V3 and V4 are two negative voltage which they are -12V and 5V respectively. The voltage V3 is connected to two serial resistors then is connected to another terminal VREF which is positive voltage. So as that the voltage node N12VIN can be obtain a posedge voltage if the scales of the two serial resirtors are carefully selected. It is recommanded from Winbond that the scale of two serial resistors are R5=232K ohms and R6=56K ohm. the The input voltage of node -12VIN can be calculated by following equation.
N 12 VIN = ( VREF + V5 ) x (
232 K 232 K + 56 K
) + V5
where VREF is equal 3.6V. If the V5 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is set to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real negative votage and the express equation is shown as follows.
V5 =
N 12 VIN - VREF x 1-
Publication Release Date: April 1999 Revision A1
- 15 -
Preliminary W83782D
Where is 232K/(232K+56K). If the N2VIN is 0.567 then the V5 is approximately equal to -12V. The another negative voltage input V6 (approximate -5V) also can be evaluated by the similar method and the serial resistors can be selected with R7=120K ohms and R8=56K ohms by the Winbond recommended. The expression equation of V6 With -5V voltage is shown as follows.
V6 =
N 5 VIN - VREF x 1 -
Where the is set to 120K/(120K+56K). If the monitored ADC value in the N5VIN channel is 0.8635, VREF=3.6V and the parameter is 0.6818 then the negative voltage of V6 can be evalated to be 5V.
6.3.3 Monitor temperature from thermistor: The W83782D can connect three thermistors to measure three different envirment temperature. The specification of thermistor should be considered to (1) value is 3435K, (2) resistor value is 10K ohms at 25C. In the Figure 11, the themistor is connected by a serial resistor with 10K Ohms, then connect to VREF (Pin 37).
6.3.4 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904 The W83782D can alternate the thermistor to Pentium IITM (Deschutes) thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 12. The pin of Pentium IITM D- is connected to power supply ground (GND) and the pin D+ is connected to pin PIITDx in the W83782D. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied togeter to act as a thermal diode.
- 16 -
Preliminary W83782D
VREF R=30K, 1% Bipolar Transistor Temperature Sensor PIITDx C=3300pF B C 2N3904 E R=30K, 1%
W83782D
OR
Pentium II CPU Therminal Diode DD+ PIITDx C=3300pF
Figure 12.
6.4 FAN Speed Count and FAN Speed Control
6.4.1 Fan speed count Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure 13. Determine the fan counter according to: Count = 135 x 10 6 . RPM x Divisor
In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan speed can be evaluated by the following equation.
RPM =
1.35 x 10
6
Count x Divisor
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, PRM, and count.
Divisor 1 2 (default) 4 8 16 32 64 128
Nominal PRM 8800 4400 2200 1100 550 275 137 68
Time per Revolution 6.82 ms 13.64 ms 27.27 ms 54.54 ms 109.08 ms 218.16 ms 436.32 ms 872.64 ms Table 1.
Counts 153 153 153 153 153 153 153 153
70% RPM 6160 3080 1540 770 385 192 96 48
Time for 70% 9.74 ms 19.48 ms 38.96 ms 77.92 ms 155.84 ms 311.68 ms 623.36 ms 1246.72 ms
- 18 -
Preliminary W83782D
+12V
+5V
+12V
Pull-up resister 4.7K Ohms
Pull-up resister 4.7K Ohms
+12V FAN Out GND Fan Input Pin 18/19/20
+12V 14K~39K FAN Out GND Fan Input Pin 18/19/20
FAN Connector
W83782D
FAN Connector
10K
W83782D
Figure 13-1. Fan with Tach Pull-Up to +5V
Figure 13-2. Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator
+12V
+12V
Pull-up resister > 1K +12V FAN Out GND Fan Input Pin 18/19/20 3.9V Zener +12V
Pull-up resister < 1K or totem-pole output
> 1K FAN Out GND 3.9V Zener Fan Input Pin 18/19/20
FAN Connector
W83782D
FAN Connector Figure 13-4. Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp
W83782D
Figure 13-3. Fan with Tach Pull-Up to +12V and Zener Clamp
6.4.2 Fan speed control The W83782D provides four sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 CR5A, CR5B, CR5E, and CR5F. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows.
Duty - cycle (% ) =
Programmed 8 - bit Register Value 255
x 100%
The PWM clock frequency also can be program and defined in the Bank0.CR5C and Bank4.CR5C. The application circuit is shown as follows.
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
+12V
R1 R2 D G PWM Clock Input NMOS S + C FAN PNP Transistor
Figure 14.
6.5 Temperature Measurement Machine
The temperature data format is 8-bit two's-complement for sensor 1 and 9-bit two's-complement for sensor 2/3. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1/2 CR[50h] and the LSB from the Bank1/2 CR[51h] bit 7. The format of the temperature data is show in Table 1.
Temperature
8-Bit Digital Output 8-Bit Binary 8-Bit Hex 7Dh 19h 01h 00h FFh E7h C9h Table 2.
9-Bit Digital Output 9-Bit Binary 0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010 9-Bit Hex 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h
+125oC +25oC +1oC +0.5oC +0oC -0.5oC -1oC -25oC -55oC
0111,1101 0001,1001 0000,0001 0000,0000 1111,1111 1110,0111 1100,1001
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Preliminary W83782D
6.5.1 The W83782D temperature sensor 1 SMI# interrupt has two modes: (1) Comparator Interrupt Mode Setting the THYST (Temperature Hysteresis) limit to 127oC will set temperature sensor 1 SMI# to the Comparator Interrupt Mode. Temperature exceeds TO (Over Temperature) Limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the TO , the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below TO. (Figure 16-1 ) (2) Two-Times Interrupt Mode Setting the THYST lower than TO will set temperature sensor 1 SMI# to the Two-Times Interrupt Mode. Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 15-2 )
T HYST 127'C
T OI
T OI
T HYST
SMI#
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 15-1. Comparator Interrupt Mode
Figure 15-2. Two-Times Interrupt Mode
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Publication Release Date: April 1999 Revision A1
Preliminary W83782D
6.5.2 The W83782D temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. (1) Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. ( Figure 16-1 ) (2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 16-2 )
T OI
T OI
T HYST
T HYST
SMI#
*
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 16-1. Comparator Interrupt Mode
Figure 16-2. Two-Times Interrupt Mode
- 22 -
Preliminary W83782D
6.5.3 The W83782D temperature sensor 2 and 3 Over-Temperature (OVT#) has two modes, and they are programmed at Bank1 and Bank2 CR[52h] bit1 . These two bits needs to be programmed the same value. (1) Comparator Mode : Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. ( Figure 17) (2) Interrupt Mode: Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. Temperature exceeding TO , then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor2 or sensor 3 registers. Once the OVT# is activated by exceeding TO , then reset, if the temperature remains above THYST , the OVT# will not be activated again.( Figure 17)
To
T HYST
OVT#
(Comparator Mode; default)
OVT#
(Interrupt Mode)
*
*
*
*
*Interrupt Reset when Temperature 2/3 is read
Figure 17. Over-Temperature Response Diagram
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Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7. REGISTERS AND RAM
7.1 Address Register (Port x5h)
Data Port: Power on Default Value Attribute: Size: Port x5h 00h Bit 6:0 Read/write , Bit 7: Read Only 8 bits
7 6 5 4 3 2 1 0
Data
Bit7: Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another ISA bus transaction. With checking this bit, multiple ISA drivers can use W83782D without interfering with each other or a Serial Bus driver. It is the user's responsibility not to have a Serial Bus and ISA bus operations at the same time. This bit is: Set: with a write to Port x5h or when a Serial Bus transaction is in progress. Reset: with a write or read from Port x6h if it is set by a write to Port x5h, or when the Serial Bus transaction is finished. Bit 6-0: Read/Write
Bit 7 Busy (Power On default 0)
Bit 6 A6
Bit 5 A5
Bit 4 A4
Bit 3 A3
Bit 2 A2
Bit 1 A1
Bit 0 A0
Address Pointer (Power On default 00h)
- 24 -
Priliminary W83782D
Address Pointer Index (A6-A0)
Registers and RAM Configuration Register Interrupt Status Register 1 A6-A0 in Hex 40h 41h Power On Value of Registers: in Binary 00001000 00000000 Auto-increment to the address of Interrupt Status Register 2 after a read or write to Port x6h. Notes
Interrupt Status Register 2 SMI#Y Mask Register 1 SMIY Mask Register 2 NMI Mask Register 1 NMI Mask Register 2 VID/Fan Divisor Register
42h 43h 44h 45h 46h 47h
00000000 00000000 00000000 00000000 01000000 <7:4> = 0101; <3:0> = VID3-ID0 Auto-increment to the address of NMI Mask Register 2 after a read or write to Port x6h Auto-increment to the address of SMIY Mask Register 2 after a read or write to Port x6h.
Serial Bus Address Register POST RAM Value RAM Value RAM
48h 00-1Fh 20-3Fh 60-7Fh
<6:0> = 0101101; <7> = 0 Auto-increment to the next location after a read or write to Port x6h and stop at 1Fh.
Auto-increment to the next location after a read or write to Port x6h and stop at 7Fh.
7.2 Data Register (Port x6h)
Data Port: Power on Default Value Attribute: Size: Port x6h 00h Read/write 8 bits
7 6 5 4 3 2 1 0
Data
Bit 7-0: Data to be read from or to be written to RAM and Register.
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Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7.3 Configuration Register Index 40h
Register Location: Power on Default Value Attribute: Size:
7 6 5
40h 00000001 binary Read/write 8 bits
4 3 2 1 0
START SMI#Enable RESERVED INT_Clear RESERVED RESERVED BEEP/GPO# INITIALIZATION
Bit 7: A one restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero. Bit 6: The logical 1 in this bit drives a zero on BEEP/GPO# pin. Bit 5: Reserved Bit 4: Reserved Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status The device will stop monitoring. It will resume upon clearing of this bit. Bit 2: Reserved Bit 1: A one enables the SMI# Interrupt output. Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode. Registers.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit.
7.4 Interrupt Status Register 1 Index 41h
Register Location: Power on Default Value Attribute: Size: 41h 00h Read Only 8 bits
- 26 -
Priliminary W83782D
7
6
5
4
3
2
1
0
VCOREA VINRO +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2
Bit 7: A one indicates the fan count limit of FAN2 has been exceeded. Bit 6: A one indicates the fan count limit of FAN1 has been exceeded. Bit 5: A one indicates a High limit of VTIN2 has been exceeded from temperature sensor 2. Bit 4: A one indicates a High limit of VTIN1 has been exceeded from temperature sensor 1. Bit 3: A one indicates a High or Low limit of +5VIN has been exceeded. Bit 2: A one indicates a High or Low limit of +3.3VIN has been exceeded. Bit 1: A one indicates a High or Low limit of VINR0 has been exceeded. Bit 0: A one indicates a High or Low limit of VCOREA has been exceeded.
7.5 Interrupt Status Register 2 Index 42h
Register Location: Power on Default Value Attribute: Size:
7 6
42h 00h Read Only 8 bits
5 4 3 2 1 0
+12VIN -12VIN -5VIN FAN3 Chassis Intrusion Temp3 Reserved Reserved
Bit 7-6:Reserved.This bit should be set to 0. Bit 5: A one indicates a High limit of VTIN3 has been exceeded from temperature sensor 3.
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Publication Release Date: April 1999 Revision A1
Priliminary W83782D
Bit 4: A one indicates Chassis Intrusion has gone high. Bit 3: A one indicates the fan count limit of FAN3 has been exceeded. Bit 2: A one indicates a High or Low limit of -5VIN has been exceeded. Bit1: A one indicates a High or Low limit of -12VIN has been exceeded. Bit0: A one indicates a High or Low limit of +12VIN has been exceeded.
7.6 SMI# Mask Register 1 Index 43h
Register Location: Power on Default Value Attribute: Size:
7
43h 00h Read/Write 8 bits
6 5 4 3 2 1 0
VCOREA VINRO +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2
Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt.
7.7 SMI# Mask Register 2 Index 44h
Register Location: Power on Default Value Attribute: Size: 44h 00h Read/Write 8 bits
- 28 -
Priliminary W83782D
7
6
5
4
3
2
1
0
+12VIN -12VIN -5VIN FAN3 Chassis Intrusion TEMP3 Reserved Reserved
Bit 7-6: Reserved. This bit should be set to 0. Bit 5-0: A one disables the corresponding interrupt status bit for SMI interrupt.
7.8 Reserved Register Index 45h 7.9 Chassis Clear Register -- Index 46h
Register Location: Power on Default Value Attribute: Size:
7 6
46h <7:0> = 00000000 binary Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear
Bit 7: Set 1 , clear Chassis Intrusion event. This bit self clears after clearing Chassis Intrusion event. Bit 6-0:Reserved. This bit should be set to 0.
7.10 VID/Fan Divisor Register Index 47h
Register Location: Attribute: Size: 47h Read/Write 8 bits Power on Default Value <7:4> is 0101, <3:0> is mapped to VID<3:0>
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Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7
6
5
4
3
2
1
0
VID0 VID1 VID2 VID3 FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1
Bit 7-6: FAN2 Speed Control. Bit 5-4: FAN1 Speed Control. Bit 3-0: The VID <3:0> inputs
Note : Please refer to Bank0 CR[5Dh] , Fan divisor table.
7.11 Serial Bus Address Register Index 48h
Register Location: Power on Default Value Serial Bus address Size:
7 6 5 4 3 2
48h <6:0> = 0101101 and <7> = 0 binary 8 bits
1 0
Serial Bus Address
Reserved
Bit 7: Read Only - Reserved. Bit 6-0: Read/Write - Serial Bus address <6:0>.
- 30 -
Priliminary W83782D
7.12 Value RAM Index 20h- 3Fh or 60h - 7Fh (auto-increment)
Address A6-A0 20h 21h 22h 23h 24h 25h 26h 27h 28h Address A6-A0 with Auto-Increment 60h 61h 62h 63h 64h 65h 66h 67h 68h VCOREA reading VINR0 reading +3.3VIN reading +5VIN reading +12VIN reading -12VIN reading -5VIN reading Temperature reading FAN1 reading Note: This location stores the number of counts of the internal clock per revolution. 29h 69h FAN2 reading Note: This location stores the number of counts of the internal clock per revolution. 2Ah 6Ah FAN3 reading Note: This location stores the number of counts of the internal clock per revolution. 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h VCOREA High Limit, default value is defined by Vcore Voltage +0.2v. VCOREA Low Limit, default value is defined by Vcore Voltage -0.2v. VINR0 High Limit. VINR0 Low Limit. +3.3VIN High Limit +3.3VIN Low Limit +5VIN High Limit +5VIN Low Limit Description
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Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7.12 Value RAM Index 20h- 3Fh or 60h - 7Fh (auto-increment), continued Address A6-A0 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh Address A6-A0 with Auto-Increment 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh +12VIN High Limit +12VIN Low Limit -12VIN High Limit -12VIN Low Limit -5VIN High Limit -5VIN Low Limit Temperature sensor 1 (VTIN1) High Limit Temperature sensor 1 (VTIN1) Hysteresis Limit FAN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Ch 7Ch FAN2 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Dh 7Dh FAN3 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 3E- 3Fh 7E- 7Fh Reserved Description
Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits.
- 32 -
Priliminary W83782D
7.13 Voltage ID (VID4) & Device ID -- Index 49h
Register Location: Power on Default Value Size:
7
49h <7:1> is 000,0001b <0> is mapped to VID <4> 8 bits
6 5 4 3 2 1 0
VID4
DID<6:0>
Bit 7-1: Read Only - Device ID<6:0> Bit 0 : Read/Write - The VID4 inputs.
7.14 Temperature 2 and Temperature 3 Serial Bus Address Register--Index 4Ah
Register Location: Power on Default Value Attribute: Size:
7 6
4Ah <7:0> = 0000,0001 binary. Reset by MR Read/Write 8 bits
5 4 3 2 1 0
I2CADDR2 I2CADDR2 I2CADDR2 DIS_T2 I2CADDR3 I2CADDR3 I2CADDR3 DIS_T3
Bit 7: Set to 1, disable temperature sensor 3 and can not access any data from Temperature Sensor 3. Bit 6-4: Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. Publication Release Date: April 1999 Revision A1
- 33 -
Priliminary W83782D
Bit 3: Set to 1, disable temperature Sensor 2 and can not access any data from Temperature Sensor 2. Bit 2-0: Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits.
7.15 Pin Control Register -- Index4Bh
Register Location: Power on Default Value Attribute: Size:
7 6
4Bh <7:0> 44h. Reset by MR. Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved CLKINSEL CLKINSEL ADCOVSEL ADCOVSEL FAN3DIV_B0 FAN3DIV_B1
Bit 7-6:Fan3 speed divisor. Please refer to Bank0 CR[5Dh] , Fan divisor table. Bit 5-4: Select A/D Converter Clock Input. <5:4> = 00 - default. ADC clock select 22.5 Khz. <5:4> = 01- ADC clock select 5.6 Khz. (22.5K/4) <5:4> = 10 - ADC clock select 1.4Khz. (22.5K/16) <5:4> = 11 - ADC clock select 0.35 Khz. (22.5K/64) Bit 3-2: Clock Input Select. <3:2> = 00 - Pin 3 (CLKIN) select 14.318M Hz clock. <3:2> = 01 - Default. Pin 3 (CLKIN) select 24M Hz clock. <3:2> = 10 - Pin 3 (CLKIN) select 48M Hz clock . <3:2> = 11 - Reserved. Pin3 no clock input. Bit 1-0: Reserved. User defined.
- 34 -
Priliminary W83782D
7.16 IRQ#/OVT# Property Select -- Index 4Ch
Register Location: Power on Default Value Attribute: Size:
7 6
4Ch <7:0> --0000,0001. Reset by MR. Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved OVTPOL DIS_OVT1 DIS_OVT2 Reserved T23_INTMode Reserved
Bit 7: Reserved. User Defined. Bit6: Set to 1, the SMI# output type of Temperature 2 and 3 is set to Comparator Interrupt mode. Set to 0, the SMI# output type is set to Two-Times Interrupt mode. (default 0) Bit5: Reserved. User Defined. Bit 4: Disable temperature sensor 3 over-temperature (OVT) output if set to 1. Default 0, enable OVT2 output through pin OVT#. Bit 3: Disable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, enable OVT1 output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: Reserved. User Defined. Bit 0: Reserved. User Defined.
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Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7.17 FAN IN/OUT and BEEP/GPO# Control Register -- Index 4Dh
Register Location: Power on Default Value Attribute: Size:
7 6
4Dh <7:0> 0001,0101. Reset by MR. Read/Write 8 bits
5 4 3 2 1 0
FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 GPOSEL DIS_ABN
Bit 7: Disable power-on abnormal the monitor voltage including V-Core A and +3.3V. If these voltage exceed the limit value, the pin (Open Drain) of BEEP will drives 300Hz and 600Hz frequency signal. Write 1, the frequency will be disable. Default 0. After power on, the system should set 1 to this bit to 1 in order to disable BEEP. Bit 6: BEEP/GPO# Pin Function Select. Write 1 Select GPO# function. Set 0, select BEEP function. This bit default 0. Bit 5: FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generate logic high signal. Write 0, pin 18 always generates logic low signal. This bit default 0. Bit 4: FAN 3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0, this pin 18 acts as FAN control signal and the output value of FAN control is set by this register bit 5. This output pin can connect to power PMOS gate to control FAN ON/OFF. Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 19 always generate logic high signal. Write 0, pin 19 always generates logic low signal. This bit default 0. Bit 2: FAN 2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0, this pin 19 acts as FAN control signal and the output value of FAN control is set by this register bit 3. This output pin can connect to power NMOS gate to control FAN ON/OFF. Bit 1: FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 20 always generate logic high signal. Write 0, pin 20 always generates logic low signal. This bit default 0. Bit 0: FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0, this pin 20 acts as FAN control signal and the output value of FAN control is set by this register t 1. This output pin can connect to power PMOS gate to control FAN ON/OFF.
- 36 -
Priliminary W83782D
7.18 Register 50h ~ 5Fh Bank Select -- Index 4Eh
Register Location: Power on Default Value Attribute: Size:
7 6
4Eh <6:3> = Reserved, <7> = 1, <2:0> = 0. Reset by MR Read/Write 8 bits
5 4 3 2 1 0
BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS
Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select.
7.19 Winbond Vendor ID -- Index 4Fh
Register Location: Power on Default Value Attribute: Size:
15
4Fh <15:0> = 5CA3h Read Only 16 bits
8 7 0
VIDH
VIDL
Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h.
- 37 -
Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7.20 Winbond Test Register -- Index 50h - 55h (Bank 0)
7.21 BEEP Control Register 1-- Index 56h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
56h <7:0> 0000,0000. Reset by MR. Read/Write 8 bits
5 4 3 2 1 0
EN_VCA_BP EN_Vr0_BP EN_V33_BP EN_V5_BP EN_T1_BP EN_T2_BP EN_FAN1_BP EN_FAN2_BP
Bit 7: Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value. Bit 6: Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value. Bit 5: Enable BEEP Output from Temperature Sensor 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 4: Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 3: Enable BEEP output from VDD (+5V), Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 2: Enable BEEP output from +3.3V. Write 1, enable BEEP output, which is default value. Bit 1: Enable BEEP output from VINR0. Write 1, enable BEEP output, which is default value. Bit 0: Enable BEEP Output from VCOREA if the monitor value exceed the limits value. Write 1, enable BEEP output, which is default value
- 38 -
Priliminary W83782D
7.22 BEEP Control Register 2-- Index 57h (Bank 0)
Register Location: Attribute: Size: 8 bits
7 6 5 4 3 2 1 0
57h Read/Write
Power on Default Value <7:0> 1000-0000. Reset by MR.
EN_V12_BP EN_NV12_BP EN_NV5_BP EN_FAN3_BP EN_CASO_BP EN_T3_BP Reserved EN_GBP
Bit 7: Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output. Bit 6: Reserved. This bit should be set to 0. Bit 5: Enable BEEP Output from Temperature Sensor 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 4: Enable BEEP output for case open if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0. Bit 3: Enable BEEP Output from FAN 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0. Bit 2: Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 1: Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output.
7.23 Chip ID -- Index 58h (Bank 0)
Register Location: Power on Default Value Attribute: Size: 58h <7:0> 0011-0000. Reset by MR. Read Only 8 bits
- 39 -
Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7
6
5
4
3
2
1
0
CHIPID
Bit 7: Winbond Chip ID number. Read this register will return 30h.
7.24 Diode Selection Register -- Index 59h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
59h <7>=0 and <6:4> = 111 and <3:0> = 0000 Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 SELPIIV3 Reserved
Bit 7: Reserved Bit 6: Temperature sensor diode 3. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904
Bipolar mode.
Bit 5: Temperature sensor diode 2. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904
Bipolar mode.
Bit 4: Temperature sensor diode 1. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904
Bipolar mode.
Bit 3-0: Reserved
- 40 -
Priliminary W83782D
7.25 PWMOUT2 Control -- Index 5Ah (Bank 0)
Register Location: Power on default value: Attribute: Size:
7 6
5Ah <7:0> 1111-1111. Reset by MR. Read/Write 8 bits
5 4 3 2 1 0
PWM2_DUTY
Bit 7: PWMOUT2 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.
- 40-A -
Priliminary W83782D
7.26 PWMOUT1 Control -- Index 5Bh (Bank 0)
Register Location: Power on default value: Attribute: Size:
7 6
5Bh <7:0> 1111-1111. Reset by MR. Read/Write 8 bits
5 4 3 2 1 0
PWM1_DUTY
Bit 7: PWMOUT1 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.
7.27 PWMOUT1/2 Clock Select -- Index 5Ch (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
5Ch <7:0> 0001-0001. Reset by MR. Read/Write 8 bits
5 4 3 2 1 0
PWM2CLKSEL PWM2CLKSEL PWM2CLKSEL EN_FANPWM2 PWM1CLKSEL PWM1CLKSEL PWM1CLKSEL Reserved
Bit 7: Reserved Bit 6-4: PWMOUT1 clock selection. The clock defined frequency is same as PWMOUT2 clock selection. Publication Release Date: April 1999 Revision A1
-41 -
Priliminary W83782D
Bit 3: Set to 1. Enable PWMOUT2 PWM Control Bit 2-0: PWMOUT2 clock Selection. <2:0> = 000: 46.87K Hz <2:0> = 001: 23.43K Hz (Default) <2:0> = 010: 11.72K Hz <2:0> = 011: 5.85K Hz <2:0> = 100: 2.93K Hz
7.28 VBAT Monitor Control Register -- Index 5Dh (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
5Dh <7:0> 0000-0000. Reset by MR. Read/Write 8 bits
5 4 3 2 1 0
EN_VBAT_MNT DIODES1 DIODES2 DIODES3 RESERVE FANDIV1_B2 FANDIV2_B2 FANDIV3_B2
Bit 7: Fan3 divisor Bit 2. Bit 6: Fan2 divisor Bit 2. Bit 5: Fan1 divisor Bit 2. Bit 4: Reserve. Bit 3: Temperature sensor 3 select into thermal diode such as Pentium II CPU supported. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 2: Sensor 2 type selection. Defined as DIODES3 described in the bit 3. Bit 1: Sensor 1 type selection. Defined as DIODES2 described in the bit 3. Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at least 300ms for W83782D.
- 42 -
Priliminary W83782D
Fan divisor table :
Bit 2 0 0 0 0 Bit 1 0 0 1 1 Bit 0 0 1 0 1 Fan Divisor 1 2 4 8 Bit 2 1 1 1 1 Bit 1 0 0 1 1 Bit 0 0 1 0 1 Fan Divisor 16 32 64 128
7.29 PWMOUT3 Control -- Index 5Eh (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
5Eh <7:0> 1111-1111. Reset by MR. Read/Write 8 bits
5 4 3 2 1 0
PWM3_DUTY
Bit 7: PWMOUT3 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.
7.30 PWMOUT4 Control -- Index 5Fh (Bank 0)
Register Location: Power on Default Value Attribute: Size: 5Fh <7:0> 1111-1111. Reset by MR. Read Only 8 bits
-43 -
Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7
6
5
4
3
2
1
0
PWM4_DUTY
Bit 7: PWMOUT4 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.
7.31 Temperature Sensor 2 Temperature (High Byte) Register - Index 50h (Bank 1)
Register Location: Attribute: Size: 50h Read Only 8 bits
7 6 5 4 3 2 1 0
TEMP2<8:1>
Bit 7: Temperature <8:1> of sensor 2, which is high byte.
7.32 Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h (Bank 1)
Register Location: Attribute: Size: 51h Read Only 8 bits
- 44 -
Priliminary W83782D
7
6
5
4
3
2
1
0
Reserved
TEMP2<0>
Bit 7: Temperature <0> of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0.
7.33 Temperature Sensor 2 Configuration Register - index 52h (Bank 1)
Register Location: Power on Default Value Size:
7 6
52h <7:0> = 0x00 8 bits
5 4 3 2 1 0
STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved
Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# Interrupt mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor.
-45 -
Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7.34 Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1)
Register Location: Power on Default Value Attribute: Size:
7 6
53h <7:0> = 0x4B Read/Write 8 bits
5 4 3 2 1 0
THYST2<8:1>
Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
7.35 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h (Bank 1)
Register Location: Power on Default Value Attribute: Size:
7
54h <7:0> = 0x0 Read Only 8 bits
6 5 4 3 2 1 0
Reserved
THYST2<0>
Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0.
- 46 -
Priliminary W83782D
7.36 Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h (Bank 1)
Register Location: Power on Default Value Attribute: Size:
7 6
55h <7:0> = 0x50 Read/Write 8 bits
5 4 3 2 1 0
TOVF2<8:1>
Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
7.37 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h(Bank 1)
Register Location: Power on Default Value Size:
7
56h <7:0> = 0x0 8 bits
6 5 4 3 2 1 0
Reserved
TOVF2<0>
Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set to 0.
-47 -
Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7.38 Temperature Sensor 3 Temperature (High Byte) Register - Index 50h (Bank 2)
Register Location: Attribute: Size: 50h Read Only 8 bits
7 6 5 4 3 2 1 0
TEMP2<8:1>
Bit 7-0: Temperature <8:1> of sensor 2, which is high byte.
7.39 Temperature Sensor 3 Temperature (Low Byte) Register - Index 51h (Bank 2)
Register Location: Attribute: Size: 51h Read Only 8 bits
7 6 5 4 3 2 1 0
Reserved
TEMP2<0>
Bit 7: Temperature <0> of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0.
7.40 Temperature Sensor 3 Configuration Register - Index 52h (Bank 2)
Register Location: Power on Default Value Size: 52h <7:0> = 0x00 8 bits
- 48 -
Priliminary W83782D
7
6
5
4
3
2
1
0
STOP3 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved
Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# Interrupt Mode select. This bit default is set to 0, which is Compared Mode. When set to 1, Interrupt Mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor.
7.41 Temperature Sensor 3 Hysteresis (High Byte) Register - Index 53h (Bank 2)
Register Location: Power on Default Value Attribute: Size:
7 6
53h <7:0> = 0x4B Read/Write 8 bits
5 4 3 2 1 0
THYST3<8:1>
Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
7.42 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index 54h (Bank 2)
Register Location: Power on Default Value Attribute: Size: 54h <7:0> = 0x0 Read Only 8 bits
-49 -
Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7
6
5
4
3
2
1
0
Reserved
THYST3<0>
Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0.
7.43 Temperature Sensor 3 Over-temperature (High Byte) Register - Index 55h (Bank 2)
Register Location: Power on Default Value Attribute: Size:
7 6
55h <7:0> = 0x50 Read/Write 8 bits
5 4 3 2 1 0
TOVF3<8:1>
Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
7.44 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index 56h(Bank 2)
Register Location: Power on Default Value Size: 56h <7:0> = 0x0 8 bits
- 50 -
Priliminary W83782D
7
6
5
4
3
2
1
0
Reserved
TOVF3<0>
Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set to 0.
7.45 Interrupt Status Register 3 -- Index 50h (BANK4)
Register Location: Power on Default Value Attribute: Size:
7
50h <7:0> = 00h Read Only 8 bits
6 5 4 3 2 1 0
5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved
Bit 7-2: Reserved. Bit 1: A one indicates a High or Low limit of VBAT has been exceeded. Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded.
7.46 SMI# Mask Register 3 -- Index 51h (BANK 4)
Register Location: Power on Default Value Attribute: Size: 51h <7:0> = 0000,0000h Read/Write 8 bits
-51 -
Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7
6
5
4
3
2
1
0
5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved
Bit 7-2: Reserved. Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt.
7.47 BEEP Control Register 3-- Index 53h (Bank 4)
Register Location: Power on Default Value Attribute: Size:
7
53h <7:0> 0000,0000. Reset by MR. Read/Write 8 bits
6 5 4 3 2 1 0
EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved
Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. (Default 0) Bit 4-2: Reserved. Bit 1: Enable BEEP output from VBAT. Write 1, enable BEEP output, which is default value. Bit 0: Enable BEEP Output from 5VSB. Write 1, enable BEEP output, which is default value.
7.48 Reserved Register -- Index 54h--58h
- 52 -
Priliminary W83782D
7.49 Real Time Hardware Status Register I -- Index 59h (Bank 4)
Register Location: Power on Default Value Attribute: Size:
7 6
59h <7:0> 0000,0000. Reset by MR. Read Only 8 bits
5 4 3 2 1 0
VCOREA_STS VINR0_STS +3.3VIN_STS +5VIN_STS TEMP1_STS TEMP2_STS FAN1_STS FAN2_STS
Bit 7: FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 6: FAN 1 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 5: Temperature sensor 2 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 4: Temperature sensor 1 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 3: +5V Voltage Status. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V is in the limit range. Bit 2: +3.3V Voltage Status. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of +3.3V is in the limit range. Bit 1: VINR0 Voltage Status. Set 1, the voltage of VINR0 is over the limit value. Set 0, the voltage of VINR0 is in the limit range. Bit 0: VCOREA Voltage Status. Set 1, the voltage of VCORE A is over the limit value. Set 0, the voltage of VCORE A is in the limit range.
-53 -
Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7.50 Real Time Hardware Status Register II -- Index 5Ah (Bank 4)
Register Location: Power on Default Value Attribute: Size:
7 6
5Ah <7:0> 0000,0000. Reset by MR. Read Only 8 bits
5 4 3 2 1 0
+12VIN_STS -12VIN_STS -5VIN_STS FAN3_STS CASE_STS TEMP3_STS Reserved Reserved
Bit 7-6: Reserved Bit 5: Temperature sensor 3 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 4: Case Open Status. Set 1, the case open sensor is sensed the high value. Set 0 Bit 3: FAN3 Voltage Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is during the limit range. Bit 2: -5V Voltage Status. Set 1, the voltage of -5V is over the limit value. Set 0, the voltage of -5V is during the limit range. Bit 1: -12V Voltage Status. Set 1, the voltage of -12V is over the limit value. Set 0, the voltage of 12V is during the limit range. Bit 0: +12V Voltage Status. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of +12V is in the limit range.
7.51 Real Time Hardware Status Register III -- Index 5Bh (Bank 4)
Register Location: Power on Default Value Attribute: Size: 5Bh <7:0> = 0000,0000h Read Only 8 bits
- 54 -
Priliminary W83782D
7
6
5
4
3
2
1
0
5VSB_STS VBAT_STS Reserved Reserved Reserved Reserved Reserved Reserved
Bit 7-2: Reserved. Bit 1: VBAT Voltage Status. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of VBAT is during the limit range. Bit 0: 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of 5VSB is in the limit range.
7.52 PWMOUT3/4 Clock Select -- Index 5Ch (Bank 4)
Register Location: Power on Default Value Attribute: Size:
7
5Ch <7:0> 0001,0001. Reset by MR. Read/Write 8 bits
6 5 4 3 2 1 0
PWM3CLKSEL PWM3CLKSEL PWM3CLKSEL Reserved PWM4CLKSEL PWM4CLKSEL PWM4CLKSEL Reserved
Bit 7: Reserved. Bit 6-4: PWMOUT4 clock selection. The clock defined frequency is same as PWMOUT3 clock selection. Bit 3: Reserved. Bit 2-0: PWMOUT3 clock Selection. <2:0> = 000: 46.87K Hz <2:0> = 001: 23.43K Hz (Default) <2:0> = 010: 11.72K Hz <2:0> = 011: 5.85K Hz <2:0> = 100: 2.93K Hz
-55 -
Publication Release Date: April 1999 Revision A1
Priliminary W83782D
7.53 Value RAM 2 Index 50h - 5Ah (auto-increment) (BANK 5)
Address A6-A0 Auto-Increment 50h 51h 52h 53h 54h 55h 56h 57h 5VSB reading VBAT reading Reserved Reserved 5VSB High Limit 5VSB Low Limit. VBAT High Limit VBAT Low Limit Description
7.54 Winbond Test Register - Index 50h (Bank 6)
- 56 -
Preliminary W83782D
8. SPECIFICATIONS
8.1 Absolute Maximum Ratings
PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature RATING -0.5 to 7.0 -0.5 to VDD+0.5 0 to +70 -55 to +150 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
8.2 DC Characteristics
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V A A VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V
- 57 -
Publication Release Date: April 1999 Revision A1
Preliminary W83782D
8.2 DC Characteristics, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA
OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage VOL 0.4 V IOL = 8 mA OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 V IOL = 12 mA OD48 - Open-drain output pin with sink capability of 48 mA Output Low Voltage VOL 0.4 V IOL = 48 mA INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A 1.1 2.4 +10 -10 VIN = VDD VIN = 0 V
- TTL level Schmitt-triggered input pin VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage
- 58 -
Preliminary W83782D
8.3 AC Characteristics 8.3.1 ISA Read/Write Interface Timing
AEN SA[2:0],CS#
t AR t RD t RCU
IOR# IOW#
t RA
RC
SD[7:0]
t RVD
VALID DATA t RDH
IRQ
t RI ISA Bus Read Timing
AEN SA[2:0],CS#
t AW
VALID
t WR t WCU
VALID
IOW# IOR#
t WA
WC
SD[7:0]
VALID DATA t DS t DH
IRQ
t WI
ISA Bus Write Timing
- 59 -
Publication Release Date: April 1999 Revision A1
Preliminary W83782D
ISA Read/Write Timing PARAMETER Valid Address to Read Active Valid Address to Write Active Data Hold Data Setup Address Hold from Inactive Read Read Cycle Update Read Strobe Width Read Data Hold Read Strobe to Clear IRQ Active Read to Valid Data Address Hold from Inactive Write Write Cycle Update Write Strobe to Clear IRQ Write Strobe Width Read Cycle = tAR + tRD+tRCV Write Cycle = tAW+tWR - tWCV SYMBOL t-AR tAW tDH tDS tRA tRCU tRD tRDH tRI tRVD tWA tWCU tWI tWR RC WC 120 210 210 5 80 60 MIN. 10 10 5 80 40 200 120 40 60 115 MAX. UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
8.3.2 Serial Bus Timing Diagram
t
SCL
SCL
t HD;SDA
t t HD;DAT SU;STO
SDA IN
VALID DATA
t SU;DAT
SDA OUT
Serial Bus Timing Diagram
- 60 -
Preliminary W83782D
Serial Bus Timing PARAMETER SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time SYMBOL t SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF
-
MIN. 10 4.7 4.7 120 5
MAX.
UNIT uS uS uS nS nS
1.0 300
uS nS
9. HOW TO READ THE TOP MARKING
The top marking of W83782D
W83782D 825AA
Left: Winbond logo 1st line: Type number W83782D, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 825 A A 825: packages made in '98, week 25 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B
- 61 -
Publication Release Date: April 1999 Revision A1
Preliminary W83782D
10. PACKAGE DIMENTIONS
(48-pin QFP)
HD D
36 25
Dimension in inch
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Symbol
Min.
Nom.
Max.
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2
A
Seating Plane
See Detail F
A1 y
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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11. APPLICATION CIRCUIT OF WINBOND W83782D / 781D
VOLTAGE SENSING
R11 CPUVCOA GTLVOLT 3VCC 10K +12VIN +12V R3 28K 1% R R4 10K 1% R21 R GNDA VCC C3 CAP 10u C4 CAP 0.1u 3VIN VINR0 VCOREA 10K R1 10K R2 R R R VCOREA VINR0 3VIN L1 INDUCTOR FB
VID3 BEEP/GPO# GNDA -5VIN 5VSB/-5VOUT VBAT/-12VOUT -12VIN +12VIN
R18
R R27 60.4K 1%/781D R
R
-12V GNDA
56K 1%/782D
232K 1%/782D 210K 1%/781D -12VIN
U1 R25 0 /781D R RSTOUT#
25 26 27 28 29 30 31 32 33 34 35 36 VID3 BEEP/GPO# GNDA -5VIN 5VSB VBAT -12VIN +12VIN AVCC +3.3VIN VINR0 VCOREA
VBAT
R22 0 /782D
R
VBAT/-12VOUT
VREF R38 R R36 R GNDA VREF T3 T2 T1 VREF 37 38 39 40 41 42 43 44 45 46 47 48 VREF VTIN3/PIITD3 VTIN2/PIITD2 VTIN1/PIITD1 VID0 OVT# ADRMSEL SMI# SA2/IA2 SA1/IA1 SA0/IA0 CS#
5VSB
5.1K 1%/782D
7.5K 1%/782D R37 0/782D 60.4K 1%/781D R28 R -5VIN R20 R R 5VSB/-5VOUT
VID0 OVT# ADRMSEL SMI# A2 A1 A0
CS# -5V
VID2 PWMOUT1 SDA SCL FAN1IO FAN2IO FAN3IO/PWMOUT2 VID4 CASEOPEN# MR GNDD VCC VID1 D0/PWMOUT3 D1/PWMOUT4 D2 D3 D4 D5 D6 D7 CLKIN IOW# IOR#
24 23 22 21 20 19 18 17 16 15 14 13
VID2 SDA SCL
R26
R PWMOUT1
0 /782D FAN1IN FAN2IN VID4 GNDD VCC CASEOPEN# RESETDRV VCC
R29 0/782D R30 0/781D
R R
PWMOUT2 FAN3IN
R19
R 56K 1%/782D
120K 1%/782D 90.9K 1%/781D
C1 CAP 10u
C2 CAP 0.1u
W83782D
Beep Circuits
VCC R33 R 100 LS1
12 11 10 9 8 7 6 5 4 3 2 1
3VCC R9 R 4.7K TO PIIX4 R10 R 4.7K OVT# SMI# VID1
IOR# IOW# CLKIN
R34 R 10K/782D SD[0..7]
{
GNDA
THRM#
EXTSMI#
SPEAKER
L2 GNDA INDUCTOR FB Select one of the two setting. Set A2-A0 as 3 lowest order bits of ISA address bus ADRMSELIN SA2 SA1 SA0 A2 A1 A0 PIIVID4 PIIVID3 PIIVID2 PIIVID1 PIIVID0 GNDD R35 R R32 R 0/781D
CPU Voltage ID output
3VCC R31 R12 R 10K R13 R 10K R14 R 10K R15 R 10K R16 R 10K VID4 VID3 VID2 VID1 VID0 BEEP/GPO# R 510/782D
0/782D
Q1 NPN 3904/782D
3VCC Set A2-A0 as bit2, bit1, bit0 of 7 bit I2C address setting VCC IA2 IA1 IA0 ADRMSELIN A2 A1 A0 SDA SCL R5 R 0 R7 R 4.7K 0 SMDAT SMCLK R8 R 4.7K
R R6
ADRMSELIN
R23 0 /782D R24
R R Title ADRMSEL Size Custom Date: Document Number Thursday, July 23, 1998
Winbond Electronic Corp. W83781D-W83782D Application Circuit Rev 0.3 Sheet 1 of 2
IRQ
0 /781D
Temperature Sensing
PWM Circuit for FAN speed control
+12V R59 R Q7 PNP 3906/782D C9 + R61 0/782D R60 0/781DR D1 DIODE 1N4148 10K 1% (for system) 4.7K/782D R58 R 1K/782D Q6 47u/782D MOSFET N 2N7002/782D R45 R 4.7K R46 27K R R47 R 10K FAN1IN
R39 VREF
R
10K 1% R40 R
THERMISTOR RT2
T
RT3
R JP2 3 2 1 HEADER 3
T
10K 1%
(for cpu1) PWMOUT1 (for cpu2)
10K 1% R41 R
R54
R
THERMISTOR RT1
T
510/782D
10K 1%
10K 1% T1 T2 T3
THERMISTOR +12V R57 GNDA R Q5 PNP 3906/782D R62 0/781D R D2 DIODE 1N4148
4.7K/782D R56 R 1K/782D Q4 R55 R
Measuring temperature by either thermistor or diode.
R42 VREF 30K 1% T1 GNDA CAPACITOR R43 VREF T2 GNDA 30K 1% CAPACITOR R44 VREF T3 GNDA 30K 1% CAPACITOR C7 3300p R Q3 NPN 3904 DC6 3300p R C5 3300p Q2 NPN 3904 (for system) R PWMOUT2 510/782D
+ MOSFET N 2N7002/782D
C8 47u/782D
R63 0/782D
R
R48 R 4.7K R49 27K R R50 R 10K FAN2IN
JP1 3 2 1 HEADER 3
D+
(from PII CPU) +12V
D3 DIODE 1N4148 (for cpu2) JP3 3 2 1 HEADER 3
R51 R 4.7K R52 27K R R53 R 10K FAN3IN
Choosing the more accurate measuring method between the above is recommanded.
Case Open Circuits
R65 R 0/782D R17 R 10M/782D R64 R 0/782D S1 CASEOPEN SW R66 R 0/781D R67 R 2.2M/781D 74HC14 /781D 4 VBAT R68 R 0/781D C10 CAP 1000p /781D CASEOPEN# U2B 3 These two inverters consume VBAT 74HC14 /781D U2A 1 2
R69 R 10K/781D
R70 R CASEOPEN 0/781D
Winbond Electronic Corp. Title W83781D-W83782D Application Circuit Size Document Number Custom Date: Wednesday, July 22, 1998 Sheet 2 of 2 Rev 0.3
Rev.
Description
0.1 0.2 0.3
First published. Change CASEOPEN circuit for W83781D/782D co-layout. Change 2N3904 in Fan Speed Control circuit to 2N7002.
Winbond Electronic Corp. Title W83781D-W83782D Application Circuit Size B Date: Document Number Thursday, July 23, 1998 Sheet 3 of 3 Rev 0.3


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