View 74LVC821A_56191.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
74LVC821A 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
Product specification 1998 Sep 25
Philips Semiconductors
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
FEATURES
* 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic * Supply voltage range of 2.7V to 3.6V * Complies with JEDEC standard no. 8-1A * Inputs accept voltages up to 5.5V * CMOS low power consumption * Direct interface with TTL levels * 10-bit positive edge-triggered register * Independent register and 3-State buffer operation * Flow-through pin-out architecture
DESCRIPTION
The 74LVC821A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC821A is a10-bit D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The ten flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the ten flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CP to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Notes 1 and 2 CONDITIONS CL = 50 pF; VCC = 3 3 V 3.3 TYPICAL 5.4 150 5.0 26 UNIT ns MHz pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 24-Pin Plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C ORDERING CODE 74LVC821A D 74LVC821A DB 74LVC821A PW PKG. DWG. # SOT137-1 SOT340-1 SOT355-1
1998 Sep 25
2
853-1970 20088
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 12 13 24 SYMBOL OE D0 to D9 Q0 to Q9 GND CP VCC NAME AND FUNCTION Output enable input (active LOW) Data inputs
3-State flip-flop outputs Ground (0 V) Clock input (LOW-to-HIGH, edge-triggered) Positive supply voltage
FUNCTION TABLE
INPUTS OPERATING MODES Load and read register Load register and disable outputs Hold OE L L H H L CP H or L Dn l h l h X INTERNAL FLIP FLOPS FLIP-FLOPS L H L H NC OUTPUTS Q0 to Q9 L H Z Z NC
H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state = LOW-to-HIGH clock transition NC= no change
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 1 2 3 4 5 6 7 8 9 10 11 24 23 22 21 20 19 18 17 16 15 14 13 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 CP
LOGIC SYMBOL
13
2 3 4 5 6 7 8 9 10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
CP
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
GND 12
OE
SA00413
1
SA00414
1998 Sep 25
3
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 CP OE FF0 to FF9 3-STATE OUTPUTS 23 22 21 20 19 18 17 16 15 14
13 1
C1 EN 3 4
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
2
1D
23
5 6 7 8 9 10
3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14
11 13 1
SA00415
SA00416
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D CP FF0
Q
D CP FF1
Q
D CP FF2
Q
D CP FF3
Q
D CP FF4
Q
D CP FF5
Q
D CP FF6
Q
D CP FF7
Q
D CP FF8
Q
D CP FF9
Q
CP OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
SA00417
1998 Sep 25
4
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage (for max. speed performance) VCC VI VO Tamb tr, tf DC supply voltage (for low-voltage applications) DC Input voltage range DC output voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 0 -40 0 0 MAX 3.6 V 3.6 5.5 VCC 5.5 +85 20 10 C ns/V V V UNIT
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW state DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +6.5 "50 -0.5 to VCC +0.5 -0.5 to 6.5 "50 "100 -65 to +150 500 500 UNIT V mA V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Sep 25
5
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ Ioff ICC ICC Input leakage current 3-State output OFF-state current Power off leakage supply Quiescent supply current Additional quiescent supply current per input pin VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND VCC = 0.0V; VI or VO = 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0.1 "0 1 0.1 0.1 0.1 5 VCC*0.5 VCC*0.2 VCC*0.6 VCC*0.8 0.40 0.20 0.55 "5 "5 "10 10 500 A A A A A V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL tPHL tPLH tPZH tPZL tPHZ tPLZ tW tSU th fmax PARAMETER Propagation delay CP to Qn 3-State output enable time OE to Qn 3-State output disable time OE to Qn Clock pulse width HIGH or LOW Setup time Dn to CP Hold time Dn to CP Maximum clock pulse frequency WAVEFORM VCC = 3.3V 0.3V MIN Figures 1, 4 Figures 2, 4 Figures 2, 4 Figure 1 Figure 3 Figure 3 Figure 1 1.5 1.5 1.5 3.3 1.9 1.5 150 TYP1 5.4 5.5 3.8 1.7 0.6 0 200 MAX 7.3 7.6 6.2 - - - - VCC = 2.7V MIN 1.5 1.5 1.5 3.3 0.9 1.5 150 MAX 8.5 8.8 6.8 - - - - ns ns ns ns ns ns MHz UNIT
NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25C.
1998 Sep 25
6
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH -0.3V at VCC w 2.7V; VY = VOH - 0.1 VCC at VCC t 2.7V
1/fmax VI CP INPUT
GND
VI CP INPUT GND tsu th tsu th VM
VM tw tPHL VOH
VM
VM
Dn INPUT
GND tPLH VM VM
VOH Qn OUTPUT
Qn OUTPUT VOL
VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
SA00394
Figure 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency.
Figure 3. Data setup and hold times for the Dn input to the CP input.
TEST CIRCUIT
VI VCC OE INPUT GND VM VI D.U.T. RT CL 50pF 500 VO 500 S1 2 x VCC Open GND
PULSE GENERATOR tPLZ tPZL
VCC OUTPUT LOW-to-OFF OFF-to-LOW VX VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled VY VM tPZH VCC t 2.7V 2.7V - 3.6V VM
outputs enabled
SA00412
Figure 2. 3-State enable and disable times.
1998 Sep 25
7
EEEEEEE EEEE EE EEEEEEE EEEE EE EEEEEEE EEEE EE
VI VM VM
SW00229
Test VI VCC 2.7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
SY00003
Figure 4. Load circuitry for switching times.
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1998 Sep 25
8
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
1998 Sep 25
9
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
1998 Sep 25
10
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
NOTES
1998 Sep 25
11
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
74LVC821A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 08-98 9397-750-04584
Philips Semiconductors
yyyy mmm dd 12

▲Up To Search▲

Price & Availability of 74LVC821A

	To Download 74LVC821A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .