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74VHC74 Dual D-Type Flip-Flop with Preset and Clear
October 1992 Revised March 1999
74VHC74 Dual D-Type Flip-Flop with Preset and Clear
General Description
The VHC74 is an advanced high speed CMOS Dual DType Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D input is transferred to the Q output during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: fMAX = 170 MHz (typ) at TA = 25C s High noise immunity: VNIH = VNIL = 28% VCC (min) s Power down protection is provided on all inputs s Low power dissipation: ICC = 2 A (max) at TA = 25C s Pin and function compatible with 74HC74
Ordering Code:
Order Number 74VHC74M 74VHC74SJ 74VHC74MTC 74VHC74N Package Number M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names D1, D2 CK1, CK2 CLR1, CLR2 PR1, PR2 Q1, Q1, Q2, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Preset Inputs Output
Truth Table
Inputs CLR L H L H H H PR H L L H H H D X X X L H X CK X X Q L H L H Qn Outputs Function Q H L H L Qn No Change Clear Preset
Note 1: This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) state.

X
H (Note 1) H (Note 1)
(c) 1999 Fairchild Semiconductor Corporation
DS011505.prf
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74VHC74
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT ) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) Soldering (10 seconds) 260C -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20 mA 20 mA 25 mA 50 mA -65C to +150C
Recommended Operating Conditions (Note 3)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 3.3V 0.3V VCC = 5.0V 0.5V 0 100 ns/V 0 20 ns/V 2.0V to 5.5V 0V to +5.5V 0V to VCC -40C to +85C
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading varaibles. Fairchild does not recommend operation outside databook specifications. Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 0 - 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 2.0 2.0 3.0 4.5 TA = 25C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 20.0 V A A IOL = 4 mA IOL = 8 mA VIN = 5.5V or GND VIN = VCC or GND V V IOH = -4 mA IOH = -8 mA VIN = VIH IOL = 50 A or VIL V Typ Max TA = -40C to +85C Min 1.50 0.7 VCC 0.50 0.3 VCC Max Units V V VIN = VIH IOH = -50 A or VIL Conditions
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2
74VHC74
AC Electrical Characteristics
Symbol fMAX Parameter Maximum Clock Frequency 5.0 0.5 tPLH tPHL Propagation Delay Time (CK-Q, Q) 5.0 0.5 tPLH tPHL Propagation Delay Time (CLR, PR -Q, Q) 5.0 0.5 CIN CPD Input Capacitance Power Dissipation Capacitance
Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/2 (per F/F).
VCC (V) 3.3 0.3
TA = 25C Min 80 50 130 90 Typ 125 75 170 115 6.7 9.2 4.6 6.1 7.6 10.1 4.8 6.3 4 25 11.9 15.4 7.3 9.3 12.3 15.8 7.7 9.7 10 Max
TA = -40C to +85C Min 70 45 110 75 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 14.0 17.5 8.5 10.5 14.5 18.0 9.0 11.0 10 Max
Units MHz MHz ns ns ns ns pF pF
Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF VCC = Open (Note 4)
3.3 0.3
3.3 0.3
AC Operating Requirements
Symbol tW(L) tW(H) tW(L) tS tH tREC Minimum Pulse Width (CLR, PR) Minimum Setup Time Minimum Hold Time Parameter Minimum Pulse Width (CK) VCC (V) (Note 5) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Minimum Recovery Time (CLR, PR) 3.3 5.0
Note 5: VCC is 3.3 0.3V or 5.0 0.5V
TA = 25C Typ
TA = -40C to +85C Guaranteed Minimum 6.0 5.0 6.0 5.0 6.0 5.0 0.5 0.5 5.0 3.0 7.0 5.0 7.0 5.0 7.0 5.0 0.5 0.5 5.0 3.0 Units
ns ns ns ns ns
3
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74VHC74
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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74VHC74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
5
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74VHC74 Dual D-Type Flip-Flop with Preset and Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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