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| Low Power CMOS SRAM 128K X 16 Features: * Vcc operation voltage : 1.5 V~ 3.6V * Low power consumption : 15mA (Max.) operating current 1uA (Typ.) CMOS standby current * High Speed Access time : 70ns (Max.) at Vcc = 1.5V * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Data retention supply voltage as low as 1.2V * Easy expansion with CE\ and OE\ options UC62LV2048 -55/-70 Description The UC62LV2048 is a high performance, low power CMOS Static Random Access Memory organized as 131,072 words by 16 and operates from 1.5 V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1uA and maximum access time of 70ns in 1.5V operation. Easy memory expansion is provided enable (CE\), and active LOW output enable (OE\) and three-state output drivers. The UC62LV2048 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The US62LV2048 is available in the JEDEC standard 44 pin TSOP (Type II) and 48 ball BGA(6*8mm). PRODUCT FAMILY Product Family UC62LV2048JC UC62LV2048KC UC62LV2048AC UC62LV2048JI UC62LV2048KI UC62LV2048AI Operating Tempature 0 ~ 70 J Vcc Range Speed (ns) Vcc=1.5V(Max.) Power Consumption STANDBY Operating Vcc=3.3V(Typ.) 1uA Vcc=3.6V(Max.) 15mA Package Type TSOPII-44 BGA-48 DICE TSOPII-44 BGA-48 DICE 1.5V ~ 3.6V J 55/70 -40J ~ 85J 1.5V ~ 3.6V 55/70 1uA 15mA PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC BLOCK DIAGRAM ROW DECODER ROW Address ADDRESS INPUT BUFFER A0 - A16 MEMORY ARRAY 128K X 16 Bits UC62LV2048JC UC62LV2048JI COL Address COLUMN DECODER LB OE A0 A1 A2 NC CE WE OE UB LB CE WE OE SENSE AMPLIFIER & WRITE DRIVER CONTROL INPUT BUFFER CONTROL BLOCK X16 I/O BUFFER UB LB DQ0 ~ DQ15 DQ8 UB A3 A4 CE DQ0 DQ9 DQ10 A5 A6 DQ1 DQ2 GND DQ11 NC A7 DQ3 VCC VCC DQ12 NC A16 DQ4 GND DQ14 DQ13 A14 A15 DQ5 DQ6 DQ15 NC A12 A13 WE DQ7 NC A8 A9 A10 A11 NC U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 Page 1 Low Power CMOS SRAM 128K X 16 PIN DESCRIPTION Name A0 - A16 CE\ Type Input Input Function UC62LV2048 -55/-70 Address inputs for selecting one of the 131,072 x 16 bit words in the RAM CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip enable is not active, the device is deselected and not in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. WE\ Input The Write enable input is active LOW and controls read and write operations. With the chip selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when WE\ is LOW, the data present on the DQ pins will be written into the selected memory location. OE\ Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE\ is inactive. UB\ and LB\ DQ0 - DQ15 Vcc Gnd Input I/O Power Power Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE Mode Not Selected Output Disabled WE\ X H X H CE\ H L L L L L L L L OE\ X H X L L L X X X LB\ X X H L H L L H L UB\ X X H H L L H L L I/O 0 ~ 7 High Z High Z DOUT High Z DOUT DIN High Z DIN I/O 8 ~ 15 High Z High Z High Z DOUT DOUT High Z DIN DIN Vcc Current ISB,ISB1 ICC Read H H L ICC Write L L ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current RATING -0.5 to VCC+0.5 -40 to 125 -50 to 150 0.5 10 UNIT V J J W mA OPERATING RANGE RANGE Commercial Industrial AMBIENT TEMPERATURE 0J to 70J -40J to 85J VCC 1.5V ~ 3.6V 1.5V ~ 3.6V CAPACITANCE(1)(TA=25J ,f=1.0MHz) SYMBOL PARAMETER CONDITIONS MAX. UNIT Input VIN=0V 6 pF CIN Capacitance Input/Output VDQ 8 pF CDQ Capacitance 1. This parameter is guaranteed and not 100% tested. 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 Page 2 Low Power CMOS SRAM 128K X 16 DC ELECTRICAL CHARACTERISTICS (TA=0J to 70J ) Symbol VIL VIH IL IOL VOL VOH ICC ISB1 ISB2 UC62LV2048 -55/-70 Comment Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current TTL Standby Current CMOS Standby Current o Test Condition VCC=2.4V VCC=3.6V VCC=MAX VIN=0V to VCC VCC=MAX CE\=VIH or OE\=VIH VIO=0V t VCC VCC=3.6V, IOL=2mA VCC=3.0V, IOH=-1mA CE\=VIL,IDQ=0mA, F=Fmax CE\=VIH, VIN=VIH to VIL CE\U VCC-0.2V, VIN=VCC-0.2V (4) or 0.2V , F=0 (3) MIN. -0.5 2.0 2.4 - TYP.(1) 1 MAX. 0.8 Vcc-0.2 1 1 0.4 15 1 5 UNITS V V uA uA V V mA mA uA 1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . 4. F=0 means input signals must be keep in static state. DATA RETENTION CHARACTERISTICS ( TA=0J to 70J ) Symbol VDR ICCDR tDR tR 1. 2. Comment VCC to Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition CE\U VCC - 0.2V VINU VCC-0.2V or VINO CE\U VCC - 0.2V VINU VCC-0.2V or VINO 0.2V 0.2V MIN. 1.2 0 See Retention Waveform TRC (2) TYP. - (1) MAX. 0.5 - UNITS V uA ns ns 0.05 - VCC = 1.5V, TA = 25J . tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM(1) (CE\ Controlled) Vcc CE tCDR VIH Data Retention Mode VDR >= 1.2V CE >= VCC - 0.2V tR VIH U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 Page 3 Low Power CMOS SRAM 128K X 16 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level VCC to 0V 1 V/ns 0.5VCC UC62LV2048 -55/-70 KEY TO SWITCHING WAVEFORMS WAVEFORMS INPUTS MUST BE STEADY MAY CHANGE FROM H TO L 1269 OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE STATE UNKNOWN AC TEST LOADS AND WAVEFORMS 3.3V INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE 3.3V 1269 OUTPUT OUTPUT MAY CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED 1404 FIGURE 1A FIGURE 1B DOES NOT APPLY 1404 100pF 5pF TERMINAL EQUIVALENT 667 OUTPUT 1.73V CENTER LINE IS HIGH IMPEDANCE OFF STATE ALL INPUT PULSES V CC 90% 10% 90% 10% GND FIGURE 2 1V/ns 1V/ns AC ELECTRICAL CHARACTERISTICS (TA=0J to 70J , VCC=1.5V~3.6V) READ CYCLE JEDEC PARAMETER NAME tAVAX tAVQV tELQV tBA tGLQV tELQX tGLQX tBE tEHQZ tGHQZ tBDO tAXOX PARAMETER NAME tRC tAA tCE tBA tOE tCLZ tOLZ tBE tCHZ tOHZ tBDO tOH DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output Low Z Data Byte Control To Output Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Data Byte Control To Output High Z Address Chang to Output Change UC62LV2048-55 Min 55 Typ Max 55 55 30 10 5 10 10 20 20 20 30 - UC62LV2048-70 Min 70 Typ Max 70 70 35 10 5 10 10 20 20 20 35 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 Page 4 Low Power CMOS SRAM 128K X 16 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) tRC ADDRESS tOH DOUT tAA UC62LV2048 -55/-70 tOH READ CYCLE2 (1,3,4) CE tCLZ (5) DOUT tCE tCHZ (5) READ CYCLE3 (1,4) tRC ADDRESS tAA OE tOE CE tOLZ tCLZ (5) UB/LB tBE DOUT NOTES: 1. 2. 3. 4. 5. WE\ is high in read cycle. Device is continuously selected when CE\ = VIL Address valid prior to or coincident with CE\ transition low. OE\ = VIL. Transition is measured 500mV from steady state with CL=5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. tOH tOHZ (1,5) tCE tCHZ (5) tBA tBDO U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 Page 5 Low Power CMOS SRAM 128K X 16 UC62LV2048 -55/-70 AC ELECTRICAL CHARACTERISTICS (TA=0J to 70J , VCC=1.5V~3.6V) WRITE CYCLE JEDEC PARAMETER NAME tAVAX tE1LWH tAVWL tAVWH tBW tWLWH tWHAX tWLOZ tDVWH tWHDX tGHOZ tWHQX PARAMETER NAME tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOHZ tOW DESCRIPTION Write Cycle Time Chip Select to END of Write Address Setup Time Address valid to End of Write Data Byte Control End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold Time for Write End Output Disable to Output In High Z End of Write to Output Active UC62LV2048-55 Min 55 40 0 40 40 40 0 35 0 10 20 20 Typ Max - UC62LV2048-70 Min 70 50 0 50 50 50 0 40 0 10 20 20 Typ Max - UNIT ns ns ns ns Ns ns ns ns ns ns ns ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITECYCLE1(1) tWC ADDRESS tAW OE tCW(11) CE tAS (4,10) tWP(2) WE tBW UB/LB tOHZ DOUT tDW tDH DIN U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 Page 6 Low Power CMOS SRAM 128K X 16 WRITE CYCLE2(1,6) tWC ADDRESS tAW CE tAS tWP(2) WE tWHZ DOUT tDW DIN tCW(11) UC62LV2048 -55/-70 tOH (7) tDH (8) NOTES: 1. WE\ must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals must be active to initiate a write and any one can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\ transition, output remain in a high impedance state. 6. OE\ is continuously low (OE\ = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 Page 7 Low Power CMOS SRAM 128K X 16 UC62LV2048 -55/-70 ORDERING INFORMATION UC62LV2048 AB -- YY A => GRADE J :44pin TSOP(II) - 400 mil K :48Ball BGA - 6*8mm A :DICE B => GRADE C :COMMERCIAL (0 ~ 70J) I :INDUSTRIAL (-40 ~ 85J) YY => SPEED 55: 55ns 70: 70ns U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 Page 8 Low Power CMOS SRAM 128K X 16 PACKAGE DIMENSIONS 44 23 A UC62LV2048 -55/-70 UNIT SYMBOL INCH 0.0433O 0.004 0.004O 0.002 0.039O 0.002 0.012 ~ 0.018 0.012 ~ 0.016 0.005 ~ 0.008 0.005 ~ 0.006 0.725O 0.004 0.400O 0.004 0.463O 0.008 0.0315O 0.004 0.0197O 0.004 0.0197O 0.004 0.004 Max. 0X~ 8X MM 1.10 O 0.1 0.1O 0.05 1.00 O 0.05 0.3 ~ 0.45 0.3 ~ 0.4 0.12 ~ 0.21 0.12 ~ 0.16 18.41O 0.1 10.1 6O 0.1 11.76O 0.20 0.80 O 0.10 0.50O 0.1 0.80 O 0.1 0.1 Max. 0X~ 8X c A L L1 1 e 22 b "A" D DETAIL "A" (2:1) A A1 A2 b b1 c c1 D E E1 e L L1 y c b A2 E E1 A WITH PLATING c c1 BASE METAL Seating Plane "y" A1 b1 SECTION A-A TSOPII - 44 1.4 MAX S id e V iew 0.25 O 0.05 D 8 .0 D O 0 .1 B all p itch e= 0 .7 5 E D1 6 .0 5 .2 5 E1 3 .7 5 S old er B a ll d iam eter = 0 .3 5 O 0 .0 5 D1 e EO 0.1 E1 F ig. A Fig. A T O P V iew 4 8 M in i-B G A 6 * 8 m m U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 Page 9 |
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