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V58C3643204SAT HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32
PRELIMINARY
CILETIV LESOM
System Frequency (fCK) Clock Cycle Time (tCK3) Clock Cycle Time (tCK4)
45 225MHz
50 200 MHz 5 ns
55 183 MHz 5.5 ns
60 166 MHz 6 ns
4.5 ns
Features
s 4 banks x 512K x 32 organization s High speed data transfer rates with system frequency up to 225 MHz s Data Mask for Write Control (DM) s Four Banks controlled by BA0 & BA1 s Programmable CAS Latency: 3, 4 s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 2, 4, 8 full page for Sequential Type 2, 4, 8 full page for Interleave Type s Automatic and Controlled Precharge Command s Suspend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 2048 cycles/16ms s Available in 100-pin TQFP s SSTL-2 Compatible I/Os s Double Data Rate (DDR) s Bidirectional Data Strobe (DQs) for input and output data, active on both edges s On-Chip DLL aligns DQ and DQs transitions with CLK transitions s Differential clock inputs CLK and CLK s Power Supply 3.3V 0.3V
Description
The V58C3643204SAT is a four bank DDR DRAM organized as 4 banks x 512K x 32. The V58C3643204SAT achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating Temperature Range
0C to 70C
Package Outline 100-pin TQFP
*
CLK Cycle Time (ns) -45
*
Power -60
*
-50
*
-55
*
Std.
*
L
*
Temperature Mark
Blank
V58C3643204SAT Rev. 1.4 August 2001
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V58C3643204SAT
Block Diagram
Column decoder Sense amplifier & I(O) bus
Column decoder Sense amplifier & I(O) bus
Column decoder Sense amplifier & I(O) bus
Bank 0
Bank 1
Bank 2
Column decoder Sense amplifier & I(O) bus
RAS
CAS
WE
CLK, CLK
DLL Strobe Gen. Data Strobe
DQS
V58C3643204SAT Rev. 1.4 August 2001
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DM0-DM3
CKE
CLK
CLK
CS
CILETIV LESOM
Column Addresses A0 - A7, AP, BA0, BA1 Row Addresses A0 - A10, BA0, BA1 Column address counter Column address buffer Row address buffer Row decoder Memory array Row decoder Memory array Row decoder Memory array 512K x 32 512K x 32 512K x 32 Input buffer Output buffer DQ0-DQ
Refresh Counter
Row decoder Memory array Bank 3
512K x 32
Control logic & timing generator
V58C3643204SAT
Top View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
DQ29 VSSQ DQ30 DQ31 VSS VDDQ N.C N.C N.C N.C N.C VSSQ RFU DQS VDDQ VDD DQ0 DQ1 VSSQ DQ2
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 8 9
51 50 49 48 47 46 45 44 43
A8(AP)
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VREF
DQ28
DQ27
DQ26
DQ25
DQ24
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDD
DM3
DM1
MCL
CKE
DQ9
DQ8
VSS
CLK
CLK
DQ3
DQ4
DQ5
DQ6
DQ7
DM0
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM2
VSS
CAS
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSSQ
Pin Names
CLK, CLK CKE CS RAS CAS WE DQS A0-A10 BA0, BA1 Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe (Bidirectional) Address Inputs Bank Select DQ0-DQ7 DM0-DM3 VDD VSS VDDQ VSSQ NC VREF RFU Data Input/Output Data Mask Power (3.3V 0.3V) Ground Power for I/O's (+2.5V) Ground for I/O's Not connected Reference Voltage for Inputs Reserved for future use.
V58C3643204SAT Rev. 1.4 August 2001
3
VDDQ
RAS
BA1
BA0
WE
CS
CILETIV LESOM
100 Pin TQFP PIN CONFIGURATION
A7 A6 A5 A4 VSS A9 N.C N.C N.C N.C N.C N.C N.C N.C A10 VDD A3 A2 A1 A0
100 Pin TQFP 20 x 14 mm2 0.65mm pin Pitch
42 41 40 39 38 37 36 35 34 33 32 31
V58C3643204SAT
CILETIV LESOM
Pin
CLK CLK CKE
Signal Pin Description
Type
Input
Signal
Pulse
Polarity
Positive Edge
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CLK.
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. Active High Active on both edges for data input and output. Center aligned to input data Edge aligned to output data -- During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge. CAn depends from the SDRAM organization: 2M x 32 SDRAM CAn = CA7 (Page) In addition to the column address, A8 is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A8 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A8 is low, autoprecharge is disabled. During a Precharge command cycle, A8(=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged simultaneously regardless of state of BA0 and BA1.
CS
Input
Pulse
RAS, CAS WE DQS
Input
Pulse
Input/ Output
Pulse
A0 - A10
Input
Level
BA0, BA1 DQx
Input
Level
--
Selects which bank is to be active.
Input/ Output Input
Level
--
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DM0-DM3
Pulse
Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if is high. Power and ground for the input buffers and the core logic.
VDD, VSS Supply VDDQ VSSQ VREF Supply -- --
Isolated power supply and ground for the output buffers to provide improved noise immunity. SSTL Reference Voltage for Inputs
Input
Level
--
V58C3643204SAT Rev. 1.4 August 2001
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V58C3643204SAT
The Auto Precharge operation can be issued by having column address A8 high when a Read or Write command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. When the Auto Precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the Read or Write cycle once tRAS(min) is satisfied. Read with Auto Precharge If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency programmed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until the minimum precharge time (tRP) has been satisfied.
CILETIV LESOM
T0 T1 CK, CK Command DQS DQ BA
Auto Precharge Operation
Read with Autoprecharge Timing
(CAS Latency = 2; Burst Length = 4) T2 T3 tRAS(min) T4 T5 T6 T7 tRP(min) T8 T9
NOP
R w/AP
NOP
NOP
NOP
NOP
NOP
BA
D0
D1
D2
D3
Begin Autoprecharge Earliest Bank A reactivate
V58C3643204SAT Rev. 1.4 August 2001
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V58C3643204SAT
CILETIV LESOM
DC Characteristics
Recommended operating conditions Unless Otherwise Noted, TA=0 to 70C
Parameter
Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in in Non Power-down mode Operating Current (Burst Mode) Refresh Current Self Refresh Current Notes: 1. Measured with outputs open. 2. Refresh period is 16ms.
Version Symbol
ICC1 ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC6
Test Condition
Burst Lenth = 2 tRC S tRC(min) IOL= 0mA, tCC = tCC(min) CKE VIL(max), tCC = tCC(min) CKE VIH(min), CS S VIH(min), tCC = tCC(min) CKE VIL(max), tCC = tCC(min) CKE S VIH(min), CS S VIH(min), tCC = tCC(min) IOL = 0mA, tCC = tCC(min), Page Burst, All Banks activated tRC S tRFC(min) CKE 0.2V
-45
350
-50
340
-55
330
-60
330
Unit Note
mA 1
60
mA
165
160
155
150
mA
95 205 200 195 190
mA mA
470
450
430
410
mA
1
470
450 4
430
410
mA mA
2
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current
Symbol
VIN , VOUT VDD, VDDQ TSTG PD IOS
Value
-1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1.6 50
Unit
V V C W mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
V58C3643204SAT Rev. 1.4 August 2001
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V58C3643204SAT
CILETIV LESOM
Parameter
Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic low voltage Input leakage current Output leakage current
Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions (Voltage referenced to VSS=0V, TA=0 to 65C)
Symbol
VDD VDDQ VREF Vtt VIH VIL VOH VOL IIL IOL
Min
3.135 2.375 0.49*VDDQ VREF-0.04 VREF+0.15 -0.30 Vtt+0.76 -5 -5
Typ
3.3 2.50 VREF -
Max
3.465 2.625 0.51*VDDQ V REF+0.04 VDDQ+0.30 VREF-0.15 Vtt-0.76 5 5
Unit
V V V V V V V V A A
Output logic high voltage IOH = -15.2mA
AC Input Operating Conditions
Recommended operating conditions (Voltage referenced to VSS=0V, VDD=3.3V+ 5%, VDDQ=2.5V+ 5%, TA=0 to 65C)
Parameter
Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK
Symbol
VIH VIL VID VIX
Min
VREF+0.35 0.7 0.5*VDDQ-0.2
Typ
-
Max
VREF -0.35 VDDQ+0.6 0.5*VDDQ+0.2
Unit
V V V V
SSTL_2 AC Test Conditions
Symbol
VREF V SWING (max) SLEW
Parameter
Input Reference Voltage Input Signal Maximum Peak to Peak Swing Input Signal Minimum Slew Rate
Value
0.5*VDDQ 1.5 1.0
Units
V V V/ns
Notes
1 1, 2 3
Notes: 1. Input waveform timing is referenced to the input signal crossing the VREF level applied to the device. 2. Compliant devices must still meet the VIH (AC) and VIL (AC) specifications under actual use conditions. 3. The 1 V/ns input signal minimum slew rate is to be maintained in the VIL max (AC) to VIL min (AC) range of the input signal swing.
V58C3643204SAT Rev. 1.4 August 2001
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V58C3643204SAT
s s s s
Capacitance (VDD = 3.3V, TA = 25C, f = 1MHz)
Parameter
Input capacitance (A0~A10, BA0~BA1) Input capacitance ( CK, CK, CKE, CS, RAS, CAS, WE ) Data & DQS input/output capacitance (DQ 0~DQ31) Input capacitance (DM0 ~ DM3)
CILETIV LESOM
SSTL_2 Output Buffers
The input voltage provided to the receiver depends on three parameters: VDDQ and current drive capabilities of the output buffer Termination voltage Termination resistance VDDQ VDD
Class II SSTL_2 Output Buffer (Driver)
VDDQ VTT = 0.5 *VDDQ RT=50 Output Buffer VREF VOUT VSSQ VIN CLOAD = 30pF
Receiver
Symbol
CIN1 CIN2 COUT CIN3
Min
2.5 2.5
Max
4.5 5.0
Unit
pF pF
2.5 2.5
5.5 5.5
pF pF
V58C3643204SAT Rev. 1.4 August 2001
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V58C3643204SAT
CILETIV LESOM
AC Characteristics
-45 Parameter
CK cycle time CL=3 CL=4 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to output data edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble DQS-In high level width DQS-In low level width Address and Control input setup time Address and Control input hold time DQ and DM setup time to DQS DQ and DM hold time to DQS Clock half period tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD tMRD tPEDX 69 18 12 9 2 2 1 2 58 69 -0.70 -0.70 +0.70 +0.70
-50 Max
7
-55 Max
7
-60 Max
7
Symbol
tCK
Min
* 4.5
Min
5 .0 * 0.45 0.45 -0.70 -0.70 0.9 0.4 0.75 0 0.25 0.4 0.4 0.4 1.2 0.9 0.5 0.5 tCLmin or tCHmin tHP0.75ns 60 70 40 20 20 14 2 2 1 2 1tCK+tIS 70 200
Min
5.5 *
Min
6 .0 *
Max Unit
7 ns ns 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 0.6 0.6 0.6 tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns
0.55 0.55 +0.70 +0.70 0.5 1.1 0.6 1.25 0.6 0.6 0.6 -
0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.4 0.4 0.4 1.2 0.9 0.5 0.5 tCLmin or tCHmin tHP0.75ns 60.5 71.5
0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 0.6 0.6 0.6 -
0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.4 0.4 0.4 1.2 0.9 0.5 0.5 tCLmin or tCHmin tHP0.75ns 60 72
Output DQS valid window
-
-
-
ns
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Last data in to Row precharge Last data in to Read command delay Col. address to Col. address delay Mode register set cycle time Power down exit time
ns ns 100K ns ns ns ns tCK tCK tCK tCK ns ns 200 tCK tCK s
100K
44 22 16.5 11 2 2 1 2 1tCK+tIS 71.5 200 5
100K
48 24 18 12 2 2 1 2 1tCK+tIS 72
Self refresh exit to active command delay tXSA Self refresh exit to read command delay tXSR Auto precharge write recovery + Precharge Refresh interval time tDAL tREF
6
6
5
7.8
7.8
7.8
V58C3643204SAT Rev. 1.4 August 2001
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V58C3643204SAT
CILETIV LESOM
AC Characteristics
V58C3643204SAT-45
Frequency
250MHz (4.5ns) 222MHz (5.0ns) 183MHz (5.5ns) 166MHz (6.0ns) 143MHz (7.0ns)
Cas Latency
4 3 3 3 3
tRC
13 12 12 10 9
tRFC
15 14 14 12 11
tRAS
9 8 8 7 6
tRCDRD
4 4 4 3 3
tRCDWR
2 2 2 2 2
tRP
4 4 4 3 3
tRRD
2 2 2 2 2
Unit
tCK tCK tCK tCK tCK
V58C3643204SAT-50
Frequency
200MHz (5.0ns) 183MHz (5.5ns) 166MHz (6.0ns) 143MHz (7.0ns)
Cas Latency
3 3 3 3
tRC
12 12 10 9
tRFC
14 14 12 11
tRAS
8 8 7 6
tRCDRD
4 4 3 3
tRCDWR
2 2 2 2
tRP
4 4 3 3
tRRD
2 2 2 2
Unit
tCK tCK tCK tCK
V58C3643204SAT-55
Frequency
183MHz (5.5ns) 166MHz (6.0ns) 143MHz (7.0ns)
Cas Latency
3 3 3
tRC
12 10 9
tRFC
14 12 11
tRAS
8 7 6
tRCDRD
4 3 3
tRCDWR
2 2 2
tRP
4 3 3
tRRD
2 2 2
Unit
tCK tCK tCK
V58C3643204SAT-60
Frequency
166MHz (6.0ns) 143MHz (7.0ns)
Cas Latency
3 3
tRC
10 9
tRFC
12 11
tRAS
7 6
tRCDRD
3 3
tRCDWR
2 2
tRP
3 3
tRRD
2 2
Unit
tCK tCK
V58C3643204SAT Rev. 1.4 August 2001
10
V58C3643204SAT
0.575
CILETIV LESOM
Package Diagram 100-Pin TQFP
17.20 0.20 14.00 0.10 #100 #1 23.20 0.20 20.00 0.10 0.825 0.30 0.08 0.13 MAX 0.65 1.00 0.10 1.20 MAX * 0.10 MAX 0.05 MIN 0.80 0.20
V58C3643204SAT Rev. 1.4 August 2001
Dimensions in Millimeters
0 ~ 7
0.09~0.20
11
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
V58C3643204SAT
UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
CILETIV LESOM
SINGAPORE
10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013
JAPAN
ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402
GERMANY (CONTINENTAL EUROPE & ISRAEL)
BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
SOUTHWESTERN
302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807
CENTRAL, NORTHEASTERN & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029
(c) Copyright 2001, MOSEL VITELIC Inc.
8/01 Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
CILETIV LESOM
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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