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STK15C88 32K x 8 AutoStoreTM nvSRAM High Performance CMOS Nonvolatile Static RAM FEATURES * Nonvolatile Storage Without Battery Problems * Directly Replaces 32K x 8 static RAM, Battery Backed RAM or EEPROM * 25ns, 35ns and 45ns Access Times * Store to EEPROM Initiated by Software or AutoStoreTM on Power Down * Recall to SRAM by Software or Power Restore * 15mA ICC at 200ns Cycle Time * Unlimited Read, Write and Recall Cycles * 1,000,000 Store Cycles to EEPROM * 100 Year Data Retention Over Full Industrial Temperature Range * Commercial and Industrial Temp. Ranges * 28 Pin 600 or 300 mil PDIP and 350 mil SOIC DESCRIPTION The Simtek STK15C88 is a fast static RAM with a nonvolatile, electrically-erasable PROM element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent, nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) can take place automatically on power down using charge stored in system capacitance. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be controlled by entering control sequences on the SRAM inputs. BLOCK DIAGRAM EEPROM ARRAY 256 x 1024 A6 A7 A8 A9 A11 A12 A13 A14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 ROW DECODER PIN CONFIGURATIONS A 14 A 12 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 V CC W A 13 A8 A9 A 11 G A 10 E DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 VCC A6 A5 A4 A3 STORE STATIC RAM ARRAY 256 x 1024 RECALL STORE/ RECALL CONTROL POWER CONTROL A2 A1 A0 DQ 0 DQ 1 DQ 2 V SS SOFTWARE DETECT INPUT BUFFERS A0 A13 COLUMN I/O COLUMN DEC 28 - 300 PDIP 28 - 600 PDIP 28 - 350 SOIC 28 - 300 SOIC PIN NAMES A0 A1 A2 A3 A4 A5 A10 A0 - A14 Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+5V) Ground G W DQ0 - DQ7 E W E G VCC VSS August 1998 5-35 STK15C88 ABSOLUTE MAXIMUM RATINGSa Voltage on input relative to VSS . . . . . . . . . . . -0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Temperature under bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Note a: Stresses greater than those listed under "Absolute Maxmum Ratings" may cause permanent damage to the device. This a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTERISTICS COMMERCIAL SYMBOL ICC1b PARAMETER MIN Average Current MAX 95 75 65 6 15 4 29 24 20 3 1 5 2.2 VSS - .5 2.4 0.4 0 70 -40 0.4 85 MIN MAX 100 80 70 7 15 4 30 25 21 3 1 5 VCC + .5 0.8 mA mA mA mA mA mA mA mA mA mA A A V V V V C INDUSTRIAL UNITS (Vcc = 5.0V 10%) NOTES tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns All inputs Don't Care W (V CC - 0.2V) All others cycling, CMOS levels All inputs Don't Care tAVAV = 25ns, E VIH tAVAV = 35ns, E VIH tAVAV = 45ns, E VIH E (V CC - 0.2V) All others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All inputs All inputs IOUT = - 4mA IOUT = 8mA ICC2c ICC3b ICC4c ISB1d Average Current During STORE Average VCC Current at tAVAV = 200ns Average Current During AutoStoreTM Cycle Average Current (Standby, Cycling TTL Input Levels) Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current ISB2d IILK IOLK SRAM READ CYCLES #1 & SRAM READ+ .5 VIH Input Logic "1" Voltage 2.2 VCC VIL VOH VOL TA Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature VSS - .5 2.4 0.8 Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ) . 2 4 Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS 5.0V Input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and output timing reference levels . . . . . . . . . . . . . . . . . 1.5V Output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 480 Ohms Output 30pF INCLUDING SCOPE AND FIXTURE CAPACITANCEe SYMBOL CIN COUT PARAMETER Input capacitance Output capacitance (TA = 25C, f = 1.0MHz) MAX 5 7 UNITS pF pF CONDITIONS 255 Ohms V = 0 to 3V V = 0 to 3V Figure 1: AC Output Loading Note e: These parameters are guaranteed but not tested. August 1998 5-36 SRAM READ CYCLES #1 & #2 SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 PARAMETER #1, #2 tELQV tAVAVf tAVQVg tGLQV tAXQXg tELQX tEHQZh tGLQX tGHQZh tELICCHe tEHICCLd, e Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 25 0 10 0 3 5 10 0 25 25 10 3 5 MIN MAX 25 35 MIN STK15C88-25 STK15C88 (Vcc = 5.0V 10%) STK15C88-35 MAX 35 45 35 15 3 5 13 0 13 0 35 45 15 15 45 20 STK15C88-45 UNITS MIN MAX 45 ns ns ns ns ns ns ns ns ns ns ns Note f: W must be high during SRAM read cycles and low during SRAM write cycles. Note g: I/O state assumes E, G, < VIL and W > VIH; device is continuously selected Note h: Measured + 200mV from steady state output voltage SRAM READ CYCLE #1 (Address Controlled)f, g tAVAV ADDRESS 5 tAXQX 3 2 tAVQV DATA VALID DQ(Data Out) SRAM READ CYCLE #2 (E Controlled)f tAVAV ADDRESS tELQV E 6 tELQX 1 2 tEHICCL 7 11 tEHQZ G tGLQX DQ(Data Out) 10 tELICCH DATA VALID 8 tGLQV 4 tGHQZ 9 ACTIVE ICC STANDBY August 1998 5-37 STK15C88 SRAM WRITE CYCLES #1 & #2 SYMBOLS NO. #1 12 13 14 15 16 17 18 19 20 21 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZh, i tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold After End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write 5 PARAMETER MIN 25 20 20 10 0 20 0 0 10 5 MAX MIN 35 25 25 12 0 25 0 0 13 5 MAX MIN 45 30 30 15 0 30 0 0 15 MAX ns ns ns ns ns ns ns ns ns ns STK15C88-25 (Vcc = 5.0V 10%) STK15C88-35 STK15C88-45 UNITS Note i: Note j: If W is low when E goes low the outputs remain in the high impedance state. E or W must be VIH during address transitions. SRAM WRITE CYCLE #1: W CONTROLLEDj tAVAV ADDRESS tELWH E 14 19 12 tWHAX tAVWH 18 tAVWL 13 17 W tWLWH 15 16 tDVWH DATA IN tWLQZ DATA OUT PREVIOUS DATA HIGH IMPEDENCE 20 DATA VALID tWHDX tWHQX 21 SRAM WRITE CYCLE #2: E CONTROLLEDj tAVAV ADDRESS tAVEL E 18 14 19 12 tELEH tEHAX tAVEH W tWLEH 15 13 17 tDVEH DATA IN DATA OUT HIGH IMPEDENCE DATA VALID tEHDX 16 August 1998 5-38 STK15C88 AutoStoreTM / POWER-UP RECALL SYMBOLS NO. Standard 22 23 24 25 26 tRESTORE tSTORE tDELAY VSWITCH VRESET Power Up RECALL Duration STORE Cycle Duration Time allowed to Complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level 1 PARAMETER (Vcc = 5.0V 10%) STK15C88 UNITS NOTES MIN MAX 550 10 s ms s 4.5 3.9 V V k g g 4.0 Note k: tRESTORE starts from the time VCC rises above VSWITCH. AutoStoreTM / POWER UP RECALL V 25 26 CC 5V VSWITCH VRESET AUTOSTORE TM t STORE POWER UP RECALL 23 22 t RESTORE 24 t DELAY W DQ (Data Out) POWER-UP RECALL BROWN OUT NO STORE DUE TO NO SRAM WRITES NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT AutoStoreTM NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT AutoStoreTM RECALL WHEN ABOVE VSWITCH August 1998 5-39 STK15C88 SOFTWARE MODE SELECTION E W A13 - A0 (hex) 0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63 MODE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM NonvolatileRECALL I/O Output data Output data Output data Output data Output data Output high Z Output data Output data Output data Output data Output data Output high Z NOTES L H l,m L H l,m Note l: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note m: While there are 15 addresses on the STK15C88, only the lower 14 are used to control software modes. SOFTWARE CYCLES #1 & #2n,o SYMBOLS NO. #1 27 28 29 30 31 32 tAVAV tELQZg,n tAVELn tELEHn tELAXg,n tRECALL PARAMETER MIN MAX MIN 35 650 0 20 20 20 0 25 20 20 650 MAX STK15C88-25 STK15C88-35 (VCC = 5.0V 10%) STK15C88-45 UNITS MIN 45 650 0 30 20 20 MAX ns ns ns ns ns s 25 STORE/RECALL initiation cycle time End of Sequence to Outputs Inactive Address Set-up Time Clock Pulse Width Address Hold Time Recall Duration Note n: The software sequence is clocked with E controlled reads. Note o: The six consecutive addresses must be in the order listed in the SOFTWARE MODE SELECTION Table - (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE CYCLE: E CONTROLLED 27 t AVAV 27 t AVAV ADDRESS #6 ADDRESS 29 t AVEL ADDRESS #1 30 t ELEH E 31 t ELAX 23 32 t STORE t RECALL t ELQZ28 DQ(Data Out) DATA VALID DATA VALID HIGH IMPEDANCE August 1998 5-40 STK15C88 DEVICE OPERATION The STK15C88 is a versatile memory chip that provides several modes of operation. The STK15C88 can operate as a standard 32K x 8 SRAM. It has a 32K x 8 EEPROM shadow to which the SRAM information can be copied, or from which the SRAM can be updated in nonvolatile mode. SOFTWARE NONVOLATILE STORE The STK15C88 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle NOISE CONSIDERATIONS Note that the STK15C88 is a high speed memory and so must have a high frequency bypass capacitor of approximately 0.1F connected between DUT VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM READ The STK15C88 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ CYCLE #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ CYCLE #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high. The software sequence is clocked with E controlled reads. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. SOFTWARE NONVOLATILE RECALL A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0C63 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle August 1998 5-41 STK15C88 Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. HARDWARE PROTECT The STK15C88 offers hardware protection against inadvertent STORE operation during low voltage conditions. When VCC < VSWITCH all Software STORE operations will be inhibited. AutoStoreTM OPERATION The STK15C88 uses the intrinsic system capacitance to perform an automatic store on power down. As long as the system power supply takes at least tSTORE to decay from VSWITCH down to 3.6V the STK15C88 will safely and automatically store the SRAM data in EEPROM on power-down. In order to prevent unneeded STORE operations, automatic STORE will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. LOW AVERAGE ACTIVE POWER The STK15C88 draws significantly less current when it is cycled at times longer than 30ns. Figure 2, below, shows the relationship between ICC and READ cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK15C88 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READ's to WRITE's; 5) the operating temperature; 6) the VCC level and; 7) I/O loading. POWER UP RECALL During power up, or after any low power condition (VCC < VRESET) an internal recall request will be latched. When VCC once again exceeds the sense 100 100 Average Active Current (mA) Average Active Current (mA) 80 80 60 60 TTL CMOS 20 40 40 20 CMOS 0 50 100 150 200 TTL 0 50 100 150 200 Cycle Time (ns) Cycle Time (ns) Fig 2: Icc (max) Reads Fig 3: Icc (Max) Writes August 1998 5-42 STK15C88 ORDERING INFORMATION STK15C88 - W 25 I Temperature Range blank = Commercial (0 to 70 degrees C) I = Industrial (-40 to 85 degrees C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Package W = Plastic 28 pin 600 mil DIP P = Plastic 28 pin 300 mil DIP S = Plastic 28 pin 350 mil SOIC N = Plastic 28 pin 300 mil SOIC August 1998 5-43 |
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