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TS652
DIFFERENTIAL VARIABLE GAIN AMPLIFIER
s LOW NOISE : 4.6nV/Hz s LOW DISTORTION s HIGH SLEW RATE : 90V/s s WIDE BANDWIDTH : 52MHz @ -3dB &
18dB gain
s GAIN PROGRAMMABLE from -9dB to
+30dB with 3dB STEPS
s POWER DOWN FUNCTION
DESCRIPTION The TS652 is a differential digitally controled variable gain amplifier featuring a high slew rate of 90V/s, a large bandwidth, a very low distortion and a very low current and voltage noise. The gain can be set from -9dB to +30dB through a 4bit digital word, with 3dB steps. The gain monotonicity is guaranteed by design. This device is particularly intended for applications such as preamplification in telecommunication systems using multiple carriers. APPLICATION
+Vcc1 1
D SO-14 (Plastic Micropackage)
PIN CONNECTIONS (top view)
14 +Vcc2
Input 1 2 Input 2 3 GC1 4 5 Gain Control Logic Decoder
13 Output 1 12 Output 2 11 Power Down 10 -Vcc 9 AGND 8 DGND
s Preamplifier and automatic gain control for
Assymetric Digital Subscriber Line (ADSL). ORDER CODE
Package Part Number TS652ID Temperature Range D -40, +85C *
GC2
GC3 6 7
GC4
D = Small Outline Package (SO) - also available in Tape & Reel (DT)
May 2000
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TS652
ABSOLUTE MAXIMUM RATINGS
Symbol VCC Vi Toper Tstd Tj Rthjc Supply voltage 1) Input Voltage
2)
Parameter
Value 14 0 to 14 -40 to + 85 -65 to +150 150 15 Infinite
Unit V V C C C C/W
Operating Free Air Temperature Range TS652ID Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Case Output Short Circuit Duration
1. All voltages values are with respect to network terminal. 2. The magnitude of input and output voltages must never exceed VCC +0.3V.
OPERATING CONDITIONS
Symbol VCC Vicm Supply Voltage Common Mode Input Voltage Parameter Value 5 to 12 + VCC/2 Unit V V
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TS652
ELECTRICAL CHARACTERISTICS. VCC = 6Volts, Tamb = 25C (unless otherwise specified).
Symbol Vi ICC Iccpdw V OFFSET SVR Zin Zout VOH VOL AV PAV Avstep Avmin Parameter Voltage on the Input Pin Total Supply Current No load, Vout = 0 Power Down Total Consumption Power Down Mode Differential Input Offset Voltage Vin = 0, AV = 30dB Supply Voltage Rejection Ratio Input Impedance Power Down Output Impedance Power Down Mode High Level Output Voltage RL = 500 RL connected to GND Low Level Output Voltage RL connected to GND RL = 500 -9 -1 2.4 3 100k 4 AV = 0dB 50 80 100k//5pF 150k//5pF 4.5 -4.5 -4 30 1 3.6 1 55 32 26 10 17 17 50 110 69 52 18 0.08 28 22 100 1.5 4.6 200 132 100 36 dB mA V/s pA/Hz nV/Hz MHz V V dB dB dB dB Test Conditio n Min. Typ. 0 28 150 6 Max Unit V mA A mV dB
DC PERFORMANCE
AC PERFORMANCE
Voltage Gain F= 1MHz Gain monotonicity guaranteed by design Precision of the Voltage Gain F= 1MHz Step Value Gain Mismatch between Both Channels Bandwidth @ -3dB R L = 500 C L = 15pF Bandwidth Roll-off Bandwidth @ -3dB RL = 500, CL = 15pF Slew Rate (gain independent) Equivalent Input Noise Current Equivalent Input Noise Voltage F= 1MHz F= 1MHz AV = -9dB
Bw
AV = 0dB AV = +18dB AV = +30dB AV = +30dB, F = 1MHz |Source| Sink Vo = 2Vpeak F = 100kHz F = 100kHz AV = 30dB 1Vpeak, F = 150kHz, AV = +30dB, RL = 500//15pF
Rbw Io SR in en
NOISE AND DISTORTION
THD30
Harmonic Distorsion
IM3
Third Order Intermodulation Product F1 = 180kHz, F2 = 280kHz
H2 H3 H4 H5 Vout = 1Vpeak, AV = +30dB RL = 500//15pF @ 80kHz @ 380kHz @640kHz @740kHz Vout = 1Vpeak, AV = +30dB RL = 500//15pF @ 60kHz @ 90kHz @220kHz @230kHz
-70 -93 -98 -99
dBc
-77 -85 -86 -87
dBc
IM3
Third Order Intermodulation Product F1 = 70kHz, F2 = 80kHz
-77 -79 -83 -84
dBc
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TS652
DIGITAL INPUTS
Symbol GC1, GC2, GC3 and GC4 Parameter Low Level High Level 2 Min. Typ. 0 3.3 Max. 0.8 Unit V
SIMPLIFIED SCHEMATIC The TS652 consists of two independent channels. Each channel has two stages. The first is a very low noise digitally controlled variable gain amplifier (range 0 to 18dB). The TS652 features a high input impedance and a low noise current. To minimize the overall noise figure, the source impedance must be less than 3k. This value gives an equal contribution of voltage and current noises. The second stage is a gain/attenuation stage (+12dB to -9dB) featuring a low output impedance. This output stage can drive loads as low as 500.
v Input1
+ _ _
Ouput1
+
+Vcc1 v -Vcc Analog GND (AGND)
v
+
+ _
Ouput2 +Vcc2
Input2
_
v v
GAIN CONTROL LOGIC DECODER
GC1 GC2 GC3 GC4
Digital GND (DGND)
POWER DOWN MODE POSITION
+Vcc
+Vcc
Power Down
Input
Output
-Vcc
-Vcc
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TS652
BANDWIDTH The small signal bandwidth is almost constant for gains between +18dB to 0dB and is in the order of 52MHz to 70MHz respectively. For 30dB gain the bandwidth is around 18MHz. The power bandwidth is typically equal to 30MHz for 2V peak to peak signals. MAXIMUM INPUT LEVEL The input level must not exceed the following values : negative peak value: must be greater than -VCC + 1.5V positive peak value: must be less than +VCC - 1.5V For example, if a +/-6V power supply is used, the input signal can swing between -4.5V and +4.5V. These values are due to common mode input range limitations of the input stage of the first amplifier. Some other limitations may occur, due to the slew rate of the first operational amplifier (typically in the order of 300V/s). This means that the maximum input signal decreases at high frequency. SINGLE SUPPLY OPERATION The incoming signal is AC coupled to the inputs. The TS652 can be used either with a dual or a single supply. If a single supply is used, the inputs are biased to the mid supply voltage (+VCC/2). This bias network must be carefully designed, in order to reject any noise present on the supply rail. The AGND pin (9) must be connected to +VCC/2. The bias current of the second stage (inverting structure) is 8A for both amplifiers. A resistor divider structure can be used. Two resistances should be chosen by considering 8A as the 1% of the total current through these resistances. For a single +12V supply voltage, two resistances of 7.5k can be used. The differential input consists of a high pass circuit, formed by the 1F capacitor and a 1k resistance and gives a break frequency of 160Hz. SINGLE +12V SUPPLY OF THE TS652
1F IN+ 12V 1k 47k
10nF
100nF TS652
+Vcc1 1 Input 1 14 +Vcc2 13 Output 1 12 Output 2 11 Power Down Gain Control Logic Decoder 10 -Vcc
12V
2
10nF
100nF
10F
Input 2 3
1k
10nF
47k
1F
GC1 4 GC2 5
12V 7.5k
INGC3 6
9 AGND 8 DGND
1F
GC4 7
10nF
7.5k
1F
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TS652
GAIN CONTROL The gain and the power down mode is programmed with a 4 bit digital word :
Digital Control $0000 $0001 $0010 $0011 $0100 $0101 $0110 $0111 $1000 $1001 $1010 $1011 $1100 $1101 $1110 $1111 Total Gain (dB) -9 -6 -3 0 3 6 9 12 15 18 21 24 27 30 30 30 First Stage Gain (dB) 0 0 0 0 3 6 9 12 15 18 21 24 27 30 30 30 Second Stage Gain (dB) -9 -6 -3 0 0 0 0 0 0 0 3 6 9 12 12 12 Maximum Input Level 2.8Vrms 2.8Vrms 2.8Vrms 2.8Vrms 2Vrms 1.4Vrms 1Vrms 0.7Vrms 0.5Vrms 0.35Vrms 0.25Vrms 175mVrms 125mVrms 88mVrms 88mVrms 88mVrms Bandwidth Small Signal 110mHZ 100MHz 85MHz 69MHz 63MHz 58MHz 56MHz 55MHz 54MHz 52MHz 42MHz 30MHz 24MHz 18MHz 18MHz 18MHz Eq. Input Noise (nV/Hz) 29 26 23 22 16 12 9 7 6 4.8 4.7 4.7 4.6 4.6 4.6 4.6
The gain is the same for both channels. The digital inputs are CMOS compatible. The supply voltage of the logic decoder used to transcode the digital word can be either 3.3V or 5V or VCC.
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TS652
Closed Loop Gain vs. Frequency
40 30
Bandwidth vs. Gain
100 90
BANDWIDTH (MHz)
20
80 70 60 50 40 30 20 10
Gain (dB)
10 0 -10 -20 -30 -40 10kHz
100kHz
1MHz
10MHz
100MHz
-9
-6 -3
0
3
6
9
12 15 18 21 24 27 30
Frequency
GAIN (dB)
Negative & Positive Slew Rate vs. Gain
110
Equivalent Input Voltage Noise vs. Gain
30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 -9 -6 -3 0 3 6 9 12 15 18 21 24 27 30
SLEW RATE (V/s)
100 95
SR-
SR+
90 85 80 75 70 -9 -6 -3 0 3 6 9 12 15 18 21 24 27 30
VOLTAGE NOISE (nV/VHz)
105
GAIN (dB)
GAIN (dB)
Gain Switching (+15dB to -9dB)
Gain Switching (+30dB to +9dB)
6 5 4
6
GC4 command
5 4
GC1 command
Ouput Signal (V)
3 2 1 0 -1 -2 -3 -4
0 5s 10s 15s 20s
Ouput Signal (V)
3 2 1 0 -1 -2 -3 -4
0 5s 10s 15s 20s
Ouput Signal
Ouput Signal
Time
Time
measurement conditi ons: Vcc=6V, Rload=500, Tamb=25C 7/9
TS652
Output/Input Isolation in Power Down Mode vs. Frequency 3rd Order Intermodulation (2 tones : 180kHz and 280kHz)
-50 -60
-70
-75
Isolation (dB)
IM3 (dBc)
-70 -80 -90
60kHZ 90kHZ
-80
220kHZ
-85
-100 -110
230kHZ
-90
10kHz 100kHz 1MHz 10MHz
0
1
2
3
4
5
Frequency
Vout peak (V)
3rd Order Intermodulation (2 tones : 180kHz and 280kHz)
-70
-75
80kHZ
IM3 (dBc)
-80
-85
380kHZ 640kHZ 740kHZ
-90 0 1 2 3 4 5
Vout peak (V)
measurement conditi ons: Vcc=6V, Rload=500, Tamb=25C
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TS652
PACKAGE MECHANICAL DATA 14 PINS - PLASTIC MICROPACKAGE (SO)
Millimeters Dim. Min. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 0.1 0.35 0.19 0.5 45 (typ.) 8.55 5.8 1.27 7.62 3.8 4.6 0.5 4.0 5.3 1.27 0.68 8 (max.) 0.150 0.181 0.020 8.75 6.2 0.336 0.228 Typ. Max. 1.75 0.2 1.6 0.46 0.25 Min. 0.004 0.014 0.007
Inches Typ. Max. 0.069 0.008 0.063 0.018 0.010 0.020 0.344 0.244 0.050 0.300 0.157 0.208 0.050 0.027
Note : (1) D and F do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.066 inc) ONLY FOR DATA BOOK.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infring ement of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change witho ut notice. This publ ication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life suppo rt devices or systems withou t express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www. st.com
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