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| PRELIMINARY WTS701 WINBOND SINGLE-CHIP TEXT-TO-SPEECH PROCESSOR The information contained in this datasheet may be subject to change without notice. It is the responsibility of the customer to check the Winbond USA website (www.winbond-usa.com) periodically for the latest version of this document, and any Errata Sheets that may be generated between datasheet revisions. -1- Publication Release Date May 2003 Revision 3.09 WTS701 1. GENERAL DESCRIPTION The WTS701 is a high quality, fully integrated, single-chip Text-to-Speech solution that is ideal for use in applications such as automotive appliances, GPS/navigation systems, cellular phones and other portable products or accessories. The WTS701 product accepts ASCII (Unicode and Big5 for Mandarin) input via a SPI port and converts it to spoken audio via an analog output or digital CODEC output. The WTS701 integrates a text processor, smoothing filter and multi-level memory storage array on a single-chip. Text-to-speech conversion is achieved by processing the incoming text into a phonetic representation that is then mapped to a corpus of naturally spoken word parts. The synthesis algorithm attempts to use the largest possible word unit in the appropriate context to maximize natural sounding speech quality. The speech units are stored uncompressed in a multi-level, non-volatile analog storage array to provide the highest sound quality to density trade-off. This unique, single-chip solution is made possible through Winbond's patented multilevel storage technology. Voice and audio signals are stored directly into solid-state memory in their natural, uncompressed form, providing superior quality voice reproduction. The chip can be programmed through the SPI port, allowing downloading of different languages and speaker databases when made available by Winbond. -2- WTS701 2. FEATURES * Fully Integrated Solution Single-chip compact text-to-speech translation No algorithm development required Selectable digital and analog audio output Simple SPI interface Reprogrammable solution enables loading different voice or language * Text-To-Speech Algorithm Characteristics High quality speech synthesis using speech element concatenation Winbond's standard 100-year speech retention Audio stored as uncompressed analog waveform - industry's highest quality and most natural sounding * Easy to Use and Control Real time conversion for streaming text General text preprocessing and normalization User customization for special characters such as SMS icons and chat emoticons User customization for application specific abbreviations * Language Support Support U.S. English and Mandarin (Beijing dialect) Other languages in development or in planning * Device Management Accepts ASCII, Unicode or Big5 streaming text 256-byte text buffer Playback of Phonetic Alphabet Variable speed playback Control of pitch change Supports Power Down mode. Supports Pause and Resume, Stop and Finish text conversion commands Embedded characters support to control speed, volume, case sensitivity, and silent behavior * Peripheral Control 16-bit linear PCM slave interface output support SPI serial port for control commands and status report to system's host controller Hardware handshake control signals Analog audio output with 8 speaker driver, digital volume control and line level o/p Analog audio input (AUXIN) for driving external audio to the speaker * Low Power Consumption +2.7 to +3.3V (VCC) Supply Voltage Operating Current: ICC Convert = 35 mA (typical) Standby Current: ISB < 1A (typical) * Device Characteristics Available in 56-lead TSOP package Industrial temperature range (-40C to +85C) 3V/5V logic tolerance -3- Publication Release Date: May 2003 Revision 3.09 WTS701 3. BLOCK DIAGRAM 3.1. WTS701 BLOCK DIAGRAM CS\ SS\ MOSI MISO SCLK R/B\ INT\ XTAL1 XTAL2 SPI INTERFACE MLS CONTROL LOGIC FLASH CODESTORE MEMORY (ROM) PROCESSOR RESET CLOCK GENERATION RAM HIGH VOLTAGE GENERATION MLS PHOENEME MEMORY AUX OUT AMP AUX OUT REFERENCE GENERATION Spkr. AMP SP+ SP- ANALOG SIGNAL AUXIN AUX AMP CONDITIONING 13 BIT CODEC LINEAR/ 2'S COMPLEMENT Power Conditioning VFS VDX VCLK VCCA VSSA VSSA VSSD VSSD VCCD VCCD ATT CAP Figure 1. WTS701 Block Diagram. -4- WTS701 3.2. WTS701 TYPICAL APPLICATIONS Baseband Processor WTS701 CS\ SS\ MOSI MISO SCLK R/B\ INT\ VFS VCLK VDX CODEC HOST Controller FS CL DIN DOUT AUXOUT AUXIN SP+ SP- Figure 2. WTS701 Configuration for Digital (CODEC) Environment. WTS701 CS\ SS\ MOSI MISO SCLK R/B\ INT\ VFS VCLK VDX HOST Controller AUXOUT AUXIN SP+ SP- Line out Line in Figure 3. WTS701 Configuration for Analog Environment -5- Publication Release Date: May 2003 Revision 3.09 WTS701 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 3 3. BLOCK DIAGRAM .............................................................................................................................. 4 3.1. WTS701 Block Diagram ............................................................................................................... 4 3.2. WTS701 Typical Applications....................................................................................................... 5 4. TABLE OF CONTENTS ...................................................................................................................... 6 5. PIN CONFIGURATION ....................................................................................................................... 8 6. PIN DESCRIPTION ............................................................................................................................. 9 7. FUNCTIONAL DESCRIPTION.......................................................................................................... 11 7.1 Text-To-Speech Mechanism ....................................................................................................... 12 7.1.1 Text Normalization ................................................................................................................ 12 7.1.2 Words-to-Phoneme conversion ............................................................................................ 12 7.1.3 Phoneme Mapping ................................................................................................................ 12 7.2 Physical Interface ........................................................................................................................ 13 7.2.1 Clocking Requirements......................................................................................................... 13 7.2.2 Power Down Mode................................................................................................................ 14 7.2.3 Power and Grounding ........................................................................................................... 14 7.2.4 SPI Interface ......................................................................................................................... 15 7.2.5 Flow Control Interface ........................................................................................................... 16 7.2.6 The CODEC Interface ........................................................................................................... 16 7.2.7 The Analog Interface............................................................................................................. 17 7.2.8 Resetting ............................................................................................................................... 18 7.3 Communication Protocol.............................................................................................................. 19 7.3.1 Command Classes................................................................................................................ 20 7.3.2 Status Register...................................................................................................................... 21 7.3.3 Interrupt Handler ................................................................................................................... 22 7.3.4 BCNT -- Byte Count Register................................................................................................ 23 7.3.5 Command Acceptance.......................................................................................................... 23 7.3.6 Data Acceptance................................................................................................................... 23 7.4 Commands Overview .................................................................................................................. 23 7.4.1 Command Description .......................................................................................................... 26 7.4.2 Illegal Commands ................................................................................................................. 37 7.4.3 Configuration Registers ........................................................................................................ 37 7.4.4 System Operation ................................................................................................................. 41 7.4.5 Initialization and Configuration.............................................................................................. 43 -6- WTS701 7.4.6 Converting Text..................................................................................................................... 43 7.5 SPI Interface ................................................................................................................................ 46 7.5.1 SPI Transactions................................................................................................................... 46 7.6 CODEC Interface......................................................................................................................... 49 7.7 Control Characters....................................................................................................................... 52 7.7.1 Phonetic Alphabet Playback ................................................................................................. 52 7.7.2 Speed Change ...................................................................................................................... 54 7.7.3 Volume Change .................................................................................................................... 55 7.7.4 Case Sensitivity..................................................................................................................... 55 7.7.5. Pause Control ...................................................................................................................... 55 7.8 Customizing Abbreviations .......................................................................................................... 56 7.8.1 Abbreviation Data Format ..................................................................................................... 56 7.8.2 Abbreviation Table Format.................................................................................................... 57 7.8.3 Command Execution............................................................................................................. 57 7.9 Device Programming ................................................................................................................... 58 7.10 Text-To-Speech Processor Commmands - Quick Reference Table........................................ 59 7.10.1 Text Input Format................................................................................................................ 64 7.10.2. Buffer length limit ............................................................................................................... 65 7.10.3. Undefined characters......................................................................................................... 65 8. TIMING WAVEFORMS ..................................................................................................................... 66 8.1 SPI Timing Diagram..................................................................................................................... 66 8.2 CODEC Timing Diagrams ........................................................................................................... 68 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 70 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 71 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 74 12. PACKAGE DRAWING AND DIMENSIONS .................................................................................... 75 13. ORDERING INFORMATION........................................................................................................... 76 14. VERSION HISTORY ....................................................................................................................... 77 -7- Publication Release Date: May 2003 Revision 3.09 WTS701 5. PIN CONFIGURATION The following sections detail the pins of the WTS701 processor. Table 1 shows all the pins and the signals that use them in different configurations. It also shows the type and direction of each signal. Figure 4 shows the physical pin out of the 56-pin TSOP package. NC VS S A VC LK VF S VDX M IS O XT AL2 XT AL1 VS S D VS S D VC C D VC C D INT \ M OS I SS\ S C LK NC NC NC NC NC NC NC NC CS\ R /B \ R ES ET NC 1 2 3 4 5 6 7 8 9 10 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 NC NC AUXOUT NC AUXIN NC NC NC VC C A NC SP+ NC VS S A NC SPNC AT T C AP NC NC NC VS S A NC NC NC NC NC NC NC W TS701 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Figure 4. 56-pin TSOP Package Connection Diagram. -8- WTS701 6. PIN DESCRIPTION Table 1. WTS701 Pin Signal Assignment. PIN NO. 2,36,44 3 4 5 SYMBOL VSSA VCLK VFS VDX I/O G I I O Analog Ground pins. CODEC master clock CODEC frame synchronization signal CODEC data output. This pin puts data out in the linear PCM unsigned or 2's complement format. It is tri-stated until the user requests a CONVERT operation. SPI Master In, Slave Out pin. Serial data line used to communicate with SPI master. Pin is tri-state when SS =1. 7 8 XTAL2 XTAL1 O I CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. The clock to the WTS701 processor is configured by a clock configuration register, which is set by the host processor during the initialization phase. Digital Ground pin. Positive Digital Voltage Supply pin. These pins carry noise generated by internal clocks in the chip. They must be independently bypassed to Digital Ground to ensure correct device operation and not connected together. Interrupt Output; an open drain output that indicates that the device wishes an interrupt service. The device can request an interrupt when it finishes an operation or needs more data to process. Under what conditions the device generates an interrupt can be configured through the user configuration registers. This pin remains LOW until a Read Interrupt command is executed. SPI Master Out, Slave In. Serial data input from Master and Open Drain SPI Slave Select input. This is an active LOW input used to select the device to respond to an SPI transaction. SPI Serial clock input. Chip Select (active LOW) Pin must be LOW to access WTS701 device. Ready/busy signal; This pin defaults HIGH indicating the device is ready for data transfer. The pin is driven LOW to handshake a pause in SPI data transfer and Open Drain. FUNCTION 6 MISO O 9,10 11,12 VSSD VCCD G P 13 INT O 14 15 16 25 26 MOSI SS I I I I O SCLK CS R/ B -9- Publication Release Date: May 2003 Revision 3.09 WTS701 PIN NO. 27 40 42 46 48 SYMBOL RESET ATTCAP SPSP+ VCCA I/O I I/O O O P Global reset signal. AutoMute Capacitor Pin. Should have a 4.7uF capacitor to VSSA. Differential Negative Speaker Driver Output. Differential Positive Speaker Driver Output. Positive Analog Voltage Supply pin. This pin supplies the LOW level audio sections of the device. It should be carefully bypassed to Analog Ground to ensure correct device operation. Analog input pin. This pin should be capacitively coupled. See page 73 for example. Analog Output for single ended output from the device. Not Connected - must be floating. FUNCTION 52 54 1,1724,2835,3739,41,43, 45,47,4951,53,5556 AUXIN AUXOUT NC I O Note: TYPE I:Input, O:Output, I/O bi-directional, P:Power, G:Ground - 10 - WTS701 7. FUNCTIONAL DESCRIPTION As a real System-On-Chip solution, the WTS701 performs the overall control functions for host controller and text-to-speech processing. The WTS701 system architecture consists of the following functions: * * * * * * Serial interface to monitor the SPI port and interpret commands and data Text normalization module to pre-process incoming text into pronounceable words Words to phoneme translator, which converts incoming text to phoneme codes Phoneme mapping module that maps incoming phonemes to words, sub-words, syllables or phonemes present in the MLS memory Volume and speed adjustments Digital and analog output blocks for off-chip usage The WTS701 system performs text-to-speech synthesis based on concatenative samples. The units for concatenation can vary from whole words down to phoneme units. The convention is that the larger the sub-word unit used for synthesis the higher the quality of the speech output. A corpus of pre-recorded words is stored in Winbond's patented multilevel storage (MLS) memory and a mapping of the various sub-word parts is held in a lookup table. The speech creation is achieved by concatenation of these speech elements to produce words. The system process flow is shown in Figure 5. WTS701 Serial Text, symbols & Control Text Normalization Words to Phoneme Phoneme Mapper Digital output MLS Memory Speech Analog output Figure 5. WTS701 System Process Flow. - 11 - Publication Release Date: May 2003 Revision 3.09 WTS701 7.1 TEXT-TO-SPEECH MECHANISM The text to speech component of the system consists of three principal blocks: * * * Text normalization Word to phoneme conversion Phoneme mapping 7.1.1 Text Normalization Text normalization involves the translation of incoming text into pronounceable words. It includes such functions as expanding abbreviations and translating numeric strings to spoken words. It involves a certain amount of context processing to determine correct spoken form. In addition, the WTS701 looks into the abbreviation list stored in the device's internal memory and converts acronyms, abbreviations or special characters (such as Instant Messaging icons or emoticons) into the appropriate text representation. The default abbreviation list supported by the WTS701 is a general one that cannot be modified by the user to match the domain that the text is being loaded from. But the default list can be overridden by the user abbreviation list. This enables a flexibility of adding abbreviation specifically for the text either by the developer or even the end user to best customize the product for its preferences. Instant Messaging or Short Messages Service (SMS) unique characters are supported through this functionality as well, defining the icon, ASCII/Unicode/Big5 text, and its replacement. The default abbreviation list supported is described in the specific language release letter. 7.1.2 Words-to-Phoneme conversion Once the data stream has been translated to pronounceable words, the system next determines how to pronounce them. This function is obviously highly language dependent. For a language such as English it is impossible to break this task down to a set of definitive rules. The task is achieved by a combination of rule based processing together with exception processing. 7.1.3 Phoneme Mapping This algorithm maps phoneme strings into the MLS phonetic inventory. This task falls into two portions. First, the word must be split into sub-word portions. This splitting must be done at appropriate phonetic boundaries to achieve high quality concatenation. Once a sub-word unit is determined, the inventory is searched to determine if a match is present. A matching weight is assigned to each match depending on how closely the phonetic context matches. Each sub-word has a left and right side context to match as well as the phoneme string itself. If no suitable match is found in the inventory, then the sub-word is further split in a tree like manner until a match is found. The splitting tree is processed from left to right and each time a successful match occurs the address and duration of the match in the corpus is placed in a queue of phonetic parts to be played out the audio interface. - 12 - WTS701 7.2 PHYSICAL INTERFACE The following sections describe the physical pin properties and the timing associated with the physical interface to the device. Note that all input pins are 3V and 5V tolerant, except for the CS signal which is only 3V tolerant. 7.2.1 Clocking Requirements The WTS701 processor can receive its clock from either an external clock source or a crystal oscillator. The XTAL1 and XTAL2 pins provide the crystal interface to the device. The clock to the WTS701 processor is configured by a clock configuration register, which must be set by the host processor during the initialization phase. Figure 6 below shows how to connect the WTS701 to a crystal oscillator. An external clock can be connected to the WTS701 providing the clock source for the system, as shown in Figure 6. C1 = C2 = 15pF X1 = 24.576MHz WTS701 C1 XTAL1 X1 XTAL2 CLK IN WTS701 XTAL1 C2 XTAL2 Figure 6. Clock Generation. Suggested Crystal Specification: F = 24.576 MHz Fundamental Mode Operation CL = 16 pF ESR = 60 maximum - 13 - Publication Release Date: May 2003 Revision 3.09 WTS701 7.2.2 Power Down Mode Upon application of power, the WTS701 will enter the RESET state and then be in a POWER DOWN state. In the POWER DOWN mode, only Class0 SPI commands are valid. (See subsection 7.3.1). The Power Down status of the device can be determined with a RDST (Read Status) command, specified by the RDY bit in STATUS BYTE 0. Issuing the PWDN (Power Down) command to the WTS701 processor will return the processor to the POWER DOWN mode. In POWER DOWN mode the external crystal oscillator is shut off and the processor is deactivated. POWER DOWN mode is exited by issuing a PWUP (Power Up) command to the WTS701. The PWUP command should be preceded by a SCLC (Set Clock) command to ensure correct clock configuration. 7.2.3 Power and Grounding The WTS701 can operate over 2.7V to 3.3V supply voltage range. The power supply and ground pins (VCCA, VCCD, VSSA, VSSD) should be carefully bypassed as close to the chip as possible to ensure high quality audio. In addition, ATTCAP pin should have a 4.7 F capacitor connected to ground. This pin must NOT be left floating. The pins that are marked as NC (Not Connected), MUST be left floating. VCCA, VCCD (Voltage Inputs) To minimize noise, the analog and digital circuits in the WTS701 device use separate power busses. These +3.0 V busses lead to separate pins. For optimal noise immunity, tie the VCCD pins together as close as possible and decouple both supplies as near to the package as possible. VSSA, VSSD (Ground Inputs) The WTS701 series utilizes separate analog and digital ground busses. The analog ground (VSSA) pins should be tied together as close to the package as possible and connected through a lowimpedance path to power supply ground. The digital ground (VSSD) pin should be connected through a separate low-impedance path to power supply ground. These ground paths should be large enough to ensure that the impedance between the VSSA pins and the VSSD pin is less than 3. The backside of the die is connected to VSSD through the substrate resistance. NC (Not Connect) These pins MUST not be connected to the board at any time. Connection of these pins to any signal, ground or VCC may result in incorrect device behavior or cause damage to the device. - 14 - WTS701 7.2.4 SPI Interface Communications with the WTS701 is conducted over the SPI serial communications port. The device responds to a command when the Chip Select signal ( CS ) is LOW and addressed by an active LOW signal on the SS (Slave Select) pin. Under this condition, it accepts data on the MOSI input, which is clocked in on rising edges of the serial clock (SCLK) signal. Concurrently, valid data from the WTS701 device to the bus master is available on MISO for the HIGH period of SCLK. The protocol implemented on the WTS701 defines that the first two bytes of data sent in an SPI transaction is a command word. A transaction is defined as the SPI transfers conducted while SS is LOW, the transaction ends when SS returns HIGH. A list of available commands can be found in subsection 7.10 (Text-To-Speech Processor Commands Quick Reference Table). The data flow over the SPI interface is MSB first, both in and out of the WTS701. All Input pins are 3V and 5V tolerant, except for the CS signal which is only 3V tolerant. The following is a description of the WTS701 SPI interface signals: SCLK (Serial Clock) The Serial Clock line is a digital input. It is driven by the SPI master and controls the timing of the data exchanged over the SPI data lines, MOSI and MISO. The maximum frequency for this pin is 5 MHz. SS (Slave Select) The Slave Select line is an active LOW digital input. It is driven by the SPI master and acts as a chip select line. The device only responds to SPI transactions when this line is selected (LOW) and then raised HIGH after SPI communication ends. CS (Chip Select) The Chip Select line is an active LOW digital input. It can be driven by the host controller to enable SPI transactions to the device. Normally this pin is tied LOW unless more than one device is to share the same SS signal. MOSI (Master Out, Slave In) The MOSI line is a digital input. MOSI is driven by the SPI master. It provides data transfer, MSB first, from the master to the slave. (See page 64) MISO (Master In, Slave Out) The MISO line is an open drain digital output. When SS is HIGH, this pin is tri-state. When SS is LOW, MISO is driven by the device. It provides serial data transfer, MSB first, from the slave to the master. - 15 - Publication Release Date: May 2003 Revision 3.09 WTS701 7.2.5 Flow Control Interface In addition to the SPI interface, the WTS701 has two control lines to facilitate data transfer and host communications. The INT (interrupt) pin is used by the WTS701 to request an interrupt service from the host controller. The interrupt types that the device generates are controlled by the communications control register command (SCOM). The R/ B (ready/busy) pin is used to control the flow of data across the SPI bus. When this signal is HIGH, the device can accept more data. When it is LOW, SPI transactions must be paused or terminated. INT (Interrupt) INT is an open drain output pin. The WTS701 interrupt pin goes LOW and stays LOW when an interrupt event has occurred, as defined by the SCOM command. The interrupt is cleared when a RINT (read interrupt) command is executed. The status register defines what type of interrupt has occurred. R/ B (Ready/Busy Signal) The R/ B line is an output open drain pin used to control data transfer rate across the SPI port. The line is used as a handshake signal to the SPI Master to indicate when the device is ready for more data. When HIGH, the master is free to send more data. When LOW, the device is busy and cannot accept more data. 7.2.6 The CODEC Interface The WTS701 provides an on chip interface for digital environment systems, supporting slave CODEC interface mode. The WTS701 CODEC interface is controlled by an external source hence the WTS701 only transmits data. Thus, it is effectively an analog-to-digital converter. Each analog sample is converted to 10 bit digital word. This digital word is transmitted with the MSB first. Since the host expects either 13 or 16 bit data in the short frame format, either three or six zeros are appended as the LSB. It interfaces to the baseband CODEC via the VCLK, VFS and VDX lines. Refer to Figure 2, for more information about the connection between the WTS701 and a CODEC. All Input pins are 3V and 5V tolerant. The following is a description of the WTS701 CODEC interface signals: VCLK (CODEC Clock Line) The CODEC clock line supplies the sampling clock to the internal CODEC. This is a digital input and expects a 512kHz--2.048MHz clock. - 16 - WTS701 VFS (CODEC Synchronization Line) The CODEC synchronization line supplies a frame synchronization signal to the internal CODEC. This is a digital input. After receipt of a synchronization pulse, the CODEC will output data on the VDX line. The VFS line expects an 8kHz sample rate and supports both short frame and long frame synchronization signal. VDX (CODEC Data Transmit Line) The CODEC data transmit line is a digital output that places digital audio data onto the CODEC bus. The line is in a tri-state condition until the device is due to transmit data. The data output from the VDX line is selected by the SCOD Command. When WTS701 places data on the VDX line, it is required that the VFS line should be in tri-state condition when another device is connected to the CODEC as well. 7.2.7 The Analog Interface The WTS701 provides an on-chip analog interface for audio output via an 8 speaker driver or an output buffer capable of driving a 5k load. Additionally, an analog input (AUXIN) allows an audio signal to be fed through the WTS701 chip to either output device. The command SAUD configures the analog path. A digitally controlled attenuator provides volume control via the SVOL command. The following is a description of the analog pins: AUXIN (Analog Input) The AUXIN is an additional audio input to the WTS701. This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB) (See Table 2). Additional gain is available in 3 dB steps (controlled by the SAUD Command) up to 9 dB. The use and equivalent circuit of the input amplifier is shown in Figure 7. (Must be AC coupled) Internal to the device Rb CCOUP = 0.1 F Ra 1 NOTE: fCUTOFF= 2R C a COUP Figure 7. AUXIN Input Amplifier. - 17 - Publication Release Date: May 2003 Revision 3.09 WTS701 Table 2. AUXIN Gain Settings. 0TLP Input VP-P1 AUD Register AIG1 AIG0 Gain2 Gain2 (dB) Resistor Ratio (Rb/Ra) 40.1 / 40.1 47.0 / 33.2 53.5 / 26.7 59.2 / 21 Speaker Out VP-P3 0.694 0.491 0.347 0.245 1 2 0 0 1 1 0 1 0 1 1.00 1.41 2.00 2.82 0 3 6 9 1.388 1.388 1.388 1.388 OTLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping. From AUXIN to AUXOUT. Measured differentially at SP+/SP-. 3 AUXOUT (Analog Output) The AUXOUT is an audio output pin used to provide an analog output of the synthesized speech from the WTS701. It drives a minimum load of 5 k up to a maximum of 1 V p-p. The AC signal is superimposed on approximately 1.2 VDC bias and must be capacitively coupled to the load. This output stage may be powered down by clearing the AOPU bit via the SAUD command. SP +, SP(Speaker +/-) This is the speaker differential output circuit. It is designed to drive an 8 speaker connected across the speaker pins up to a maximum of 23.5 mW power. This stage has selectable gains of 1.32 and 1.6, which can be chosen through the SPG bit via the SAUD command. These pins are biased to approximately 1.2 VDC and, if used single-ended, must be capacitively coupled to their load. Do NOT ground the unused pin. This output stage may be powered down by clearing the SPPU bit via the SAUD command. ATTCAP (AutoMute Attenuator Capacitor) This pin provides a capacitor connection for setting the AutoMute. It should have a 4.7 F capacitor connected to ground and it cannot be left floating. The AutoMute circuit reduces the amount of noise present in the output during quiet pauses. 7.2.8 Resetting The chip has an internal power-on reset circuit that ensures correct initialization upon application of power. The reset pin signal must be held HIGH for 0.5s to achieve a reset (see Figure 8) and to put the WTS701 in the RESET state. Once the WTS701 completes the reset, it will enter the POWER DOWN mode. Before issuing active commands, a clock configuration and device power up command must be issue in the POWER DOWN mode. Issuing a Reset command (RST) resets the WTS701 processor to the initial POWER DOWN state. Applying the reset pin, while the chip is active, allows the host processor to reset the WTS701 to its default values and the IDLE state. - 18 - WTS701 T res et T re s et > 0.5 s R ESET Figure 8. Reset Condition Timing. 7.3 COMMUNICATION PROTOCOL The WTS701 is controlled by a series of SPI transactions to send commands to the device. The general format of an SPI transaction is shown in Figure 9. A transaction is always started by sending a command word. The command word consists of a command byte followed by a command data byte. At the same time, the status register is shifted out on the MISO line. What follows depends on what command is sent. The general case is that following the command word, up to n-bytes of data can be sent to the device and n-bytes can be read from the device. An SPI transaction is finished when SS is returned to the HIGH condition. MSB 7 MOSI CMD BYTE 7 0 STATUS BYTE 0 0 7 CMD DATA 7 0 STATUS BYTE 1 7 DATA0 0 7 DATA0 0 7 DATA1 0 7 DATA1 LSB 0 DATAn 0 DATAn MISO time Figure 9. SPI Transaction Format. - 19 - Publication Release Date: May 2003 Revision 3.09 WTS701 7.3.1 Command Classes The SPI transactions to the WTS701 fall into four classes. The four classes represent variations in how the command, and any associated data, is handled. The class of a command is defined by the two most significant bits of the command byte. A summary of the command classes is given below Class 0 Commands These are commands that are executed irrespective of the state of the WTS701. That is, the command will execute even if the device is busy or powered down. These commands are executed internally by a hardware command interpreter. All commands not of class 0 require that the WTS701 be in a powered up state. Example of class 0 command is the Read Status (RDST) command. Class 1 Commands Class 1 commands require interpretation by the internal firmware of the WTS701. Class 1 commands consist only of a command byte and command data byte. Any further data sent in a transaction is ignored. Class 1 commands are most often used for setting a configuration register in the device or sending commands that have no data such as the conversion pause (PAUS) command. Class 2 Commands Class 2 commands have associated data. After the command word, any data bytes following are loaded into an internal FIFO buffer for processing. If this FIFO becomes full, the R/ B signal is asserted (LOW) indicating that the host must pause data transfer. An alternative to monitoring the R/ B line, the R/ B bit of the status register can be monitored instead (see subsection 7.3.2) or via the RDST command. The R/ B bit cannot be used for intra-byte flow control, e.g. if a string of characters is sent, only every other byte is checked. Class 3 Commands Class 3 commands have data to return to the host. The R/ B line will go to busy immediately following the command word indicating that the WTS701 is fetching the requested data. Data is put into the BCNT0 and BCNT1 (see subsection 7.3.4) registers and is read out in the two subsequent bytes after R/ B is released. If more than two bytes are returned from the command, R/ B will again be asserted until data is ready to read. The primary Class 3 commands are to read the contents of internal configuration registers such as RREG command. - 20 - WTS701 7.3.2 Status Register The WTS701 has a sixteen-bit status register whose value is returned to the host controller during the command word. For class 2 commands, the status register is repeatedly returned every two bytes. This status register provides the host with information regarding the current status of the chip. The host can decide on required actions with this information. The Status Register is echoed back by all commands. Table 3. Status Bytes. Bit 7 Status Byte 0 Status Byte 1 ICNT R/ B Bit 6 IBUF Reserved Bit 5 ICNV Reserved Bit 4 COD Reserved Bit 3 BFUL Reserved Bit 2 BEMP IABB Bit 1 CNVT Reserved Bit 0 RDY ICMD The contents of the status bytes are described in Table 4. - 21 - Publication Release Date: May 2003 Revision 3.09 WTS701 Table 4. Status Bit Description. Byte Bit Name RDY Bit # 0 CNVT 1 Ready to accept commands. After the device has been powered up, this bit is set after the Power Up latency delay. Converting. This bit is set anytime while the conversion process is running. If this bit is clear when a convert command is sent, the count in the Count register is set to 0. The text input buffer is empty. This bit is set anytime the input buffer is empty. The text input buffer is full. This bit is cleared after 128 bytes become available in the input buffer. CODEC is enabled. This is set when the CODEC has been enabled by the SCOD command. Conversion finished interrupt has occurred. To stop CODEC transmission or Power Down the analog outputs an IDLE command should be sent. This bit is cleared by RINT command. The input text buffer been filled above the defined threshold and then gone below the defined threshold. The buffer threshold level is set by the SCOM command. If set by the SCOM command, the INT pin will also go LOW. This bit is cleared by RINT command. BEMP BFUL Status Byte 0 2 3 4 5 COD ICNV IBUF 6 ICNT 7 Count interrupt has occurred. This interrupt is generated every time a word has been spoken if activated by the SCOM command. This bit is cleared by RINT command. Command was ignored. Anytime ICMD is set, the transaction must revert to a single word command and the command must be resent. Any data sent will be ignored. Abbreviation interrupt has occurred, abbreviation add or abbreviation delete has been completed. Now the ENTER_RRSM command can be sent. Current state of the R/ B pin. If this bit is 0, any data sent will be ignored. ICMD Status Byte 1* 0 IABB 2 R/ B *5 bits are reserved. 7 7.3.3 Interrupt Handler If an interrupt has occurred, no further interrupts will be registered until the first interrupt has been cleared. Only one interrupt can be active at any time. The RINT command will read and clear pending interrupts while the RDST command will read interrupts without clearing them. Make sure that all interrupts that are not being used are masked by clearing the corresponding bits in the COM register. - 22 - WTS701 7.3.4 BCNT -- Byte Count Register The byte count register (BCNT) is a tool for the host to keep track of where in a conversion the WTS701 is. When a new conversion is started, the byte count register is reset to zero. As each word (as defined by white-space separated characters) is spoken, the byte count register is updated to point to the first character of the next word to be spoken. In this way, the host can position a new conversion if the user wishes to repeat or skip text. The BCNT register is sent with BCNT1 (MSB) first and BCNT0 (LSB) second. 7.3.5 Command Acceptance The WTS701 processes commands and data as they are sent to the device. Under certain conditions the device will not be ready to accept a new command or data. If the device has not finished processing the previous command, the ICMD bit of the status register will be set. If this bit is set, it implies that device is not in a position to accept the command being sent and that it will be ignored. The host should monitor this bit when a command is sent and, if it is detected, the SPI transaction should be terminated at the end of the command word. The host can then resend the command until the command is accepted. 7.3.6 Data Acceptance The WTS701 has an eight byte FIFO to buffer data from the SPI port to the internal processor. During a conversion, data is read from this FIFO into an internal RAM data buffer. If SPI transmission is too fast for the WTS701 to keep up with, the R/ B line will be asserted (LOW) to pause data transfer. Alternatively, the STATUS register can be monitored for the state of the R/ B signal. 7.4 COMMANDS OVERVIEW Control of the WTS701 is implemented through a 16-bit command word. The command word is always the first word to follow the falling edge on the SS signal. The command word consists of the command byte followed by the command data byte. Many commands do not require a command data byte, although one must be sent. For commands that have no data, the command data byte is a `don't care'. Commands fall into five categories. Commands that control an operational synthesis function of the text-to-speech processing, commands that modify internal configuration registers, commands that change system state, commands that read internal status registers, and customization commands. - 23 - Publication Release Date: May 2003 Revision 3.09 WTS701 Status Commands Table 5. Status Opcodes. The WTS701 has three read-only registers accessed by the opcodes, which are shown to the right. * Opcode Mnemonic Function 0x04 RDST RINT RVER Read Status Register Read Interrupt Register Device Version 0x06 The Read Status Register returns the device's 0x12 operational status and the numbers of bytes that have been converted. * * The Read Interrupt Register returns the same status data and clears any of the interrupt status bits that are set. The Version Register returns the hardware and firmware version of the chip. System Commands Table 6. System Opcodes. The WTS701 responds to various system commands that change the state of the system, namely: * Opcode Mnemonic Function 0x02 0x40 0x10 PWUP PWDN RST Power Up Power Down Reset The Power Up command wakes up the device from POWER DOWN mode. * * * 0x57 IDLE Go Idle The Power Down command requests that the device enter the POWER DOWN mode. The Reset command resets the device (see subsection 7.4.4). The Idle command puts WTS701 processor in IDLE mode - 24 - WTS701 Synthesis Commands Table 7. Synthesis Opcodes. The synthesis commands affect the text-to-speech synthesis. They are detailed in the table to the right. The basic commands are: * Start a conversion * Pause the conversion * Resume the conversion * Stop the conversion * Finish conversion at the end of the current word. * Finish the conversion at the end of the buffer * Volume up/down * Speed up/down the text-tospeech conversion Opcode Mnemonic Function 0x81 0x49 0x4A 0x4B 0x4D 0x4C 0x53 0x54 0x55 0x56 CONV PAUS RES ST FINW FIN VLUP VLDN SPUP SPDN Start Converting Pause Conversion Resume Conversion Stop Conversion Finish Word Finish Buffer Volume Up Volume Down Speed Up Conversion Slow Down Conversion Configuration Commands Table 8. Configuration Opcodes. The WTS701 has several configuration registers. The commands are: * Opcode Mnemonic Function The COM configuration register governs the behavior of how the chip uses the INT and R/ B hardware lines to communicate with the host 0xC0 0x4E 0x4F 0x50 0x51 0x52 0x14 0x77 RREG SCOM SCOD SAUD SVOL SSPD SCLC SPTC Read Configuration register COM Configuration register CODEC Configuration register AUDIO Configuration register VOL Configuration register SPEED Configuration register CLC (Clock) register Configuration * The CODEC register configures the mode of the digital audio output The AUDIO register sets parameters of the analog audio path * Set Speech Pitch * * * * The VOLUME register sets the volume level of output The SPEED register sets the speed level of output speech The CLC register sets the master clock frequency of the device The SPTC command sets speech pitch - 25 - Publication Release Date: May 2003 Revision 3.09 WTS701 Customization Commands Table 9. Customization Opcodes. The WTS701 has the ability for the user to customize the way in which it responds to certain text strings. This is done by way of an abbreviation table. The customization opcodes allow the user to interrogate and modify the abbreviation table. Opcode Mnemonic Function 0xC8 0xC9 0xC7 0xAF 0x83 0x0C ABBR_NUM ABBR_RD ABBR_MEM ABBR_ADD ABBR_DEL ENTER_RRSM Get number of abbrev. entries Read abbreviation table Get number of free bytes. Add abbrev. entry Delete abbrev. entry Swap memory 7.4.1 Command Description The following section list all the standard commands that can be executed on the WTS701. PWDN Go to POWER DOWN Mode This command puts the WTS701 processor in power-down mode. This is a single word command therefore no data is required for this command. The Power Down command places the WTS701 device into its lowest power consumption mode. In POWER DOWN mode, the device will only respond to a Power Up command (PWUP) and Read Status (RDST) command. As soon as Power Down sequence has ended, the RDY flag in the status word is cleared. PWDN Byte Sequence: Description: PWUP Power Up Class WTS701 1 Type I 0x40 0x00 Status Byte 1 Host controller Status Byte 0 Put the WTS701 processor in power-down mode. This command wakes up the WTS701 processor to IDLE state. The result of this command is that the WTS701 starts the power up sequence, which leads to bringing up internal supplies, resetting the processor, all configuration registers are initialized to their default values and entering IDLE state. As soon as power up sequence has ended, the RDY flag in the status word is asserted. The SCLC command must be sent BEFORE PWUP. - 26 - WTS701 PWUP Byte Sequence: Description: CONV Class WTS701 0 Type I 0x02 0x00 Status Byte 1 Host controller Status Byte 0 Wake up the WTS701 processor to IDLE state. Convert The convert command starts the text to speech conversion process. The convert command is followed by ASCII text data. The device has a buffer of 256 bytes. When this buffer is full, the chip pulls the R/ B line LOW and sets the BFUL bit in the status word indicating that the WTS701 buffer manager is in the buffer full condition. The WTS701 remains in the buffer full condition until the input buffer has been emptied of half the buffer space (128 bytes). When the buffer is full, the Host may do one of three things: 1. The Host may end the command at that point, then poll the BFUL bit of the SPI status register until it is clear, and then send new CONV commands with the additional ASCII text data. 2. The Host may also continue the command (keep SS LOW) and wait for the R/ B pin to go HIGH. As each word is processed by the WTS701, space will become free in the buffer and the R/ B pin will go HIGH until it is full again. 3. The device may also be configured such that it will generate an interrupt to the host when the buffer threshold (set by RCOM command) has been crossed. (See Tables 3 and 4) This allows the host to fill the buffer then wait for the Interrupt to send the additional data. During conversion, the Convert Count Register is updated as each word has been spoken. This register is cleared to zero at power up, and at the beginning of a new conversion process after one has been terminated. A convert command is terminated in several ways: * * Send a finish command (FIN) indicating that the host has finished sending data. In this case, the device finishes converting the text buffer, then stops and enters a wait state. The conversion process will also stop when the EOT (^D, ASCII 0x1A, UNICODE/Big5 0x00 0x1A) character is part of the input text. When the device detects the EOT character, it will continue the conversion process until the buffer is emptied and the final word spoken. Then it will stop and enter the wait state. The finish word command (FINW) will cause the WTS701 device to finish the word currently being spoken, then flush the buffers and enter the wait state. * - 27 - Publication Release Date: May 2003 Revision 3.09 WTS701 The stop command (ST) will cause the WTS701 to immediately stop converting, flush the buffer and enter the wait state. Once the wait state has been entered the device will clear the convert (CONV) bit from the status register and, if enabled, generate an ICVT interrupt. At this stage the CODEC and analog path are still active. To release the CODEC bus, or Power Down the analog path, an IDLE command should be sent to the device. If a convert command is terminated using any of the methods described in this section, another convert command cannot be sent until the previous conversion is completed. The CNVT bit must be polled to determine that conversion is completed before a new conversion can be started. * CONV Byte Sequence: Description: Class WTS701 2 Type 0x81 Stadus Byte 0 III 0x00 Status Byte 1 DATA0 Status Byte 0 ... DATAn ... Status Byte n%2 Host controller Start or continue a conversion process. Data sent is text data for conversion. PAUS PAUSE This command causes a pause of the conversion process. There is no data associated with this command. The pause condition is terminated by the RES (Resume) command PAUS Byte Sequence: Description: Class WTS701 1 Type I 0x49 0x00 Status Byte 1 Host controller Status Byte 0 This command pauses the conversion process. RES RESUME This command causes the conversion to resume if it was paused. There is no data associated with this command RES Byte Sequence: Description: Class WTS701 1 Type I 0x4A 0x00 Status Byte 1 Host controller Status Byte 0 This command resumes conversion after pause. - 28 - WTS701 ST STOP This command immediately stops conversion without finishing buffer, and clears the buffer. ST Byte Sequence: Description: Class WTS701 1 Type I 0x4B 0x00 Status Byte 1 Host controller Stop conversion. Status Byte 0 FINW FINISH WORD This command directs the WTS701 to finish text conversion at the end of the current word. FINW Byte Sequence: Description: Class WTS701 1 Type I 0x4D 0x00 Status Byte 1 Host controller Status Byte 0 This indicates that conversion is to end with the processing of the current word. FIN FINISH This command indicates that no further conversion data is to follow and to stop conversion after processing the current buffer contents. FIN Byte Sequence: Description: Class WTS701 1 Type I 0x4C 0x00 Status Byte 1 Host controller Status Byte 0 Finish conversion after processing the current buffer. - 29 - Publication Release Date: May 2003 Revision 3.09 WTS701 IDLE IDLE This command is executed after the receipt of an end-of-conversion interrupt (ICNV) has occurred. The IDLE command will deactivate all audio outputs and bring the device to the IDLE state. IDLE Byte Sequence: Description: Class WTS701 1 Type I 0x57 0x00 Status Byte 1 Host controller Put WTS701 in IDLE state. Status Byte 0 RDST READ STATUS The Read Status command reads the status word of the device. If two dummy data bytes are also sent, the contents of the byte count register are also returned. Refer to subsections 7.3.2 and 7.3.4 for more information regarding the STATUS register and BCNT register. RDST Byte Sequence: Class 0 Type II 0x00 Status Byte 1 0x00 BCNT 1 0x00 BCNT0 Host controller WTS701 0x04 Status Byte 0 Description: Read Status word of the device. RVER READ VERSION The Read version command reads the WTS701 version information. The software version information is only valid when the device is powered up. RVER Byte Sequence: Description: Class WTS701 0 Type 0x12 II 0x00 Status Byte 1 0x00 HW VER 0x00 SW VER Host controller Status Byte 0 Read WTS701 Software and Hardware versions. - 30 - WTS701 RINT READ INTERRUPT The Read Interrupt command reads the status word of the device, it also clears the status interrupt request flags at the end of the transaction. As a result of this command, all interrupt bits are cleared and INT pin is released. Refer to subsections 7.3.2 and 7.3.4 for more information regarding the STATUS register and BCNT register. RINT Byte Sequence: Description: Class WTS701 0 Type 0x06 II 0x00 Status Byte 1 0x00 BCNT1 0x00 BCNT0 Host controller Status Byte 0 Read status word and clear the status interrupt bits. RREG READ CONFIGURATION REGISTER The read configuration register command reads the configuration register specified in the command data byte. The code 0xNN is the register number and it is described in Table 10 - Configuration Registers, subsection 7.4.2. RREG Byte Sequence: Description: Note: XX = don't care. Class WTS701 3 Type 0xC0 IV 0xNN Status Byte 1 0x00 XX 0x00 REG Host controller Status Byte 0 Read configuration register 0xNN. SCOM SET COM REGISTER Set the COM (interrupt communication) configuration register to value 0xNN. Refer to subsection 7.4.3 describing all configuration registers and the COM register in particular. The Default value of this register after Power-Up or Reset is 0x00. Refer to subsection 7.4.3 Configuration Registers, which describes all register bits. SCOM Byte Sequence: Description: Class WTS701 1 Type I 0x4E 0xNN Status Byte 1 Host controller Status Byte 0 Set the COM (interrupt communication) configuration register to value 0xNN. - 31 - Publication Release Date: May 2003 Revision 3.09 WTS701 SCOD SET COD REGISTER Set the COD (CODEC control) configuration register to value 0xNN. The Default value of this register after Power-Up or Reset is 0x01. Refer to subsection 7.4.3 Configuration Registers, which describes all register bits. SCOD Byte Sequence: Description: Class WTS701 1 Type I 0x4F 0xNN Status Byte 1 Host controller Status Byte 0 Set the COD (CODEC control) configuration register to value 0xNN. SAUD SET AUD REGISTER Set the AUD (analog audio) configuration register to value 0xNN. The Default value of this register after Power-Up or Reset is 0x43. Refer to subsection 7.4.3 Configuration Registers, which describes all register bits. SAUD Byte Sequence: Description: Class WTS701 1 Type I 0x50 0xNN Status Byte 1 Host controller Status Byte 0 Set the AUD (analog audio) configuration register to value 0xNN. SVOL SET VOL REGISTER Set the VOL (volume) configuration register to value 0xNN. The Default value of this register after Power-Up or Reset is 0x07. Refer to subsection 7.4.3 Configuration Registers, which describes all register bits. SVOL Byte Sequence: Description: Class WTS701 1 Type I 0x51 0xNN Status Byte 1 Host controller Status Byte 0 Set the VOL (volume) configuration register to value 0xNN. - 32 - WTS701 SSPD SET SPD REGISTER Set the SPD (speech rate/speed) configuration register to value 0xNN. The Default value of this register after Power-Up or Reset is 0x02. Refer to subsection 7.4.3 Configuration Registers, which describe all register bits. SSPD Byte Sequence: Description: Class WTS701 1 Type I 0x52 0xNN Status Byte 1 Host controller Status Byte 0 Set the SPD (speech rate/speed) configuration register to value 0xNN. SCLC SET CLC REGISTER Set the Clock configuration register (CLC) to value 0xNN. The value of this register must be set before Power-Up or Reset command to 0x00. Refer to subsection 7.4.3 - Configuration Registers, which describes all register bits. SCLC Byte Sequence: Description: Class 0 Type I 0x14 0xNN Host controller WTS701 Status Byte 0 Status Byte 1 Set the Clock configuration register (CLC) to value 0xNN. SPTC SET SPEECH PITCH Set the speech pitch to value 0xNN. The valid pitch values are between 0x00 and 0x06 while the default pitch value is 0x05, and these values can be used to control the speech output pitch. The command can be executed only when the WTS701 is in IDLE state. SPTC Byte Sequence: Description: Class WTS701 1 Type I 0x77 0xNN Status Byte 1 Host controller Status Byte 0 Set the speech pitch parameter to value 0xNN. - 33 - Publication Release Date: May 2003 Revision 3.09 WTS701 VLUP VOLUME-UP COMMAND Increment the volume (VOL) register. Has no effect if already at maximum volume. The Default value of this register after Power-Up or Reset is 0x07. Refer to subsection 7.4.3 Configuration Registers, which describes all register bits. VLUP Byte Sequence: Description: Class WTS701 1 Type I 0x53 0x00 Status Byte 1 Host controller Status Byte 0 Increment the volume (VOL) register. VLDN VOLUME DOWN COMMAND Decrement the volume (VOL) register. This has no effect if already at minimum volume. The Default value of this register after Power-Up or Reset is 0x07. Refer to subsection 7.4.3 - Configuration Registers, which describes all register bits. VLDN Byte Sequence: Description: Class WTS701 1 Type I 0x54 0x00 Status Byte 1 Host controller Status Byte 0 Decrement the volume (VOL) register. SPUP SPEED UP COMMAND Increase speaking rate (SPD register). This has no effect if already at maximum speaking rate. The Default value of this register after Power-Up or Reset is 0x02. Refer to subsection 7.4.3 Configuration Registers, which describes all register bits. SPUP Byte Sequence: Description: Class WTS701 1 Type I 0x55 0x00 Status Byte 1 Host controller Status Byte 0 Increase speaking rate (SPD register). - 34 - WTS701 SPDN SPEED DOWN COMMAND Decrease speaking rate (SPD register). Has no effect if already at minimum speaking rate. The Default value of this register after Power-Up or Reset is 0x02. Refer to subsection 7.4.3 Configuration Registers, which describes all register bits. SPDN Byte Sequence: Description: Class WTS701 1 Type I 0x56 0x00 Status Byte 1 Host controller Status Byte 0 Decrease speaking rate (SPD register). RST RESET COMMAND Sending this command has the same affect as a Power-On reset, the WTS701 enters the POWER DOWN state. RST Byte Sequence: Description: Class WTS701 0 Type I 0x10 0x00 Status Byte 1 Host controller Reset the WTS701 device. Status Byte 0 ABBR_ADD ADD ABBREVIATION Add an entry to the abbreviation table. ABBR_ADD Byte Sequence: Description: Class WTS701 2 Type 0xAF Status Byte 0 III 0x00 Status Byte 1 DATA0 Status Byte 0 ... DATAn ... Status Byte n%2 Host controller Add an entry to the abbreviation table.. - 35 - Publication Release Date: May 2003 Revision 3.09 WTS701 ABBR_MEM RETURN ABBREVIATION MEMORY The ABBR_MEM command will return the number of bytes available in the abbreviation table in MEM_HI and MEM_LOW. ABBR_MEM Byte Sequence: Description: Class WTS701 3 Type 0xC7 Status Byte 0 IV 0x00 Status Byte 1 0x00 MEM_HI 0x00 MEM_LOW Host controller Return the number of bytes available in the abbreviation table. ABBR_NUM RETURN NUMBER OF ABBREVIATION ENTRIES The ABBR_NUM command will return the number of abbreviation entries in the abbreviation table in NUM_HI and NUM_LOW. ABBR_NUM Byte Sequence: Description: Class WTS701 3 Type 0xC8 Status Byte 0 IV 0x00 Status Byte 1 0x00 NUM_HI 0x00 NUM_LOW Host controller Return the number of abbreviation entries in the abbreviation table. ABBR_RD READ ABBREVIATION TABLE The ABBR_RD command will return the abbreviation table. This command must read 2048 bytes after receiving the Status register. ABBR_RD Byte Sequence: Description: Class WTS701 3 Type 0xC9 IV 0x00 Status Byte 1 0x00 ABBR0 ..... ..... 0x00 ABRRn Host controller Status Byte 0 Return the 2048 bytes of abbreviations. - 36 - WTS701 ABBR_DEL DELETE ABBREVIATION ENTRY This command deletes abbreviation entry from abbreviation table. ABBR_DEL Byte Sequence: Description: Class WTS701 2 Type 0x83 I 0x00 Status Byte 1 DATA0 Status Byte 0 ... ... DATAn Status Byte n%2 Host controller Status Byte 0 Delete an entry from the abbreviation table. ENTER_RRSM SWAP MEMORY This command is used in programming mode, and causes the xdata and code store memory to swap spaces. Please refer to subsection 7.8 for more information about customizing abbreviations. ENTER_RRSM Byte Sequence: Description: Class WTS701 0 Type I 0x0C 0x00 Status Byte 1 Host controller Status Byte 0 Swap memory between xdata and code store. 7.4.2 Illegal Commands All commands described in section 7.4.1 are the only legal commands that should be sent to the WTS701 device, unless stated otherwise. Other commands should not be sent to the device, as the device behavior cannot be predicted. Specific illegal commands are those in which the 2 Most Significant Bits of the Command Byte are zeros and are not defined in this document as commands allowed to be sent to the WTS701. 7.4.3 Configuration Registers The configuration registers are accessed by sending the appropriate configuration command followed by a single byte of data to load the register. The definition of the contents of the various registers is given below. The default value for each of these registers after Power Up or Reset is also described in Table 10. - 37 - Publication Release Date: May 2003 Revision 3.09 WTS701 Table 10. Configuration Registers. MSB LSB Register COM COD AUD VOL CLC SPD Reg. # 0x4E 0x4F 0x50 0x51 0x14 0x52 Default 0x00 0x01 0x43 0x07 None 0x02 Bit 7 ICNT X AOPU X X X Bit 6 IBUF X SPPU X X X Bit 5 ICNV X SPG X X X Bit 4 X X FDTH X CLC4 X Bit 3 X X X X CLC3 X Bit 2 X MD2 X VL2 CLC2 SPD2 Bit 1 BUF1 MD1 AIG1 VL1 CLC1 SPD1 Bit 0 BUF0 MD0 AIG0 VL0 CLC0 SPD0 X = Reserved. The bits of each register are described below: COM Register ICNT IBUF ICNV BUF1..0 If set to a `1', the device will generate an interrupt when the Count register has been updated. This occurs after each word has been spoken. If set to `1', the device will generate an interrupt when the buffer level crosses the threshold set by the BUF bits. (see Table 3, Status bytes). If set to `1', the device will generate an interrupt when the end of a conversion is reached. If IBUF is set, BUF1..0 determines the buffer level at which the interrupt will be generated. 00b - Input buffer empty. 01b - Input buffer <10% full. 10b - Input buffer <50% full. 11b - Input buffer <75% full. - 38 - WTS701 COD Register MD2 CODEC enable, possible modes are: 0b: CODEC disabled. 1b: CODEC enabled during conversion. MD1 CODEC precision, possible modes are: 0b: 13 bit linear PCM output 1b: 16 bit linear PCM output. MD0 CODEC output format, possible modes are: 0b: unsigned PCM output 1b: 2's complement PCM output. AUD Register AOPU 1b: Power up the analog output buffer. SPPU 1b: Power up the analog speaker driver. SPG Speaker Driver gain selection. 0b: 8 Speaker. Av = 1.32 1b: 100 Speaker. Av = 1.6 FDTH 1b: Enable feed-through path from AUXIN to AUXOUT. AIG1..0 AUXIN gain setting 00b - 0dB 01b - 3dB 10b - 6dB 11b - 9dB - 39 - Publication Release Date: May 2003 Revision 3.09 WTS701 VOL Register VL2..0 Volume level of output. 000 - 0dB 001 - -4dB 010 - -8dB 011 - -12dB 100 - -16dB 101 - -20dB 110 - -24dB 111 - -28dB Each step gives a 4dB attenuation of output. CLC Register CLC4..0 Configure the device for different master clock frequencies. 0x00 0x10 0x08 24.576 MHz 16.384 MHz 32.768 MHz (The only clock frequency currently recommended for operation is 24.576MHz.) SPD Register SPD2..0 Configure the speech speed register. 0x04 is the fastest speed and 0x00 is the slowest. - 40 - WTS701 7.4.4 System Operation The WTS701 is a single chip solution for text-to-speech synthesis. The Text-to-Speech operation is accomplished by a process of screening the incoming text to normalize common abbreviations and numbers into a spoken form. The normalized text is then analyzed for phonetic interpretation and this phonetic translation is mapped into samples to be played out of the analog storage array. This output signal is then smoothed by a low-pass filter and is available as an analog signal, or can be passed through the CODEC for digital audio output. The WTS701 processor state machine The WTS701 functions as a state machine and changes states either in response to a command sent by the host controller, after execution of command is completed, or as a result of an internal event. The WTS701 states are described below in reference to Figure 10. Vcc Applied Reset Power Down Soft Reset, PWDN Soft Reset PWDN, Soft Reset Wait Hard Reset PWDN PWUP Idle Idle Convert Stop finish finish word conversion finished Convert Convert Hard Reset Figure 10. WTS701 Processor States - 41 - Publication Release Date: May 2003 Revision 3.09 WTS701 RESET The WTS701 processor is initialized to the RESET state when Vcc is first applied to the part. After a reset condition the device enters the POWER DOWN state. All configuration registers are initialized to their default values after issuing the PWUP command. Once the WTS701 is active and a hardware reset is applied on the RESET pin, the WTS701 will be in IDLE state, and all configuration registers will return to their default values. POWER DOWN In this state, the power consumption of the WTS701 is minimal. All analog outputs are tristate, the crystal interface is deactivated and the microcontroller is stopped. The only commands valid in the Power Down mode are PWUP, SCLC and RDST. All configuration registers will return to their default values after issuing the PWUP command. IDLE The idle state is first entered with the PWUP command. In this state, the micro-controller is running and the device is ready to respond to further commands. From the IDLE state, the device can go to the active CONVERT state or the POWER DOWN state. CONVERT This state is initiated by the CONV command. The text located in the internal buffer is converted into speech and played back to the analog or digital interface according to the state of the configuration registers. Once the active conversion has finished, the device enters the WAIT state. WAIT Once a conversion has finished, the device enters the WAIT state. In this state, audio outputs are still active. To deactivate, audio outputs and return to the IDLE state an IDLE command is issued. - 42 - WTS701 7.4.5 Initialization and Configuration Configuration After power-on or a Reset command (RST) the WTS701 processor can be configured for operation. This involves initializing the internal configuration registers for the users requirements. Table 11. Initialization Commnad Sequence State Command Description POWER DOWN -------SCLC PWUP State after power-on or RST command. Set clock configuration. Power up device. Set up communication register to enable interrupts. Set up CODEC configuration (if used). Set up audio control register. Set the initial volume level. Set the initial speech output speed level. Set the initial speech pitch level. IDLE SCOM SCOD SAUD SVOL SSPD SPTC 7.4.6 Converting Text After configuration, the WTS701 is ready for text-to-speech conversion. Because of the real-time nature of speech, some form of flow control is necessary to inform the host system: 1. When the device is ready for more text data 2. When the device has finished converting text 3. When the device can release the audio interface The CONVERT state is entered by sending a CONV command along with some textual data. The WTS701 has an internal 256-byte buffer to accept text data. The R/ B signal (both the hardware line and the status bit) will become active (LOW): 1. When the internal buffer is full 2. If the host sends data at a rate too fast for the WTS701 to process it to the internal buffer When R/ B becomes active the user may: 1. Wait for the R/ B pin to return to the (HIGH) ready state 2. Terminate the SPI transaction until a later time and resend the data - 43 - Publication Release Date: May 2003 Revision 3.09 WTS701 The user has the choice of enabling interrupts to signal the host when there is free space in the internal buffer. When all text data has been sent, the user must indicate this by: 1. Sending a FIN (Finish) command 2. Sending an EOT (ASCII 0x1A) character as the last byte of a CONV command (MANDARIN UNICODE/Big5 0x00 0x1A) When conversion has been terminated using either of these commands, another CONV command cannot be sent until conversion is completed and the chip enters the WAIT state. Notes 1. Buffer length limit: The max. character length of a white-space-bounded string is 53. The exceeding characters will be truncated. 2. Undefined characters: All the undefined characters will be deleted (prior to the word pronounciation process). The defined characters range from `0x00' to 0x7A' excluding `0x22', `0x3C', `0x3E' and `0x60'. Once the WTS701 has synthesized the contents of the text buffer, it will enter the WAIT state. In this state the audio interface is still active. To disable the audio interface and return to the IDLE state an IDLE command is sent. The WAIT state can be detected either through polling of the CNVT bit or enabling of the ICNV interrupt. An example of the flow for a conversion is shown in Figure 11. The flow here assumes that the COM register is set such that the WTS701 generates an IBUF interrupt at the 75 percent buffer level (64 free bytes) and that the ICNV interrupt is enabled. - 44 - WTS701 IDLE Send CONV command Fill serial buffer with text data No Sent all data? Yes Send FIN command Wait for ICNV interrupt or CNVT cleared Send IDLE command Wait for IBUF interrupt Write a new batch of text data to buffer ( < 192 bytes otherwise buffer may overflow) Figure 11. Flow Diagram for Convert Operation. - 45 - Publication Release Date: May 2003 Revision 3.09 WTS701 Controlling Text Conversion The WTS701 offers several features to control text conversion. The PAUS (Pause) and RES (Resume) commands allow the host to pause and then continue speech output. The FINW command allows the host to end a conversion after the next whole word is spoken. The ST (Stop) command will terminate a conversion immediately - even mid-word. To allow more advanced control, the WTS701 allows the host to interrogate the byte count register, which keeps track of the position in the input stream that is currently being spoken. If the host wishes to repeat a spoken word, it should: 1. Read the byte count register 2. Send a FINW or ST command 3. Wait for ICNV 4. Send a new CONV command resending the data starting at the desired number of bytes, according to the repeated spoken words, prior to the count returned in the byte count In a similar way a skip function could be implemented to skip ahead words or sentences. 7.5 SPI INTERFACE The SPI interface consists of the 4-wire bus SS , SCLK, MOSI and MISO. In addition, flow control protocols are implemented via the R/ B signal and/or the WTS701 Status register transmitted via MOSI. The WTS701 processor also has the option to communicate with the host via interrupt services requested by the interrupt request line. The timing and behavior of these signals is dependent upon the command class being executed, i.e., commands with or without associated data. Additionally the use of the R/ B hardware control line is not compulsory; rather the host can monitor the R/ B bit of the status register to determine when data has been accepted. The status register also contains the ICMD bit. This bit is set to indicate an SPI transaction has been ignored, indicating that the WTS701 processor is unable to service a new command. Asynchronous (Class 0) commands are always accepted. For more information, refer to subsection 7.3.1 which describes the command classes. 7.5.1 SPI Transactions SPI Transactions with the WTS701 are broken down into four classes and four basic types: Type I - Single Word Transactions Single word transactions are Class 0 or Class 1 commands that have no data to transmit or transmit all required data in the command data byte. R/ B will never become active for these commands. ICMD could be active for a Class 1 command if the WTS701 is still interpreting the previous command. - 46 - WTS701 Command Byte Command Data Byte SSB SCLK MOSI MISO 7654321076543210 00 0 0 0 0 0 ICNT IBUFI ICNV COD BFUL BEMP CNVT RDY R/B IABB Figure 12. Type I SPI Transaction. Type II - Two Word Transactions that Receive Data Type II transactions are four byte transactions that read out the byte count register. As these commands are all Class0, ICMD will never be active and R/ B will never occur. Command Data Byte Data Byte 0 (even) Data Byte 1 (odd) SSB SCLK MOSI MISO Command Byte 7654321076543210 00 0 0 0 0 0 7 6 54 3 2 1 0 f e d c b a 9 8 BCNT0 BCNT1 ICNT IBUFI ICNV COD BFUL BEMP CNVT RDY R/B IABB Figure 13. Type II SPI Transaction. Type III - Transactions that send data Type III transactions send data to the WTS701. If the data rate exceeds the ability of the WTS701 to read data from the input FIFO or if the internal data queue becomes full then the R/ B line will handshake a pause in the SPI transaction. The host can either: * * Wait for R/ B to return HIGH then continue sending data Terminate the transaction and try sending data later ICMD - 47 - Publication Release Date: May 2003 Revision 3.09 ICMD WTS701 Command Byte Command Data Byte SSB SCLK MOSI MISO 7654321076543210 00 0 0 0 0 ICNT IBUFI ICNV COD BFUL BEMP CNVT RDY R/B IABB ICMD Data n (even) SSB SCLK MOSI R/B Data n+1 (odd) Data n+2 (even) Data n+3 (odd) 7654321076543210 7654321076543210 R/B low with SPI End MISO ICNT IBUFI ICNV COD BFUL BEMP CNVT RDY R/B 000 00 00 ICNT IBUFI ICNV COD BFUL BEMP CNVT RDY R/B IABB ICMD 000000 IABB ICMD Figure 14. Type III SPI Transaction. Type IV - Transactions reading data Type IV transactions read data from the WTS701. Because of the latency required for the WTS701 to place data in the output register, R/ B must be monitored. Command Data Byte Data Byte 0 (even) Data Byte 1 (odd) SSB SCLK MOSI MISO R/B Command Byte 7654321076543210 00 0 0 0 0 0 7654321076543210 ICNT IBUFI ICNV COD BFUL BEMP CNVT RDY R/B IABB Figure 15. Type IV SPI Transaction. - 48 - ICMD WTS701 7.6 CODEC INTERFACE The WTS701 processor supports analog and digital telephony in various configurations. The WTS701 can be used in digital environments, along with a DSP that controls a CODEC. Therefore, the WTS701 is configured to operate in slave mode, where the control signals are provided by an external source, which is usually the DSP. It supports a variety of single channel CODECs, examples of which are listed in Table 12. The CODEC interface is designed to send data in short frame format as well as long frame format. The channel width is 13 or 16 bits linear, the precision of the output is 10 bits. The operation mode of the CODEC is configured by the COD configuration register and SCOD command. See subsection 7.4.3 for details. * * * The CODEC can be configured to transmit data in the unsigned or 2's Complement mode (see Table 13 for details). The CODEC responds to both the Long and Short sync format (see Figure 16 and Figure 17). The CODEC can be configured to tristate the VDX line after 13 or 16 bits. Table 12. Supported CODEC Examples. Manufacturer CODEC Device Name Characteristics Operating Voltage Conversion Type Data Format OKI OKI OKI Motorola Lucent ML7041 MSM7716 MSM7732-011 MC145483 T8538B Single codec Single codec Single codec Single codec Quad codec 3V 3V 3V 3V 3.3 V 14-bit linear 14-bit linear 14-bit linear 13-bit linear 16-bit linear 2s Complement 2s Complement 2s Complement 2's Complement 2's Complement - 49 - Publication Release Date: May 2003 Revision 3.09 WTS701 Table 13. CODEC Transmission Modes. Level Signed Mode (2's Complement) Sign Bit (MSB) 13 Bit Mode 16 Bit Mode Unsigned Mode 13 Bit Mode 16 Bit Mode +ve full scale +1 LSB Zero (ground) -1 LSB -ve full scale 0 0 0 1 1 1111 1111 1000 0000 0000 1000 0000 0000 0000 1111 1111 1000 0000 0000 0000 1111 1111 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 1111 1111 1000 0000 0000 0000 0000 0000 1 1111 1111 1000 1 0000 0000 1000 1 0000 0000 0000 0 1111 1111 1000 0 0000 0000 0000 1111 1111 1100 0000 1000 0000 0100 0000 1000 0000 0000 0000 0111 1111 1100 0000 0000 0000 0000 0000 VFS VC LK VD X 13 12 11 10 9 8 7 6 5 4 0 LSB 00 MSB Figure 16. CODEC Protocol, 13 bit, Short Frame Sync. - 50 - WTS701 VFS VC LK VD X 13 12 11 10 9 8 7 6 5 4 0 LSB 00 MSB Figure 17. CODEC Protocol, 13 bit, Long Frame Sync. VFS VC LK VD X MSB 13 12 11 10 9 8 7 6 5 4 0 0 0 0 00 LSB 3 ZEROS Figure 18. CODEC Protocol, 16 bit, Short Frame Sync. - 51 - Publication Release Date: May 2003 Revision 3.09 WTS701 VFS VC LK VD X MSB 13 12 11 10 9 8 7 6 5 4 0 0 0 0 00 LSB 3 ZEROS Figure 19. CODEC Protocol, 16 bit, Long Frame Sync. 7.7 CONTROL CHARACTERS The WTS701 allows receiving control characters embedded in the text sent in the Convert command to better emphasize word or alter meaning of sentence. The control characters supported are for phonetic alphabet playback, speed, volume modification and case sensitivity behavior. 7.7.1 Phonetic Alphabet Playback The WTS701 uses an intermediate phonetic translation represented as an alphabet that represents phonemes and stress for each input word. This feature allows the text sent to the WTS701 to consist of a combination of ASCII characters as well as phonetic alphabet. This capability offers the flexibility to send words already processed for phonetic representation, achieving the desired pronunciation. Phonetic strings can be sent directly to the WTS701. This can be done by embedding phoneme strings in the text stream for conversion. To embed a phoneme string, the string must be preceded by a control-P (^P, ASCII 0x10) character and terminated by a space character. For example: "The quick ^Pbr1Wn fox." The following table lists the phoneme symbols acceptable by the WTS701E (English software version). As the acceptable phoneme symbols are language dependent, please refer to the specific language User's Guide for details regarding characters accepted and other development considerations. - 52 - WTS701 Table 14. Acceptable Phoneme Symbols. Vowels Phoneme i Hex Value Example Consonants Phoneme Hex Value Example 0x69 0x49 0x65 0x45 0x40 0x75 0x55 0x6f 0x63 0x61 0x41 0x52 0x4f 0x59 0x57 0x78 0x58 beat bit bait bet bat boot book boat bought Bob but burr boy buy down about p t k b d g h f T D s S v z Z y w r l m n G C J P Q 0x70 0x74 0x6b 0x62 0x64 0x67 0x68 0x66 0x54 0x44 0x73 0x53 0x76 0x7a 0x5a 0x79 0x77 0x72 0x6c 0x6d 0x6e 0x47 0x43 0x4a 0x50 0x51 pet ten kit bet debt get hat fat thing that sat shut vat zoo I e E @ u U o c a A R O Y W x X azure you wit rent let met net roses sing church Judge Butter* Written* Note that each phoneme is represented by exactly one character and each vowel is preceded by a stress symbol. * Female English only. - 53 - Publication Release Date: May 2003 Revision 3.09 WTS701 Numbers 1 and 0 represent stress: each word has a single 1 stress, representing the main stress of the word; all other syllables have 0 stress. Examples: Input hi. test testing Phonetic translation h1Y (phoneme /h/, followed by a 1-stress vowel phoneme Y) t1Est t1Est0IG Special Characters in Text Input String These characters inserted into the ASCII text are used to modify the behavior for special circumstances. 0x10 ^P This `^Ppr0Ez0Intles0In'). control flag indicates a phoneme string follows immediately (e.g. 0x11 ^Q Pauses with variant length can be added within a sentence by using the `^QX' flag. `X' is an integer which indicates the pause duration (`X' is 0.1 sec per unit). For instance, `^Q10' will add in a 1-second pause. It is important to remember that all the text following these special characters will be subjected to the same special conditions. If a ^V+ command precedes a word then all the following words will be spoken louder. If a single word is to be emphasized then the ^V+ must be ahead of the word and a ^V- must follow. 7.7.2 Speed Change The rate of speech can be changed by sending an SPI command to modify the speed or by adding a control character to control the speed in real-time. 0x13 ^S Speed Change Flag. A space character is required after the control characters before the input text string. * * * ^S+: ^S-: Increase speed by 1 (e.g. `^S+ Hello world'). Decrease speed by 1. ^SX: Set the speed to X. X starts from 0 to 4 (e.g. `^S1 Hello world'). Any number that is greater than 4 will be set to 4. It's the user's responsibility to verify the WTS701 speed setting before sending a control character and/or SPI command that modify speed. - 54 - WTS701 7.7.3 Volume Change The speech volume can be changed by sending SPI command to modify the speed or by adding control character to control the volume in real-time. 0x16 ^V Volume Change Flag. A space character is required after the control characters before the input text string. * * * ^V+: ^V-: Increase volume by 1 (e.g. `^V+ Hello world'). Decrease volume by 1. ^VX: Set the volume to X. X starts from 0 to 7 (e.g. `^V1 Hello world'). Any number that is greater than 7 will be set to 0. It's the user's responsibility to verify the WTS701 volume setting before sending a control character and/or SPI command that modify volume. 7.7.4 Case Sensitivity The way upper/lower case is handled can be changed by adding a control character in the text sent to control the case sensitivity behavior in real-time. 0x15 ^U All-Uppercase Word (all CAPs) Control Flag. This flag controls interpretation of strings with all uppercase letters. A space character is required after the control characters before the acutual input text string. * ^U0: This is the default setting. Some all-uppercase words (all CAPs) are spelled out, but others are treated as ordinary words, abbreviations, Roman numerals, ect. (e.g. `^U0 IBM equals `i b m'). ^U1: Avoid spelling out all-uppercase words. Any all-uppercase word in the input string will NOT be spelled out unless the system determines that the word is not pronounceable. In this mode, there is no abbreviation support (e.g. `^U1 NOKIA' equals `nokia'). ^U2: Spell out all words, regardless of case. All words in the input sting are spelled out in this mode. There is no abbreviation support in this mode (e.g. `^U2 NOKIA' equals `n o k i a'). ^U3: Force the all-capital words/strings to be spelled out regardless of string length. For instance, `^U3 HELLO' will be pronounced as `H', `E', `L', `L', `O'. * * 7.7.5. Pause Control Pause control flage: `^QX': Pauses with variant length can be added within a sentence by using the `^QX' flag. `X' is an integer which indicats the pause duration (`X' is 0.1 sec per unit). For instance, `^Q10' will add in a 1-second pause. - 55 - Publication Release Date: May 2003 Revision 3.09 WTS701 7.8 CUSTOMIZING ABBREVIATIONS The WTS701 has support for entering and using custom abbreviations in addition to the general abbreviation table supported internally by the WTS701. There are 2K bytes of flash memory reserved for this purpose. After the WTS701 internal software has been initially programmed, this entire area is free and available for custom abbreviations. The commands associated with custom abbreviations are: Command ABBR_ADD Command Byte 0xaf Command Data Byte 0x00 + abbreviation data. 0x00+ abbreviation data. 0x00 + 0x00 + 0x00. 0x00 + 0x00 + 0x00. 0x00 + 2048 0x00s. Adds a new abbreviation to the abbreviation table in the WTS701 See next page for the format of the abbreviation data. Deletes an existing abbreviation from the abbreviation table in the WTS701. See next page for the format of the abbreviation data. Returns the number of abbreviation currently active in the abbreviation table of the WTS701. Returns the number of free bytes in the abbreviation table of the WTS701. Returns the abbreviation table contents from the WTS701. See next page for the format of the abbreviation table data. Causes the xdata and code store memory to swap spaces. The WTS701 begins to execute code previously stored into xdata after this command. ABBR_DEL 0x83 ABBR_NUM 0xc8 ABBR_MEM 0xc7 ABBR_RD 0xc9 ENTER_RRSM 0x0c 0x00 7.8.1 Abbreviation Data Format The format of the abbreviation data that is sent with the ABBR_ADD and ABBR_DEL commands is: XXX + "," + YYYY + ";". XXX - the abbreviation characters. "," - comma. YYYY - abbreviation text. - 56 - WTS701 ";" - semi-colon. Example: TTS,text to speech; After this is added using the ABBR_ADD command, when the text "TTS" is sent as part of the convert data, the WTS701 will speak "text to speech" instead of T T S. Note: when deleting an abbreviation, the abbreviation text is optional. To delete the TTS example, only "TTS,;" is necessary. 7.8.2 Abbreviation Table Format The format of the abbreviation table returned with the ABBR_RD command is: Abbreviation entry - Marker + Count + XXX + 0x00 + YYYY + 0x00. Marker - The marker will be either 0xfe for active abbreviation or 0xfc for a deleted abbreviation. Count - The byte count for this entry including the Marker, Count, XXX, YYYY, and zeros. XXX - the abbreviation characters. 0x00 - Null terminator. YYYY - abbreviation text. 0x00 - Null terminator. The unused data are always 0xff. 7.8.3 Command Execution ABBR_NUM & ABBR_MEM - These commands are executed by sending the command and command data, waiting for R/ B to be ready, then receiving two bytes from MISO. The first byte received is the MSB, and the second is LSB. ABBR_RD - This command is executed by sending the command and command data, waiting for R/ B to be ready, then receiving 2048 characters (the entire abbreviation table). ABBR_ADD & ABBR_DEL - These commands are executed by sending the command and command data, followed by the abbreviation data formatted as described in subsection 7.8.1. When the WTS701 is ready for the next step, it will generate an IABB interrupt. After the interrupt, send the ENTER_RSSM (0x0c + 0x00) command. After issuing the command wait for 100ms. After the timeout, the WTS701 will have programmed the new abbreviation entry and be ready to accept more commands. Adding or removing an abbreviation will reset the configuration registers to their default values. - 57 - Publication Release Date: May 2003 Revision 3.09 WTS701 After abbreviation entry deletion, the abbreviation entry is only deleted from the table and not used, however it still holds memory space. The only way to free all memory will be to reprogram the WTS701 firmware into the device. 7.9 DEVICE PROGRAMMING The WTS701 is fully programmable to support different available languages or different voices that can be loaded to the device whenever the user wishes to do so. The language or the voice module should be stored externally and transmitted to the WTS701 processor with regards to a specific protocol defined in this section. Programming the WTS701 consists of downloading a binary executable to the processor code memory and a digitized analog speech corpus to the non-volatile analog multi-level storage (MLS). Winbond will supply code as a set of ASCII readable data files. The information will be provided to qualified customers upon request. - 58 - WTS701 7.10 TEXT-TO-SPEECH PROCESSOR COMMMANDS - QUICK REFERENCE TABLE. Status Commands Command Description Opcode Hex Command byte Command data Previous State Result State Command Parameters Description Return Value Description Byte count Byte count Hw_ver, Sw_ver Name RDST RINT RVER 0 0 0 II II II Read Status Read Interrupt Read version 04 06 12 00 00 00 Idle, Convert, Power Down Idle, Convert Idle, Convert No change No change No change None None None - - 59 - Publication Release Date: May 2003 Revision 3.09 Bytes Class Type WTS701 System Commands Command Description Opcode Hex Previous State Result State Command Parameters Return Value Description Description Command byte Command data Name Class Bytes PWUP PWDN 0 1 0 I I I Exit Power Down mode Go To Power Down mode Reset 02 40 10 00 00 00 Power Down Idle, Convert Wait Idle, Convert Wait, Power down Idle Power Down Power Down None None None - None None None RST - 60 - Bytes Type - WTS701 Synthesis Commands Command Description Opcode Hex Previous State Result State Command Parameters Description Return Value Description Command byte Command data Name Class Bytes CONV PAUS RES ST FINW FIN VLUP VLDN SPUP SPDN IDLE 2 1 1 1 1 1 1 1 1 1 1 III I I I I I I I I I I Convert text Pause conversion Resume conversion Stop conversion Finish word Finish Volume up Volume down Speed up Speed down Switch to Idle state 81 49 4A 4B 4D 4C 53 54 55 56 57 00 00 00 00 00 00 00 00 00 00 00 Idle, Wait Convert Convert Convert Convert Convert Idle, Convert Wait Idle, Convert Wait Idle, Convert Wait Idle, Convert Wait Wait, Convert Convert No change No change Wait Wait Wait No change No change No change No change Text data None None None None None None None None None None N - None None None None None None None None None None None Idle - 61 - Publication Release Date: May 2003 Revision 3.09 Bytes Type - WTS701 Configuration Commands Command Description Opcode Hex Previous State Result State Command Parameters Description Return Value Description Command byte Command data Name Class RREG 3 IV Read configuration register Set COM register Set COD register Set AUD register Set VOL register Set SPD register Set CLC register Set Speech Pitch C0 Register Number Idle, Convert No change None Bytes Type - Registe r value, dummy byte None None None None None None None SCOM SCOD SAUD SVOL SSPD SCLC SPTC 1 1 1 1 1 1 1 I I I I I I I 4E 4F 50 51 52 14 77 Value Value Value Value Value Value Value Idle, Wait Idle, Wait Idle, Wait Idle, Wait Idle, Wait Idle, Wait Idle, Wait No Change No Change No Change No Change No Change No Change No Change None None None None None None None - - 62 - WTS701 Customization Commands Command Description Opcode Hex Previous state Result State Command Parameters Description Return Value Description Num_of_entries Abbreviation table entries Available_mem Command byte Command data Name Class ABBR_ NUM 3 IV Return number of abbreviation entries Read abbreviation table Return abbreviation memory Add abbreviation Delete abbreviation entry Swap memory C8 00 Idle No change None - ABBR_ RD ABBR_ MEM ABBR_ ADD ABBR_ DEL ENTER _RRS M 3 IV C9 00 Idle No change None - 3 IV C7 00 Idle No change None - 2 1 III I AF 83 00 00 Idle Idle No change No change Abbreviation information Abbreviation information N N Bytes Type None None 0 I 0C 00 Idle No change None - None - 63 - Publication Release Date: May 2003 Revision 3.09 WTS701 7.10.1 Text Input Format The following table lists the ASCII characters acceptable by the WTS701E (English software version). Please refer to the specific language User's Guide for more details regarding characters accepted and other development considerations. Note: Unexpected behavior may occur if the input text contains characters that are not defined in this ASCII table. Table 15. Allowable ASCII Characters. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f EOT ^U ^V ^S ^P ^Q 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f ? = # $ % & ` (apostrophe) ( ) * + , (comma) - (dash) . (period) Space ! 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z ] (right bracket) \ (back slash) [ (left bracket) _ (under score) 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f a b c d e f g h i j k l m n o p q r s t u v w x y z / (slash) 0 1 2 3 4 5 6 7 8 9 : (colon) - 64 - WTS701 7.10.2. Buffer length limit The max. character length of a white-space-bounded string is 53. The exceeding characters will be truncated. 7.10.3. Undefined characters All the undefined characters will be deleted (prior to the word pornunciation process). The difined characters range from `0x00' to `0x7A' excluding `0x22', `0x3E', and `0x60'. - 65 - Publication Release Date: May 2003 Revision 3.09 WTS701 8. TIMING WAVEFORMS 8.1 SPI TIMING DIAGRAM SS Tsss SCLK Tsclkhigh Tsclklow Tssh Tssmin Tdis MOSI Tdih TRISTATE Tpd Tdf TRISTATE MISO Figure 20. SPI Timing Specification. SS BIT 7 SCLK BIT 0 Trbd R/B Trblow Trbh Figure 21. SPI R/ B Timing. - 66 - WTS701 Table 16. SPI Timing Parameters (see Figure 20 and Figure21) Symbol TSSS TSSH TDIS TDIH TPD TDF TSSmin TSCKhi TSCKlow Trbd Parameters SS Setup Time SS Hold Time Min 100 100 50 50 Typ(7) Max Units ns ns ns ns Conditions Data in Setup Time Data in Hold Time Output Delay Output Delay to hiZ SS High 100 100 200 80 80 ns ns ns ns ns SCLK High Time SCLK Low Time Delay SCLK Hi to R/ B low 80 0 0 ns ms Trblow Trbh FO R/ B low time SCLK hold time from R/ B \ High CLK Frequency 5000 kHZ - 67 - Publication Release Date: May 2003 Revision 3.09 WTS701 8.2 CODEC TIMING DIAGRAMS tsync tfsp VFS tx VCLK tsx tdv VDX tdhi LSB MSB MSB-1 Figure 22. CODEC Timing -- Short Frame Sync. tsync tfsp VFS tx VCLK tsx tdv VDX tdhi LSB MSB MSB-1 Figure 23. CODEC Timing -- Long Frame Sync. - 68 - WTS701 Table 17. CODEC Timing Parameters (see Figure 22 and Figure 23) Symbol Tclk Tsync DC Tir Tif Tfsp Trs Tsr Tdv Tdhi Parameters Bit clock frequency Frame Sync. Frequency Clock Duty Cycle Rise Time Fall Time Frame Sync. Pulse Width Receive Sync. Timing Receive Sync. Timing Output Delay Time for VDX Valid Output Delay Time for VDX High Impedance Min 128 Typ(7) Max 2048 Units kHz kHz Conditions 8 45 50 55 50 50 100 20 80 10 10 140 140 % ns ns ns ns ns ns ns All digital inputs All digital inputs VFS VCLK to VFS VFS to VCLK VCLK to VDX VCLK to VDX - 69 - Publication Release Date: May 2003 Revision 3.09 WTS701 9. ABSOLUTE MAXIMUM RATINGS Table 18. Absolute Maximum Ratings (Packaged Parts) (1) Condition Junction temperature Storage temperature range Voltage Applied to any pin Voltage applied to any pin (Input current limited to +/-20 mA) Lead temperature (soldering VCC - VSS - 10 seconds) (2) Value 150 C -650C to +1500C (VSS - 0.3V) to (VCC + 0.3V) (VSS - 1.0V) to (VCC + 2.2V) 3000C -0.3V to +7.0V 0 Table 19. Operating Conditions (Packaged Parts). Condition Commercial operating temperature range (3) Extended operating temperature(2) Industrial operating temperature(2) Supply voltage (VCC)(4) Ground voltage (VSS) (5) Value 00C to +700C -200C to +700C -400C to +850C +2.7V to +3.3V 0V 1 Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. All input pins except for CS signal, which is 3V tolerant ONLY. Case Temperature. VCC = VCCA = VCCD. VSS = VSSA = VSSD - 70 - 2 3 4 5 WTS701 10. ELECTRICAL CHARACTERISTICS (VCC = 3.3V, VSS = 0V, TA = 0 to 70 C) Table 20. General Parameters. PARAMETER SYMBOL TEST CONDITIONS MIN (6) SPEC TYP (7) UNIT MAX. Input LOW Voltage Input HIGH Voltage Output LOW Voltage R/ B , INT Output LOW Voltage Output HIGH Voltage VCC Current (Operating) - Convert - Idle - CODEC - Speaker VCC Current (Standby) Input Leakage Current VIL VIH VOL VOL1 VOH ICC No Load(8) No Load No Load No Load ISB IIL (8) (8) (8) (8) VCC x 0.2 VCC x 0.8 IOL = 10 A IOL = 1 mA IOL = -10 A VCC - 0.4 50 20 20 15 1 50 +/-1 0.4 0.4 V V V V V mA mA mA mA A A 6 7 8 All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100% tested. Typical values are T = 25C and VCC = 3.0V, timing measured at 50% levels. VCCA and VCCD summed together. Publication Release Date: May 2003 Revision 3.09 - 71 - WTS701 Table 21. Speaker Driver Specifications. PARAMETER SP+/- Output Voltage (HIGH Gain Setting) SP+/- Output Load Imp. (LOW Gain) SP+/- Output Load Imp. (HIGH Gain) SP+/Cap. Output Load SYMBOL VSPHG RSPLG RSPHG CS P TEST CONDITIONS MIN. Peak-to-Peak, load = 150 differential 8 70 SPEC TYP. MAX. 3.6 UNIT V 150 100 1.2 pF VDC SP+/Output Bias Voltage (Analog Ground) Speaker Offset Output DC VSPAG VSPDCO PSRR With AUXIN to Speaker, AUXIN AC coupled to VSSA Measured with a 1 kHz, 100 ma sine wave input at VCC and VCC pins With 0TLP input to AUX IN, 6 dB setting (12) Differential load at 8 -0.25 23.5 -55 100 mVDC dB Power Supply Rejection Ratio Frequency Response (300-3400 Hz) Power Output Gain Setting) (LOW FR PUTLOG +0.25 dB mWRMS - 72 - WTS701 Table 22. AUXOUT Parameters. PARAMETER AUXOUT - Maximum Output Swing Minimum Load Impedance Maximum Load Capacitance AUXOUT SYMBOL VANAIUT RL CL VBIAS TEST CONDITIONS MIN. 5k Load (AC Coupled) 5 SPEC TYP. MAX. 1.0 UNIT V k 100 pF VDC 1.2 Table 23. Volume Control Parameters. PARAMETER Output Gain Absolute Gain SYMBOL AOUT TEST CONDITIONS MIN. 8 steps of 4 dB, referenced to output AUXIN 1.0 kHz 0TLP, 6 dB gain setting measured differentially at SP+/-0.5 SPEC TYP. -28 to 0 +0.5 UNIT MAX. dB dB - 73 - Publication Release Date: May 2003 Revision 3.09 WTS701 11. TYPICAL APPLICATION CIRCUIT The following schematic diagrams are extracted from the WTS-ES701 evaluation board schematic. The evaluation system includes the following basic clusters: WTS701 processor cluster working with 3.3V, including an 8-ohm speaker, SPI connector to the host PC via the PC parallel port. For more information about the evaluation system, please refer to the WTS-ES701 User's Guide. VCCD U6 1 2 3 4 5 6 7 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 13 12 11 10 9 8 2 .1UF PG 1,3 PAD_BCLK PG 1,3 PAD_FS PG 1,3 PAD_DIN J7 3 2 1 PG 1,3 PAD_MISO PAD_XTI PAD_XTO 3 4 5 6 8 7 9 PG 1 PAD_XTO C18 10PF C19 10PF PG 1,3 PAD_INTB VCCD C23 .1UF VCCD C24 .1UF VCCD PAD_RDY PAD_MISO PAD_INTB R9 33K R10 33K R11 33K C25 PG 1 CSB CSB PG 1,3 PAD_RDY PG 1,3 PAD_RESET 25 26 27 CSB RDY RESET WTS701 R12 33K R13 10K MJ-3536N PAD_AUXIN .1UF J5 3 2 1 VCCA C21 .1UF VCCA C22 .1UF PG 1,3 PAD_MOSI PG 1,3 PAD_SSB PG 1,3 PAD_SCLK VCCD Y2 XTAL 10 11 12 13 14 15 16 C26 U5 VSSA1 VCLK VFS VDX MISO XTI XTO VSSDN VSSD VCCD VCCDN INTB MOSI SSB SCLK VSSA2 36 ATTCAP 40 PAD_ATTCAP VCCA SPK+ VSSA3 SPK48 46 44 42 PAD_SPKPAD_SPK+ AUXIN 52 PAD_AUXIN VCCA AUXOUT 54 PAD_AUXOUT PAD_AUXOUT PG 1 C17 J1 3 2 1 AUXOUT .1UF R8 10K MJ-3536N CRYSTAL SOCKET PAD_AUXIN PG 1 PAD_SPK+ PG 1 J2 3 2 1 PG 1 PAD_XTI SPEAKER MJ-3536N PAD_SPK- PG 1 PAD_ATTCAP PG 1 + C20 4.7UF J4 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GNDA GND VCCD VCCA PAD_RDY PAD_RESET PAD_ATTCAP PAD_SPKPAD_SPK+ PAD_AUXOUT PAD_SCLK PAD_SSB PAD_MOSI PAD_INTB PAD_XTI PAD_XTO PAD_MISO PAD_DIN PAD_FS PAD_BCLK Label pins of J4 with signal names. AUXIN - 74 - WTS701 12. PACKAGE DRAWING AND DIMENSIONS 56 L TSOP(I) (14X20 MM) - 75 - Publication Release Date: May 2003 Revision 3.09 WTS701 13. ORDERING INFORMATION WTS701__ __ /__ Language E - English M - Mandarin Voice F - Female M - Male Package Type T - TSOP 56-leads For the latest product information, access Winbond's worldwide website at http://www.winbond-usa.com - 76 - WTS701 14. VERSION HISTORY VERSION DATE PAGE DESCRIPTION 3.07 3.08 3.09 Apr. 2002 Jun. 2002 May 2003 1-73 1-73 all Initial issue Improved package drawing, added illegal commands description, modified part number format Add crystal spec., description of buffer length limit & undefined characters, consonant phoneme characters (P & Q), ^U3 and ^Q control characters. The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental injury could occur. Headquarters No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A.. TEL: 1-408-9436666 FAX: 1-408-5441798 http://www.winbond-usa.com Winbond Electronics (Shanghai) Ltd. 27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998 Taipei Office 9F, No. 480, Pueiguang Rd Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-287153579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoky-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloom, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all dataand specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. This product incorporates SuperFlash(R) technology licensed from SST. - 77 - Publication Release Date: May 2003 Revision 3.09 |
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