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INTEGRATED CIRCUITS 74ABT16899 74ABTH16899 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Product specification Supersedes data of 1997 Mar 28 IC23 Data Handbook 1998 Feb 25 Philips Semiconductors Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 FEATURES * Symmetrical (A and B bus functions are identical) * Selectable generate parity or "feed-through" parity for A-to-B and B-to-A directions Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The 74ABT/H16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. * Independent transparent latches for A-to-B and B-to-A directions * Selectable ODD/EVEN parity * Continuously checks parity of both A bus and B bus latches as ERRA and ERRB FUNCTIONAL DESCRIPTION The 74ABT/H16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of: * Open-collector ERR output * Ability to simultaneously generate and check parity * Can simultaneously read/latch A and B bus data * Output capability: +64 mA/-32mA * Latch-up protection exceeds 500mA per Jedec Std 17 * ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model * Power up 3-State * Power-up reset * Live insertion/extraction permitted * Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs DESCRIPTION The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. * Transparent latch / 1 bus latched / both buses latched * Feed-through parity / generate parity * Check in bus parity / check out bus parity / check in and out bus parity QUICK REFERENCE DATA SYMBOL tPLH tPHL tPLH tPHL CIN CI/O ICCZ ICCL Propagation delay An to Bn or Bn to An Propagation delay An to ERRA Input capacitance Output capacitance Quiescent supply current PARAMETER CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V Output Low; VCC = 5.5V TYPICAL 2.7 5.0 4 7 500 10.5 UNIT ns ns pF pF A mA ORDERING INFORMATION PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT16899 DL 74ABT16899 DGG 74ABTH16899 DL 74ABTH16899 DGG NORTH AMERICA BT16899 DL BT16899 DGG BH16899 DL BH16899 DGG DWG NUMBER SOT371-1 SOT364-1 SOT371-1 SOT364-1 1998 Feb 25 2 853-1960 19018 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 PIN CONFIGURATION ODD/EVEN OEA 1A0 GND 1A1 1A2 1A3 1A4 VCC 1A5 1A6 1A7 1APAR 1ERRA GND 2ERRA 2APAR 2A7 2A6 2A5 VCC 2A4 2A3 2A2 2A1 GND 2A0 LEB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SEL LEA 1B0 GND 1B1 1B2 1B3 1B4 VCC 1B5 1B6 1B7 1BPAR 1ERRB GND 2ERRB 2BPAR 2B7 2B6 2B5 VCC 2B4 2B3 2B2 2B1 GND 2B0 OEB SH00082 PIN DESCRIPTION SYMBOL 1A0 - 1A7 2A0 - 2A7 1B0 - 1B7 2B0 - 2B7 1APAR 2APAR 1BPAR 2BPAR ODD/EVEN OEA, OEB SEL LEA, LEB 1ERRA, 1ERRB 2ERRA, 2ERRB GND VCC PIN NUMBER 3, 5, 6, 7, 8, 10, 11, 12 27, 25, 24, 23, 22, 20, 19, 18 54, 52, 51, 50, 49, 47, 46, 45 30, 32, 33, 34, 35, 37, 38, 39 13, 17 44, 40 1 2, 29 56 55, 28 14, 43, 16, 41 4, 15, 26, 31, 42, 53 9, 21, 36, 48 NAME AND FUNCTION Latched A bus 3-State inputs/outputs Latched B bus 3-State inputs/outputs A bus parity 3-State input B bus parity 3-State input Parity select input (Low for EVEN parity) Output enable inputs (gate A to B, B to A) Mode select input (Low for generate) Latch enable inputs (transparent High) Error signal outputs (active-Low) Ground (0V) Positive supply voltage 1998 Feb 25 3 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 LOGIC SYMBOL 3 5 6 7 8 10 11 12 13 27 25 24 23 22 20 19 18 17 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1APAR 55 28 56 1 2 29 LEA LEB SEL ODD/EVEN OEA OEB 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1BPAR 1ERRA 1ERRB 14 43 55 28 56 1 2 29 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2APAR LEA LEB SEL ODD/EVEN OEA OEB 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2BPAR 2ERRA 2ERRB 16 41 54 52 51 50 49 47 46 45 44 30 32 33 34 35 37 38 39 40 SH00083 PARITY AND ERROR FUNCTION TABLE INPUTS SEL H H H H L L L L H L t r * ODD/EVEN H H L L H H L L xPAR (A or B) H L H L H L H L of High Inputs Even Odd Even Odd Even Odd Even Odd Even Odd Even Odd Even Odd Even Odd xPAR (B or A) H H L L H H L L H L H L L H L H OUTPUTS ERRt H L L H L H H L H L L H L H H L ERRr* H L L H L H H L H H H H H H H H PARITY MODES Odd Mode Feed-through/check parity Even Mode Odd Mode Generate parity Even Mode = High voltage level = Low voltage level = Transmit-if the data path is from AB then ERRt is ERRA = Receive-if the data path is from AB then ERRr is ERRB Blocked if latch is not transparent 1998 Feb 25 4 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 BLOCK DIAGRAM OE 9-bit Transparent Latch OEB 9-bit Output Buffer LEA A0 A1 A2 A3 A4 A5 A6 A7 APAR LE Parity Generator 1 mux 0 B0 B1 B2 B3 B4 B5 B6 B7 BPAR 9-bit Transparent Latch 9-bit Output Buffer OEA OE 1 mux 0 Parity Generator LE LEB ERRA SEL ERRB ODD/ EVEN (1 of 2 parity blocks) SH00084 FUNCTION TABLE INPUTS OEB H H H H H H L L L L L L OEA H L L L L L H H H H H L SEL X L L L H H L L L H H X LEA X L H X X H H H L H H X LEB X H H L H H X H X L H X 3-State A bus and B bus (input A & B simultaneously) B A, transparent B latch, generate parity from B0 - B7, check B bus parity B A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity B A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity B A, transparent B latch, parity feed-through, check B bus parity B A, transparent A & B latch, parity feed-through, check A & B bus parity A B, transparent A latch, generate parity from A0 - A7, check A bus parity A B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity A B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity A B, transparent A latch, parity feed-through, check A bus parity A B, transparent A & B latch, parity feed-through, check A & B bus parity Output to A bus and B bus (NOT ALLOWED) OPERATING MODE H = High voltage level L = Low voltage level X = Don't care 1998 Feb 25 5 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK VI IOK VOUT IO OUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state DC output current output in High state Storage temperature range -64 -65 to 150 C VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 mA UNIT V mA V mA V DC output diode current DC output voltage3 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Min VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 4.5 0 2.0 0.8 -32 64 5 +85 LIMITS Max 5.5 VCC V V V V mA mA ns/V C UNIT 1998 Feb 25 6 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C Min VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II Low-level output voltage Power-up output low voltage3 Input leakage current Control pins Data pins VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 5.5V; VI = GND or 5.5V VCC = 4.5V; VI = 0.8V VCC = 4.5V; VI = 2.0V VCC = 5.5V; VI = 0 to 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC Additional supply current per input pin2 VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 75 -75 500 2.0 5.0 2.0 -2.0 2.0 -100 0.5 10.5 0.5 0.2 100 50 50 -50 50 -180 1 19 1 1.5 -50 100 50 50 -50 50 -180 1 19 1 1.5 A A A A A mA mA mA mA mA 2.5 3.0 2.0 Typ -0.7 3.1 3.6 2.7 0.36 0.13 0.2 1.0 0.55 0.55 1.0 100 75 -75 A Max -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 Tamb = -40C to +85C Min Max -1.2 V V V V V V A A UNIT IHOLD Bushold current A or B inputs5 74ABTH16899 Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 IOFF IPU/IPD IIH + IOZH IIL + IOZL ICEX IO ICCH ICCL ICCZ ICC NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100sec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Feb 25 7 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500 LIMITS Tamb = +25oC VCC = +5.0V CL = 50pF RL = 500 Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay An to Bn or Bn to An Propagation delay An to BPAR or Bn to APAR Propagation delay An to ERRA or Bn to ERRB Propagation delay APAR to BPAR or BPAR to APAR Propagation delay APAR to ERRA or BPAR to ERRB Propagation delay ODD/EVEN to APAR or BPAR Propagation delay ODD/EVEN to ERRA or ERRB Propagation delay SEL to APAR or BPAR Propagation delay SEL to ERRA or ERRB Propagation delay LEA to Bn or LEB to An Propagation delay LEA to BPAR or LEB to APAR Propagation delay LEA to ERRA or LEB to ERRB Output enable time OEA to An, APAR or OEB to Bn, BPAR Output disable time OEA to An, APAR or OEB to Bn, BPAR 1 2 3 1 6 5 4 8 8 9 9 7 11, 12 11, 12 1.0 1.0 2.5 2.5 2.8 2.8 1.5 1.5 1.0 1.0 2.5 2.5 2.5 2.5 1.5 1.5 2.5 2.5 1.0 1.0 2.8 2.8 1.1 1.2 1.0 1.0 2.5 1.5 Typ 2.7 2.2 4.9 5.0 5.0 4.9 3.1 2.5 2.5 2.5 4.1 3.9 4.1 4.0 3.1 2.6 5.0 4.4 3.1 2.8 5.5 5.1 5.4 5.8 2.6 2.3 3.9 2.8 Max 4.5 3.5 7.2 7.4 9.3 8.0 3.9 3.1 3.3 3.3 5.1 5.0 6.1 5.5 4.0 3.4 7.5 5.9 4.2 4.3 8.0 7.7 8.0 8.0 3.6 3.2 5.6 4.1 Tamb = -40 to +85oC VCC = +5.0V 10% CL = 50pF RL = 500 Min 1.0 1.0 2.5 2.5 2.8 2.8 1.5 1.5 1.0 1.0 2.5 2.5 2.5 2.5 1.5 1.5 2.5 2.5 1.0 1.0 2.8 2.8 1.1 1.2 1.0 1.0 2.5 1.5 Max 5.5 6.9 8.8 8.7 11.0 10.2 4.8 3.9 4.3 3.9 6.1 5.7 7.1 6.6 5.0 4.2 8.3 7.1 5.2 4.7 9.7 9.1 9.2 9.6 5.1 4.5 6.0 4.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL PARAMETER WAVEFORM UNIT AC SETUP REQUIREMENTS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500 LIMITS Tamb = VCC = +5.0V CL = 50pF RL = 500 Min ts(H) ts(L) th(H) th(L) tw(H) Setup time, High or Low An, APAR to LEA or Bn, BPAR to LEB Hold time, High or Low An, APAR to LEA or Bn, BPAR to LEB Pulse width, High LEA or LEB 10 10 10 1.5 1.0 1.5 1.0 3.0 +25oC Tamb = -40 to +85oC VCC = +5.0V 10% CL = 50pF RL = 500 Min 1.5 1.0 1.5 1.0 3.0 ns ns ns SYMBOL PARAMETER WAVEFORM UNIT Typ 0.3 -0.1 0.1 -0.2 1.0 1998 Feb 25 8 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V 1 SEL An, APAR (Bn, BPAR) INPUT VM tPLH VM tPHL VM VM OUTPUT Bn, BPAR (An, APAR) SA00293 Waveform 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR SEL 0 ODD/EVEN 0 1 LEA (LEB) An (Bn) ODD PARITY VM tPHL EVEN PARITY VM ODD PARITY INPUT tPLH VM VM OUTPUT BPAR (APAR) NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00294 Waveform 2. Propagation Delay, An to BPAR or Bn to APAR ODD/EVEN 0 APAR (BPAR) 0 1 LEA (LEB) SEL An (Bn) ODD PARITY VM tPLH EVEN PARITY VM ODD PARITY INPUT tPHL VM VM OUTPUT ERRA (ERRB) NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00295 Waveform 3. Propagation Delay, An to ERRA or Bn to ERRB 1998 Feb 25 9 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 1 APAR (BPAR) An (Bn) EVEN PARITY INPUT ODD/EVEN INPUT VM tPLH VM tPHL VM VM OUTPUT ERRA (ERRB) NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA00296 Waveform 4. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB SEL 0 APAR (BPAR) 0 An (Bn) EVEN PARITY INPUT ODD/EVEN VM tPLH VM tPHL VM VM INPUT BPAR (APAR) OUTPUT NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA00297 Waveform 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR 1998 Feb 25 10 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 ODD/EVEN 0 An (Bn) EVEN PARITY INPUT APAR (BPAR) VM tPLH VM tPHL VM VM INPUT ERRA (ERRB) OUTPUT NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00298 Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB 1 ODD/EVEN APAR (BPAR) 0 An (Bn) EVEN PARITY ODD PARITY EVEN PARITY INPUT LEA (LEB) VM tPLH VM tPHL VM VM INPUT ERRA (ERRB) OUTPUT NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o SA00299 Waveform 7. Propagation Delay, LEA to ERRA or LEB to ERRB 1998 Feb 25 11 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 1 ODD/EVEN APAR (BPAR) 0 An (Bn) EVEN PARITY INPUT SEL VM tPLH VM tPHL VM VM INPUT BPAR (APAR) OUTPUT NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00300 Waveform 8. Propagation Delay, SEL to BPAR or SEL to APAR 1 SEL APAR, An] (BPAR, Bn) INPUT LEA (LEB) VM tPLH VM tPHL VM VM INPUT Bn, BPAR (An, APAR) OUTPUT SA00301 Waveform 9. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An APAR, BPAR, An, Bn VM VM ts(H) LEA, LEB VM The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 10. Data Setup and Hold Times, Pulse Width High 1998 Feb 25 EEEEEEEEEEEEEE EEEE EEEEEEEEEEEEEE EEEE EEEEEEEEEEEEEE EEEE VM VM th(H) ts(L) th(L) VM tw(H) VM EEE EEE EEE SA00302 12 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 OEA, OEB VM tPZH VM tPHZ VM VOH -0.3V 0V An, APAR, Bn, BPAR SA00303 Waveform 11. 3-State Output Enable Time to High Level and Output Disable Time from High Level OEA, OEB VM tPZL VM tPLZ An, APAR, Bn, BPAR VM VOL +0.3V SA00304 Waveform 12. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM VCC VX VIN PULSE GENERATOR RT D.U.T. VOUT RX NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tW 10% 0V tW VM 10% tTLH (tr ) 0V AMP (V) 90% Test Circuit for Open Collector Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open LOAD VALUES OUTPUT R X VX ERROR 100 VCC All other 500 7.0V VM Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. FAMILY INPUT PULSE REQUIREMENTS Amplitude 74ABT/H16 3.0V Rep. Rate 1MHz tw 500ns tR 2.5ns tF 2.5ns SH00009 1998 Feb 25 13 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 1998 Feb 25 14 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1 1998 Feb 25 15 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03507 Philips Semiconductors yyyy mmm dd 16 |
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