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Features
* Serial EEPROM Family for Configuring Altera FLEX(R) 10K Devices * Simple, Easy-to-use 4-pin Interface * E2 Programmable 1M Bit Serial Memories Designed To Store Configuration Programs * * * * * * *
For Programmable Gate Arrays Cascadable To Support Additional Configurations or Future Higher-density Arrays Low-power CMOS EEPROM Process Programmable Reset Polarity Available in the Space-efficient Surface-mount PLCC Package In-System Programmable Via 2-Wire Bus Emulation of 24CXX Serial EPROMs Available in 3.3V 10% LV and 5V 5% C Versions
Description
The AT17C512/010A and AT17LV512/010A (AT17A Series) FPGA Configuration EEPROMs (Configurators) provide and easy-to-use, cost-effective configuration memory for programming Altera FLEX Field Programmable Gate Arrays, FPGA, (the "devices"). The AT17A Series is packaged in the popular 20-pin PLCC package. The AT17A Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17A Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user can select the polarity of the reset function by programming an EEPROM byte. The AT17C/LV512/010A parts generate their own internal clock and can be used as a system "master" for loading the FPGA devices. The Atmel devices also supports a system friendly READY pin and a write protect mechanism. The READY pin is used to simplify system power-up considerations. The WP1 pin is used to protect part of the device memory during in-system programming. The AT17A Series can be programmed with industry standard programmers.
FPGA Serial Configuration Memories AT17C512A AT17LV512A AT17C010A AT17LV010A
Pin Configurations
20-Pin PLCC NC DATA NC VCC NC 3 2 1 20 19 nCS GND NC nCASC NC 9 10 11 12 13 DCLK WP1 NC NC RESET/OE 4 5 6 7 8 18 17 16 15 14 SER_EN NC NC READY NC
Rev. 0974A-04/98
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Block Diagram
SER_EN PROGRAMMING MODE LOGIC PROGRAMMING DATA SHIFT REGISTER
OSC CONTROL ROW ADDRESS COUNTER OSC
24/32
11
ROW DECODER
EEPROM CELL MATRIX 24/32
BIT COUNTER
5
COLUMN DECODER TC
DCLK
OE
nCS
nCASC
DATA
Device Configuration
The control signals for configuration EEPROMs-nCS, OE, and DCLK-interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. The configuration EEPROM device's OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter and the oscillator. When OE is driven low, the configuration EEPROM device resets the address counter and tri-states its DATA pin. The nCS pin controls the output of the AT17A Series. If nCS is held high after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven low, the counter and the DATA output pin are enabled. When OE is driven low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS. When the configurator has driven out all of its data and nCASC is driven low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. 2
FPGA Device Configuration
FPGA devices can be configured with an AT17A Series EEPROM. The AT17A Series device stores configuration data in its EEPROM array and clocks the data out serially with its internal oscillator. The OE, nCS, and DCLK pins supply the control signals for the address counter and the output tri-state buffer. The AT17A Series device sends a serial bitstream of configuration data to its DATA pin, which is connected to the DATA0 input pin on the FPGA device. When configuration data for a FPGA device exceeds the capacity of a single AT17A Series device, multiple AT17A Series devices can be serially linked together. When multiple AT17A Series devices are required, the nCASC and nCS pins provide handshaking between the AT17A Series devices. The position of an AT17A Series device in a chain determines its operation. The first AT17A Series device in a Configurator chain is powered up or reset with nCS low and is configured for FPGA devices protocol. This AT17A Series device supplies all clock pulses to one or more FPGA devices and to any downstream AT17A Series during configuration. The first AT17A Series device also provides the first stream of data to the FPGA devices during
AT17C/LV/512A/010A
AT17C/LV/512A/010A
multi-device configuration. Once the first AT17A Series device finishes sending configuration data, it drives its nCASC pin low, which drives the nCS pin of the second AT17A Series device low. This activates the second AT17A Series device to send configuration data to the FPGA device. The first AT17A Series device clocks all subsequent AT17A Series devices until configuration is complete. Once all configuration data is transferred and nCS on the first AT17A Series device is driven high by CONF_DONE on the FPGA devices, the first AT17A Series device clocks 16 additional cycles to initialize the FPGA device. Then the first AT17A Series device goes into zero-power (idle) state. If nCS on the first AT17A Series device is driven high before all configuration data is transferred-or if the nCS is not driven high after all configuration data is transferred- the nSTATUS is driven low, indicating a configuration error.
Figure 1. FPGA Device Configured with Two AT17A Series Devices
VCC VCC
1KW
1KW
VCC
Device 1 nCONFIG DCLK DATA0 CONF_DONE MSEL0 MSEL1 nSTATUS nCE
AT17C010A Device 1 DCLK DATA nCS OE nCASC
AT17C010A Device 2 DCLK DATA nCS OE
GND
GND
3
Pin Configurations
Pin Number (20-Pin PLCC) 2 4 Pin Name DATA DCLK Pin Type Output I/O Description Serial data output. Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the OE input is held high, the nCS input is held low, and all configuration data has not been transferred to the target device (otherwise, in FPGA 10K master mode, the DCLK pin drives low). WRITE PROTECT (1). Used to protect portions of memory during programming. See programming guide for details. Output enable (active high) and reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. In the mode, if this pin is low (reset), the internal oscillator becomes inactive and DCLK drives low. Chip select input (active low). A low input allows DCLK to increment the address counter and enables DATA to drive out. If the AT17A Series is reset with nCS low, the device initializes as the first device in a daisy-chain. If the AT17A Series is reset with nCS high, the device initializes as the next AT17A Series device in the chain A 0.2 F decoupling capacitor should be placed between the VCC and GND pins. Cascade select output (active low). This output goes low when the address counter has reached its maximum value. In a daisy-chain of AT17A Series devices, the nCASC pin of one device is usually connected to the nCS input pin of the next device in the chain, which permits DCLK to clock data from the next AT17A Series device in the chain. Device selection input, A2. This is used to enable (or select) the device during programming, when SER_EN is Low (see Programming Guide for more details) Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (Recommend a 4.7K Pull-up on this pin if used). Serial enable is normally high during FPGA loading operations. Bringing SER_EN Low, enables the two wire serial interface mode for programming. Power pin.
5 8
WP1 RESET/OE
Input Input
9
nCS
Input
10 12
GND nCASC
Ground Output
A2 15 18 20 READY SER_EN VCC
Input Output Input Power
Absolute Maximum Ratings*
Operating Temperature .................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .............................-0.1V to VCC + 0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V Maximum Soldering Temp. (10 s @ 1/16 in.)..................260C ESD (RZAP = 1.5K, CZAP = 100 pF) ................................ 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
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AT17C/LV/512A/010A
AT17C/LV/512A/010A
Operating Conditions
AT17CXXXA Symbol Description Commercial VCC Industrial Military Supply voltage relative to GND -0C to +70C Supply voltage relative to GND -40C to +85C Supply voltage relative to GND -55C to +125C Min 4.75 4.5 4.5 Max 5.25 5.5 5.5 AT17LVXXXA Min 3.0 3.0 3.0 Max 3.6 3.6 3.6 Units V V V
5
DC Characteristics
VCC = 5V 5% Commercial / 5V 10% Ind./Mil.
Symbol VIH VIL VOH VOL VOH VOL VOH VOL ICCA IL ICCS Description High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode Input or output leakage current (VIN = VCC or GND) Commercial Supply current, standby mode AT17010A/512A Industrial/Military 150 -10 3.5 Military 0.4 10 10 150 V mA A A A 3.6 Industrial 0.37 V V Commercial 0.32 V V Min 2.0 0 3.7 Max VCC 0.8 Units V V V
DC Characteristics
VCC = 3.3V 10%
Symbol VIH VIL VOH VOL VOH VOL VOH VOL ICCA IL ICCS Description High-level input voltage Low-level input voltage High-level output voltage (IOH = -2.5 mA) Low-level output voltage (IOL = +3 mA) High-level output voltage (IOH = -2 mA) Low-level output voltage (IOL = +3 mA) High-level output voltage (IOH = -2 mA) Low-level output voltage (IOL = +2.5 mA) Supply current, active mode Input or output leakage current (VIN = VCC or GND) Commercial Supply current, standby mode Industrial/Military 50 -10 2.4 Military 0.4 5 10 50 V mA A A A 2.4 Industrial 0.4 V V Commercial 0.4 V V Min 2.0 0 2.4 Max VCC 0.8 Units V V V
6
AT17C/LV/512A/010A
AT17C/LV/512A/010A
AC Characteristics
AC Characteristics When Cascading
7
.
AC Characteristics for AT17C010A/512A
VCC = 5V 5% Commercial / VCC = 5V 10% Ind./Mil
Commercial Symbol TOE
(2)
Industrial/Military Min Max 35 45 55 0 Units ns ns ns ns 50 20 20 25 0 20 15 ns ns ns ns ns ns MHz 250 250 2.4 ns ns V
Description OE to Data Delay nCS to Data Delay CLK to Data Delay Data Hold From nCS, OE, or DCLK nCS or OE to Data Float Delay CLK Low Time Slave Mode CLK High Time Slave Mode nCS Setup Time to DCLK (to guarantee proper counting) nCS Hold Time to DCLK (to guarantee proper counting) OE High Time (Guarantees Counter Is Reset) MAX Input Clock Frequency Slave Mode CLK Low Time Master Mode CLK High Time Master Mode Ready Pin Open Collector Voltage
Min
Max 30 45 50
TCE(2) TCAC(2) TOH TDF TLC THC TSCE THCE THOE FMAX TLC THC VRDY
(2) (3)
0 50 20 20 20 0 20 15 30 30 1.2 250 250 2.4
30 30 1.2
AC Characteristics for AT17C010A/512A When Cascading
VCC = 5V 5% Commercial / VCC = 5V 10% Ind./Mil.
Commercial Symbol TCDF TOCK
(3) (2)
Industrial/Military Min Max 50 40 35 30 Units ns ns ns ns
Description DCLK to Data Float Delay DCLK to nCASC Delay CE to nCASC Delay OE to nCASC Delay
Min
Max 50 35 35 30
TOCE(2) TOOE(2) Notes:
1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
8
AT17C/LV/512A/010A
AT17C/LV/512A/0
.
AC Characteristics for AT17C010A/512A
VCC = 3.3V 10% Commercial / VCC = 3.3V 10% Ind./Mil
Commercial Symbol TOE
(2)
Industrial/Military Min Max 55 60 65 0 Units ns ns ns ns 50 25 25 40 0 20 10 ns ns ns ns ns ns MHz 300 300 2.4 ns ns V
Description OE to Data Delay nCS to Data Delay CLK to Data Delay Data Hold From nCS, OE, or DCLK nCS or OE to Data Float Delay CLK Low Time Slave Mode CLK High Time Slave Mode nCS Setup Time to DCLK (to guarantee proper counting) nCS Hold Time to DCLK (to guarantee proper counting) OE High Time (Guarantees Counter Is Reset) MAX Input Clock Frequency Slave Mode CLK Low Time Master Mode CLK High Time Master Mode Ready Pin Open Collector Voltage
Min
Max 50 55 60
TCE(2) TCAC(2) TOH TDF TLC THC TSCE THCE THOE FMAX(4) TLC THC VRDY
(2) (3)
0 50 25 25 35 0 20 15 30 30 1.2 300 300 2.4
30 30 1.2
AC Characteristics for AT17C010A/512A When Cascading
VCC = 3.3V 10% Commercial / VCC =3.3V 10% Ind./Mil.
Commercial Symbol TCDF
(3) (2)
Industrial/Military Min Max 50 55 40 35 Units ns ns ns ns
Description DCLK to Data Float Delay DCLK to nCASC Delay CE to nCASC Delay OE to nCASC Delay
Min
Max 50 50 35 35
TOCK
TOCE(2) TOOE(2) Notes:
1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels. 4. During cascade FMAX = 12.5 MHz
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Ordering Information - 5V Devices
Memory Size (K) 512K
(1)
Ordering Code AT17C512A-10JC AT17C512A-10JI
Package 20J 20J 20J 20J
Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
1M Bit(2)
AT17C010A-10JC AT17C010A-10JI
Ordering Information - 3.3V Devices
Memory Size (K) 512K(1) Ordering Code AT17LV512A-10JC AT17LV512A-10JI 1M Bit(2) AT17LV010A-10JC AT17LV010A-10JI Notes: 1. Use 512K density parts to replace Altera EPC1441. 2. Use 1M density parts to replace Altera EPC1 Package 20J 20J 20J 20J Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
Package Type 20J 20-Lead, Plastic J-Leaded Chip Carrier (PLCC)
10
AT17C/LV/512A/010A
AT17C/LV/512A/0
Packaging Information
20J, 20-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AA
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