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STE53NA50
N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR
TYPE ST E53NA50 V DSS 500 V R DS(on) < 0.085 ID 53 A
s s s s
s s
s s
s
TYPICAL RDS(on) = 0.075 HIGH CURRENT POWER MODULE AVALANCHE RUGGED TECHNOLOGY VERY LARGE SOA - LARGE PEAK POWER CAPABILITY EASY TO MOUNT SAME CURRENT CAPABILITY FOR THE TWO SOURCE TERMINALS EXTREMELY LOW Rth (Junction to case) VERY LOW INTERNAL PARASITIC INDUCTANCE ISOLATED PACKAGE UL RECOGNIZED
ISOTOP
APPLICATIONS s SMPS & UPS s MOTOR CONTROL s WELDING EQUIPMENT s OUTPUT STAGE FOR PWM, ULTRASONIC CIRCUITS
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol V DS V DGR V GS ID ID I DM (*) P to t Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (RGS = 20 k) Gate-source Voltage Drain Current (continuous) at T c = 25 C Drain Current (continuous) at T c = 100 o C Drain Current (pulsed) Total Dissipation at Tc = 25 C Derating Factor T st g Tj V ISO Storage Temperature Max. Operating Junction T emperature Insulation W ithhstand Voltage (AC-RMS)
o o
Value 500 500 30 53 33 212 460 3.68 -55 to 150 150 2500
Unit V V V A A A W W/ o C
o o
C C
V 1/7
(*) Pulse width limited by safe operating area
February 1998
STE53NA50
THERMAL DATA
R t hj-ca se R thc -h Thermal Resistance Junction-case Thermal Resistance Case-heatsink W ith Conductive Grease Applied Max Max 0.27 0.05
o o
C/W C/W
AVALANCHE CHARACTERISTICS
Symb ol I AR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, < 1%) Single Pulse Avalanche Energy o (starting Tj = 25 C, I D = IAR , VDD = 50 V) Max Valu e 26 1014 Unit A mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symb ol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage I D = 1 mA Test Cond ition s V GS = 0 Min. 500 100 1000 400 Typ . Max. Un it V A A nA
V DS = Max Rating Zero G ate Voltage Drain Current (VGS = 0) V DS = Max Rating Gate-body Leakage Current (V DS = 0) V GS = 30 V
T c = 125 C
o
ON ()
Symb ol V GS(th) R DS( on) ID(o n) Parameter Gate Threshold Voltage V DS = VGS Test Cond ition s ID = 1 mA ID = 27 A 53 Min. 2.25 Typ . 3 0.075 Max. 3.75 0.085 Un it V A
Static Drain-source On V GS = 10V Resistance
On State Drain Current V DS > I D(on) x R DS(on) max V GS = 10 V
DYNAMIC
Symb ol g fs () C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse T ransfer Capacitance Test Cond ition s V DS >I D(on ) X V DS = 25 V
RDS(on)MAX
Min. 25
Typ .
Max.
Un it S
I D = 27 A VGS = 0
f = 1 MHz
13 1500 450
16 2000 650
nF pF pF
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STE53NA50
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symb ol t d(on) tr Qg Q gs Q gd Parameter Turn-on Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Cond ition s V DD = 250 V I D = 27 A VGS = 10 V R G = 4.7 (see test circuit, figure 1) V DD = 400 V I D = 53 A VGS = 10 V Min. Typ . 57 92 470 54 219 Max. 80 130 658 Un it ns ns nC nC nC
SWITCHING OFF
Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Cond ition s V DD = 400 V I D = 53 A V GS = 10 V R G = 4.7 (see test circuit, figure 3) Min. Typ . 105 36 145 Max. 145 50 205 Un it ns ns ns
SOURCE DRAIN DIODE
Symb ol I SD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 53 A V GS = 0 1000 31.5 63 Test Cond ition s Min. Typ . Max. 53 212 1.6 Un it A A V ns C A
I SD = 53 A di/dt = 100 A/s o Tj = 150 C V R = 100 V (see test circuit, figure 3)
() Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area
Safe Operating Area for
Thermal Impedance
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STE53NA50
Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STE53NA50
Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
Fig. 1: Switching Times Test Circuits For Resistive Load
Fig. 2: Gate Charge test Circuit
Fig. 3: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STE53NA50
ISOTOP MECHANICAL DATA
DIM. MIN. A B C D E F G H J K L M N O 11.8 8.9 1.95 0.75 12.6 25.15 31.5 4 4.1 14.9 30.1 37.8 4 7.8 8.2 4.3 15.1 30.3 38.2 mm TYP. MAX. 12.2 9.1 2.05 0.85 12.8 25.5 31.7 MIN. 0.466 0.350 0.076 0.029 0.496 0.990 1.240 0.157 0.161 0.586 1.185 1.488 0.157 0.307 0.322 0.169 0.594 1.193 1.503 inch TYP. MAX. 0.480 0.358 0.080 0.033 0.503 1.003 1.248
G B
A
O
N D E F
J C K L M
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H
STE53NA50
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1998 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . ..
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