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HP PA-8000 CLOCK SOURCE
ClockWorksTM PRELIMINARY SY89801A
FEATURES
s s s s s 3.3V, -1.9V power suppies Differential LVPECL clock input Differential HSTL/LVPECL outputs Compatible with HP PA-8000 microprocessors Low-jitter source for all PA-8000 required timing signals s Available in 44-pin MQUAD package
DESCRIPTION
Micrel-Synergy's SY89801A PLL based clock generator provides, in a single chip, all the necessary clocks for HewlettPackard's PA-8000 Microprocessor. Utilizing Micrel-Synergy's advanced PLL technology, the SY89801A accepts a Positive-ECL (PECL) reference clock input at 100MHz-132MHz, and provides precisely aligned, ultra-low-jitter ratios of frequencies necessary for the operation of the processor. In addition, the SY89801A provides the "USYNC" synchronizing signals as required by the PA-8000. The frequency ratios are 1:1, 4:3, 3:2, 5:3 and 2:1. To facilitate direct interfacing to the PA-8000, the SY89801A operates across +3.3 volt and -1.9 volt supplies. The processor clock (PCLK), runway clock (RCLK) , and USYNC outputs are HSTL-compatible. Additionally, there is a PECL-compatible runway clock output (RCLKLV). The SY89801A requires only a simple external series-RC loop filter. Coupling Micrel-Synergy's advanced PLL technology with our proprietary ASSET bipolar process has produced a Timing Generator IC which meets the stringent requirements of the PA-8000 P, while setting a new standard for performance and flexibility.
PIN CONFIGURATION
VEE NC NC REF_CLK REF_CLK VCC
6
5
4
3
2
1 44 43 42 41 40 39 38 37 36
VEEA NC NC FILP FILN VCCA NC NC NC NC NC
RCLKLV RCLKLV VEE
RCLK RCLK
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VEE PCLK1 PCLK1 PCLK2 PCLK2 VCC USYNC USYNC NC NC VCC
TOP VIEW MQUAD M44-1
35 34 33 32 31 30 29
VCC NC NC NC
FSEL1 FSEL2 VCC
NC FSEL0
RST VEE
PIN NAMES
Pin REF_CLK, REF_CLK FILP, FILN VCCA, VEEA RST FSEL2-0 USYNC, USYNC PCLK1-2, PCLK1-2 RCLK, RCLK RCLKLV, RCLKLV Function Differential Input Ref. Clock Filter Pins (Positive & Negative) Analog VCC, VEE Master Reset LVPECL Frequency Select Pins Diff. HSTL Sync Signal for PA-8000 Diff. HSTL Processor Clock Signal Diff. HSTL Runway Clock Signal Diff. LVPECL Clock Signal
Rev.: E
Amendment: /0
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Issue Date: November 1998
Micrel
ClockWorksTM PRELIMINARY SY89801A
BLOCK DIAGRAM
LOOP FILTER VCC 2 AVCC 3 VCCO 2
REFCLK (100-132MHz)
(PECL)
LF VCO (600-800)
MF VCO (800-1060)
HF VCO (1000-1320)
f/2
/3
f/2
/4
f/2
/5 /
2/ 3/ 4/ 5 f/2
PCLK1
(HSTL)
PCLK2
(HSTL)
SYNC LOGIC VCO ENAB
f/2
USYNC
(HSTL)
RCLK
(HSTL)
FSEL
(PECL)
3
DECODE
RCLKLV
(PECL)
2 RESET
(PECL)
2 DVEE
3 AVEE
TEST
(PECL)
GND
2
Micrel
ClockWorksTM PRELIMINARY SY89801A
3.3V DC ELECTRICAL CHARACTERISTICS
VCC = VCCA = 3.3V 10%; VEEA = VEE = -1.9V
Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current (VCC) Min. 3.0 -- Typ. -- 250 Max. 3.6 321 Unit V mA Condition VEE = -1.9V
PECL DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V 10%; VEE = -1.9V
Symbol VOH VOL VIH VIL VBB Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage PECL Threshold Min. VCC - 1.075 VCC - 1.860 VCC - 1.165 VCC - 1.810 -- Typ. -- -- -- -- VCC - 1.35 Max. VCC - 0.830 VCC - 1.570 VCC - 0.880 VCC - 1.475 -- Unit V V V V V Condition
HSTL DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V 10%; VEE = -1.9V
Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage Min. VCC - 2.3 VCC - 3.1 Typ. -- -- Max. VCC - 2.1 VCC - 2.9 Unit V V Condition
AC ELECTRICAL CHARACTERISTICS(1)
VCC = 3.3V 10%; VEE = -1.9V
TA = 0C Symbol fVCO fMAX tskew(2) Parameter Maximum VCO Frequency TA = +25C TA = +70C Condition Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 1320 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 100 100 500 250 +50 51 800 1320 264 132 -- -- -- -- -- -50 49 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 100 100 500 250 +50 51 800 1320 264 132 -- -- -- -- -- -50 49 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 100 100 500 250 +50 51 800 MHz MHz MHz ps ps ps ps ps ps % ps Peak to Peak, Cycle to Cycle Measured at differential crossover
Maximum PCLK Output Frequency 264 Maximum RCLK Output Frequency 132 PCLK to PCLK RCLK to RCLKLV PCLK to RCLK PCLK (neg.) to USYNC Phase Error RCLK to REF_CLK Output Jitter Output Duty Cycle Rise/Fall Times (20% to 80%) -- -- -- -- -- -50 49 100
tpe tj(2) tdc(2) tr (2) tf
NOTES: 1. All HSTL outputs terminated into 50 ohms in parallel with 3pf to GND. 2. tskew, tj, tdc, tr and tf are specified by HP for the PA-8000. This is our best information as of the date of this document.
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Micrel
ClockWorksTM PRELIMINARY SY89801A
APPLICATIONS INFORMATION
The following table lists the various PCLK and RCLK ratios supported by the SY89801A and the corresponding PCLK, RCLK, FB and VCO frequencies. The table is arranged in order of increasing PCLK:RCLK ratio. The table was designed to balance several constraints: s 2.5:1 VCO frequency range s Maximum system frequency of 120MHz plus 10% margin s Maximum output frequency of 264MHz
FSEL <2:0> 000 001 010 011 100 101 110 111
PCLK:RCLK 1:1 4:3 3:2 5:3 2:1 1:1 1:1 n/a
fPCLK (MHz) 100-132 133.3-176 150-198 166.7-220 200-264 100-132 100-132 n/a
fRCLK (MHz) 100-132 100-132 100-132 100-132 100-132 100-132 100-132 n/a
VCO / ratios VCO/P:VCO/R 8:8 6:8 4:6 6:10 4:8 6:6 10:10 n/a
fVCO (MHz) 800-1056 800-1056 600-792 1000-1320 800-1056 600-792 1000-1320 n/a
LOOP FILTER COMPONENT SELECTION
R
C1
filp
filn
R
= 500 10%
C1 = 1000pF 10%
PRODUCT ORDERING CODE
Ordering Code SY89801AMC SY89801AMCA
(1)
Package Type M44-1 M44-1
Operating Range Commercial Commercial
NOTES: 1. "A" denotes enhanced 200MHz testing.
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Micrel
ClockWorksTM PRELIMINARY SY89801A
44 LEAD MLCC (M44-1)
Rev. 02
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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