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Dual Interface for Flat Panel Displays AD9882
FEATURES Analog Interface 140 MSPS Maximum Conversion Rate Programmable Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 140 MSPS 3.3 V Power Supply Full Sync Processing Midscale Clamping 4:2:2 Output Format Mode Digital Interface DVI 1.0 Compatible Interface 112 MHz Operation High Skew Tolerance of 1 Full Input Clock Sync Detect for "Hot Plugging" Supports High Bandwidth Digital Content Protection APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converter Microdisplays Digital TV FUNCTIONAL BLOCK DIAGRAM
AD9882
ANALOG INTERFACE 8 REF A/D ROUT REFBYPASS
RAIN
CLAMP
GAIN
CLAMP
A/D
8
GOUT
BAIN SOGIN HSYNC FILT VSYNC
CLAMP
A/D
8
BOUT 8 8 8 ROUT GOUT BOUT
DATACK SYNC PROCESSING AND CLOCK GENERATION HSOUT VSOUT SOGOUT
SCL SDA A0 SERIAL REGISTER AND POWER MANAGEMENT MUXES
DATACK HSOUT VSOUT SOGOUT DE
DIGITAL INTERFACE RX0+ RX0- RX1+ RX1- RX2+ RX2- RXC+ RXC- RTERM DDCSCL DDCSDA MCL MDA 8 DVI RECEIVER 8 8 ROUT GOUT BOUT DATACK DE HSYNC HDCP VSYNC
GENERAL DESCRIPTION
The AD9882 offers designers the flexibility of an analog interface and Digital Visual Interface (DVI) receiver integrated on a single chip. Also included is support for High bandwidth Digital Content Protection (HDCP).
Analog Interface
The AD9882 is a complete 8-bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 1024 at 75 Hz). The analog interface includes a 140 MHz triple ADC with internal 1.25 V reference, a Phase Locked Loop (PLL), and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and Hsync. Threestate CMOS outputs may be powered from 2.2 V to 3.3 V. The AD9882's on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is typically 500 ps p-p at 140 MSPS. The AD9882 also offers full sync processing for composite sync and Sync-onGreen (SOG) applications. REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
Digital Interface
The AD9882 contains a DVI 1.0 compatible receiver and supports display resolutions up to SXGA (1280 1024 at 60 Hz). The receiver features an intra-pair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9882 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP v1.0 protocol. Fabricated in an advanced CMOS process, the AD9882 is provided in a space-saving 100-lead LQFP surface-mount plastic package and is specified over the 0C to 70C temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9882-SPECIFICATIONS
ANALOG INTERFACE ELECTRICAL CHARACTERISTICS
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias Current Input Full-Scale Matching Offset Adjustment Range REFERENCE OUTPUT Output Voltage Temperature Coefficient SWITCHING PERFORMANCE1 Maximum Conversion Rate Minimum Conversion Rate Data to Clock Skew Serial Port Timing tBUFF tSTAH tDHO tDAL tDAH tDSU tSTASU tSTOSU Hsync Input Frequency Maximum PLL Clock Rate Minimum PLL Clock Rate PLL Jitter Sampling Phase Tempco DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Current, High (IIH) Input Current, Low (IIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) Duty Cycle, DATACK Output Coding
1
(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)
AD9882KST-100 Min Typ Max 8 AD9882KST-140 Typ Max 8 +1.25/-1.0 +1.35/-1.0 1.85 2.0 0.5 0.5 Guaranteed +1.35/-1.0 +1.45/-1.0 2.0 2.3
Test Temp Level
Min
Unit Bits LSB LSB LSB LSB
25C Full 25C Full Full
I VI I VI VI
0.5 0.5 Guaranteed
Full Full 25C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C Full Full Full Full Full Full 25C Full Full Full
VI VI V IV VI VI VI V VI IV IV VI VI VI VI VI VI VI VI IV VI IV IV IV IV VI VI IV IV V IV IV IV
0.5 1.0 100 1.5 49 1.25 50 1 8.0 56 1.32 1.0 100 1.5 49 1.25 50
0.5
46 1.20
46 1.20
1 8.0 56 1.32
V p-p V p-p ppm/C mA % FS % FS V ppm/C MSPS MSPS ns ms ms ms ms ms ns ms ms kHz MHz MHz ps p-p ps p-p ps/C V V mA mA pF V V %
100 -0.5 4.7 4.0 0 4.7 4.0 250 4.7 4.0 15 100 500 15 2.6 0.8 -1.0 +1.0 3 VDD - 0.1 45 50 Binary 0.4 55 10 +2.0
140 -0.5 4.7 4.0 0 4.7 4.0 250 4.7 4.0 15 140 500 15 2.6 0.8 -1.0 +1.0 3 VDD - 0.1 45 50 Binary 0.4 55 10 +2.0
110 12 7002 10002
110 12 7002 10002
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AD9882
Parameter POWER SUPPLY VD Supply Voltage VDD Supply Voltage PVD Supply Voltage ID Supply Current (VD) IDD Supply Current (VDD)3 IPVD Supply Current (PVD) Total Supply Current Power-Down Supply Current DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Signal-to-Noise Ratio (SNR) fIN = 2.3 MHz Crosstalk THERMAL CHARACTERISTICS 4 JA Junction-to-Ambient
1
Test Temp Level Full Full Full 25C 25C 25C Full Full 25C 25C Full IV IV IV V V V VI VI V V V V
Min 3.15 2.2 3.15
AD9882KST-100 Typ Max 3.3 3.3 3.3 162 47 19 228 30 300 44 55 43 3.45 3.6 3.45
Min 3.15 2.20 3.15
AD9882KST-140 Typ Max 3.3 3.3 3.3 181 63 21 265 30 300 43 55 43 3.45 3.6 3.45
Unit V V V mA mA mA mA mA MHz dB dBc C/W
237 35
274 35
NOTES 1 Drive Strength = 11. 2 VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693. 3 DATACK Load = 15 pF, Data Load = 5 pF. 4 Simulated typical performance with package mounted to a four-layer board. Specifications subject to change without notice.
REV. A
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AD9882 DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
Parameter RESOLUTION DC DIGITAL I/O Specifications High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Output Leakage Current (IOL) DC SPECIFICATIONS Output High Drive (IOHD)(VOUT = VOH) Output Low Drive (IOLD)(VOUT = VOL) DATACK High Drive (VOHC)(VOUT = VOH) DATACK Low Drive (VOLC)(VOUT = VOL) Differential Input Voltage Single-Ended Amplitude POWER SUPPLY VD Supply Voltage VDD Supply Voltage PVD Supply Voltage ID Supply Current (Typical Pattern)1 IDD Supply Current (Typical Pattern)1, 2 IPVD Supply Current (Typical Pattern)1 Total Supply Current with HDCP (Typical Pattern)1, 2 ID Supply Current (Worst-Case Pattern)3 IDD Supply Current (Worst-Case Pattern)2, 3 IPVD Supply Current (Worst-Case Pattern)3 Total Supply Current with HDCP (Worst-Case Pattern)2, 3 Power-Down Supply Current (IPD) Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C 25C Full 25C 25C 25C Full Full VI VI IV IV IV V V V V V V V V V V V V IV IV IV IV V V V IV V V V IV VI 75 3.15 2.2 3.15 3.3 3.3 3.3 269 32 54 355 276 127 54 457 30 2.6 0.8 2.4 -10 11 8 5 -7 -6 -5 28 14 7 -15 -9 -7 800 3.45 3.6 3.45 0.4 +10
(VD = 3.3 V, VDD = 3.3 V, Clock = Maximum, unless otherwise noted.)
Temp Test Level Min AD9882KST Typ Max 8 Unit Bits V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mV V V V mA mA mA mA mA mA mA mA mA
Conditions
High Impedance Output Drive = High Output Drive = Med Output Drive = Low Output Drive = High Output Drive = Med Output Drive = Low Output Drive = High Output Drive = Med Output Drive = Low Output Drive = High Output Drive = Med Output Drive = Low
367
468 35
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AD9882
Parameter AC SPECIFICATIONS Intra-Pair (+ to -) Differential Input Skew (TDPS) Channel-to-Channel Differential Input Skew (TCCS) Low-to-High Transition Time for Data (DLHT) Conditions Temp Test Level Min AD9882KST Typ Max Unit
Full Full
IV IV
360 1
ps Clock Period
Output Drive = High, CL = 10 pF Output Drive = Med, CL = 7 pF Output Drive = Low, CL = 5 pF Output Drive = High, CL = 10 pF Output Drive = Med, CL = 7 pF Output Drive = Low, CL = 5 pF Output Drive = High, CL = 10 pF Output Drive = Med, CL = 7 pF Output Drive = Low, CL = 5 pF Output Drive = High, CL = 10 pF Output Drive = Med, CL = 7 pF Output Drive = Low, CL = 5 pF
Full Full Full
IV IV IV
2.2 2.5 3.2
ns ns ns
Low-to-High Transition Time for DATACK (DLHT)
Full Full Full
IV IV IV
1.0 1.6 2.1
ns ns ns
High-to-Low Transition Time for Data (DHLT)
Full Full Full
IV IV IV
2.2 1.9 1.7
ns ns ns
High-to-Low Transition Time for DATACK (DHLT)
Full Full Full Full Full Full
IV IV IV IV IV VI
1.0 1.0 1.4 +2.0 50 112
ns ns ns ns % MHz
Data-to-Clock Skew4 Duty Cycle, DATACK4 DATACK Frequency (FCIP)
-0.5 40 25
46
NOTES 1 The typical pattern contains a grayscale area, Output Drive = High. 2 DATACK Load = 10 pF, Data Load = 10 pF. 3 The worst-case pattern contains a black and white checkerboard pattern, Output Drive = High. 4 DRIVE STRENGTH = 11 Specifications subject to change without notice.
REV. A
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AD9882
ABSOLUTE MAXIMUM RATINGS*
VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . -25C to +85C Storage Temperature . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . 175C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
EXPLANATION OF TEST LEVELS Test Level
I. II.
100% production tested. 100% production tested at 25C and sample tested at specified temperatures.
III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25C; guaranteed by design and characterization testing.
ORDERING GUIDE
Model AD9882KST-100 AD9882KST-140 AD9882/PCB
Temperature Range 0C to 70C 0C to 70C 25C
Package Option ST-100 ST-100 Evaluation Board
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9882 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD9882
PIN CONFIGURATION
89 SOGOUT
85 DATACK
99 RED<0>
98 RED<1>
97 RED<2>
96 RED<3>
95 RED<4>
94 RED<5>
93 RED<6>
92 RED<7>
88 HSOUT
79 HSYNC
87 VSOUT
80 VSYNC
91 GND
84 GND
82 MDA
81 MCL
78 SDA
100 VDD
77 SCL
VDD
83 VDD
86 DE
GND GREEN<7> GREEN<6> GREEN<5> GREEN<4> GREEN<3> GREEN<2> GREEN<1> GREEN<0>
76 A0
90
1 2 3 4 5 6 7 8 9
75 74 73 72 71 70 69 68 67 66 65
GND MIDBYPASS REFBYPASS VD GND RAIN VD GND VD GND GAIN SOGIN VD GND VD GND BAIN VD GND VD GND DDCSDA DDCSCL PVD GND
VDD 10 GND 11 BLUE<7> 12 BLUE<6> 13 BLUE<5> 14 BLUE<4> 15 BLUE<3> 16 BLUE<2> 17 BLUE<1> 18 BLUE<0> 19 VDD 20 GND 21 CTL 0 22 CTL 1 23 CTL 2 24 CTL 3 25
GND 26 VD 27 RTERM 28 VD 29 VD 30 GND 31 RX0- 32 RX0+ 33 GND 34 RX1- 35 RX1+ 36 GND 37 RX2- 38 RX2+ 39 GND 40 RXC+ 41 RXC- 42 VD 43 PVD 44 GND 45 PVD 46 GND 47 FILT 48 PVD 49 GND 50
AD9882
TOP VIEW (Not to Scale)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
REV. A
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AD9882
Table I. Complete Pinout List
Pin Type
Mnemonic
Function Analog Input for Converter R Analog Input for Converter G Analog Input for Converter B Horizontal Sync Input Vertical Sync Input Input for Sync-on-Green
Value 0.0 V to 1.0 V 0.0 V to 1.0 V 0.0 V to 1.0 V 3.3 V CMOS 3.3 V CMOS 0.0 V to 1.0 V
Pin Number Interface 70 65 59 79 80 64 88 87 89 73 74 48 Analog Analog Analog Analog Analog Analog Both Both Analog Analog Analog Analog Both Both Both Both 78 77 76 92-99 2-9 12-19 85 33 32 36 35 39 38 41 42 Both Both Both Both Both Both Both Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital
Analog RAIN Video Inputs GAIN BAIN External Sync/Clock Sync Outputs References PLL Filter Power Supply HSYNC VSYNC SOGIN HSOUT VSOUT SOGOUT
HSYNC Output Clock (Phase-Aligned with DATACK) 3.3 V CMOS VSYNC Output Clock 3.3 V CMOS Sync-on-Green Slicer Output 3.3 V CMOS 1.25 V
REFBYPASS Internal Reference Bypass MIDBYPASS Internal Midscale Voltage Bypass FILT VD VDD PVD GND SDA SCL A0 Red [7:0] Green [7:0] Blue [7:0] DATACK Connection for External Filter Components for Internal PLL Analog Power Supply Output Power Supply PLL Power Supply Ground Serial Port Data I/O Serial Port Data Clock (100 kHz Max) Serial Port Address Input Outputs of Converter "Red", Bit 7 is the MSB Outputs of Converter "Green", Bit 7 is the MSB Outputs of Converter "Blue", Bit 7 is the MSB Data Output Clock for the Analog and Digital Interface Digital Input Channel 0 True Digital Input Channel 0 Complement Digital Input Channel 1 True Digital Input Channel 1 Complement Digital Input Channel 2 True Digital Input Channel 2 Complement Digital Data Clock True Digital Data Clock Complement Data Enable Decoded Control Bits Sets Internal Termination Resistance HDCP Slave Serial Port Data Clock HDCP Slave Serial Port Data I/O HDCP Master Serial Port Data Clock HDCP Master Serial Port Data I/O
3.15 V to 3.45 V 2.2 V to 3.6 V 3.15 V to 3.45 V 0V 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS
Serial Port Control Data Outputs Data Clock Output
Digital Video RX0+ Data Inputs RX0- RX1+ RX1- RX2+ RX2- Digital Video RXC+ Clock Inputs RXC- Data Enable DE Control Bits CTL [0:3] RTERM HDCP RTERM DDCSCL DDCSDA MCL MDA
3.3 V CMOS 3.3 V CMOS
86 22-25 28
3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS
53 54 81 82
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REV. A
AD9882
PIN DESCRIPTIONS OF SHARED PINS BETWEEN ANALOG AND DIGITAL INTERFACES HSOUT Horizontal Sync Output DATA OUTPUTS RED Data Output, RED Channel GREEN Data Output, GREEN Channel BLUE Data Output, BLUE Channel
A reconstructed and phase-aligned version of the video Hsync. The polarity of this output can be controlled via a serial bus bit. In analog interface mode, the placement and duration are variable. In digital interface mode, the placement and duration are set by the graphics transmitter. VSOUT Vertical Sync Output The separated Vsync from a composite signal or a direct pass-through of the Vsync input. The polarity of this output can be controlled via a serial bus bit. The placement and duration in all modes is set by the graphics transmitter.
The main data outputs. Bit 7 is the MSB. These outputs are shared between the two interfaces and behave according to which interface is active. Refer to the sections on the two interfaces for more information on how these outputs behave. DATACK Data Output Clock Just like the data outputs, the data clock output is shared between the two interfaces. It behaves differently depending on which interface is active. Refer to the sections on the two interfaces to determine how this pin behaves.
SERIAL PORT (2-WIRE) SDA Serial Port Data I/O SCL Serial Port Data Clock A0 Serial Port Address Input
For a full description of the 2-wire serial register, refer to the Control Port section on 2-Wire Serial Control.
Table II. Analog Interface Pin List
Pin Type Analog Video Inputs External Sync/Clock Sync Outputs
Mnemonic RAIN GAIN BAIN HSYNC VSYNC SOGIN HSOUT VSOUT SOGOUT REFBYPASS MIDBYPASS FILT VD PVD VDD GND
Function Analog Input for Converter R Analog Input for Converter G Analog Input for Converter B Horizontal SYNC Input Vertical SYNC Input Sync-on-Green Input Hsync Output (Phase-Aligned with DATACK) Vsync Output Composite SYNC Internal Reference Bypass Internal Midscale Voltage Bypass Connection for External Filter Components for Internal PLL Main Power Supply PLL Power Supply (Nominally 3.3 V) Output Power Supply Ground
Value 0.0 V to 1.0 V 0.0 V to 1.0 V 0.0 V to 1.0 V 3.3 V CMOS 3.3 V CMOS 0.0 V to 1.0 V 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 1.25 V
Pin Number 70 65 59 79 80 64 88 87 89 73 74 48
Voltage Reference Clamp Voltages PLL Filter Power Supply
3.15 V to 3.45 V 3.15 V to 3.45 V 2.2 V to 3.6 V 0V
REV. A
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AD9882
PIN FUNCTION DETAIL (ANALOG INTERFACE) INPUTS RAIN Analog Input for RED Channel Analog Input for GREEN Channel GAIN BAIN Analog Input for BLUE Channel SOGOUT Sync-on-Green Slicer Output
High impedance inputs that accept the RED, GREEN, and BLUE channel graphics signals, respectively. For RGB, the three channels are identical and can be used for any colors, but colors are assigned for convenient reference. For proper 4:2:2 formatting in a YPbPr application, the Y must be connected to the GAIN input, the Pb must be connected to the BAIN input, and the Pr must be connected to the RAIN input. They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation.
HSYNC Horizontal Sync Input FILT
This pin can be programmed to produce either the output from the Sync-on-Green slicer comparator or an unprocessed but delayed version of the Hsync input. See the Sync Processing Block Diagram, Figure 18, to view how this pin is connected. Note: The output from this pin is the composite SYNC without additional processing from the AD9882.
External Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics on this node.
REFBYPASS Internal Reference BYPASS
This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by Serial Register Bit 10H, Bit 6 (Hsync Polarity). Only the leading edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the falling edge of Hsync is used. When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V. Electrostatic Discharge (ESD) protection diodes will conduct heavily if this pin is driven more than 0.5 V above the maximum tolerance voltage (3.3 V), or more than 0.5 V below ground.
VSYNC SOGIN Vertical Sync Input DATACK
Bypass for the internal 1.25 V band gap reference. It should be connected to ground through a 0.1 mF capacitor. The absolute accuracy of this reference is 4%, and the temperature coefficient is 50 ppm, which is adequate for most AD9882 applications. If higher accuracy is required, an external reference may be employed instead.
MIDBYPASS Midscale Voltage Reference BYPASS
Bypass for the internal midscale voltage reference. It should be connected to ground through a 0.1 mF capacitor. The exact voltage varies with the gain setting of the RED channel.
HSOUT Horizontal Sync Output
A reconstructed and phase-aligned version of the Hsync input. The duration of Hsync can only be programmed on the analog interface, not the digital.
Data Output Clock
This is the input for vertical sync.
Sync-on-Green Input
The data clock output signal is used to clock the output data and HSOUT into external logic. It is produced by the internal clock generator and is synchronous with the internal pixel sampling clock. When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The Data, DATACK, and HSOUT outputs are all moved so the timing relationship among the signals is maintained.
VSOUT Vertical Sync Output
This input is provided to assist with processing signals with embedded sync, typically on the GREEN channel. The pin is connected to a high speed comparator with an internally generated threshold, which is set by the value of register 0FH, Bits 7-3. When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting digital output on SOGOUT. When not used, this input should be left unconnected. For more details on this function and how it should be configured, refer to the Syncon-Green section.
The separated Vsync from a composite signal or a direct pass-through of the Vsync input. The polarity of this output can be controlled via Register 10H, Bit 2. The placement and duration in all modes is set by the graphics transmitter.
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AD9882
RED GREEN BLUE Data Output, RED Channel Data Output, GREEN Channel Data Output, BLUE Channel
VDD
These are the main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained. Please refer to the timing diagrams for more information.
POWER SUPPLY VD Main Power Supply PVD
Digital Output Power Supply A large number of output pins (up to 25) switching at high speed (up to 140 MHz) generates a lot of power supply transients. These supply pins are identified separately from the VD pins so special care can be taken to minimize output noise transferred into the sensitive analog circuitry. If the AD9882 is interfacing with lower voltage logic, VDD may be connected to a lower supply voltage (as low as 2.2 V) for compatibility.
Clock Generator Power Supply
These pins supply power to the main elements of the circuit. They should be as quiet as possible.
GND
The most sensitive portion of the AD9882 is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide noise-free power to these pins.
Ground
The ground return for all circuitry on chip. It is recommended that the AD9882 be assembled on a single solid ground plane, with careful attention to ground current paths.
Table III. Interface Selection Controls
AIO (0FH Bit 2) 1
Analog Interface Detect X 0
Digital Interface Detect X 0 1 0 1
AIS (0FH Bit 1) 0 1 X X X 0 1
Active Interface Analog Digital None Digital Analog Analog Digital
Description Force the analog interface active. Force the digital interface active. Neither interface was detected. Both interfaces are powered down. The digital interface was detected. Power down the analog interface. The analog interface was detected. Power down the digital interface. Both interfaces were detected. The analog interface gets priority. Both interfaces were detected. The digital interface gets priority.
0 0 1 1
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AD9882
Table IV. Power-Down Modes, 4:2:2 and 4:4:4 Format Descriptions
Mode Soft PowerDown (Seek Mode) Digital Interface On
Analog Digital Active Power- Interface Interface Interface Down1 Detect2 Detect3 Override 1 0 0 0
Active Interface 4:2:2 Select Formatting Data Sheet Signals Powered On X X Serial bus, digital interface clock detect, analog interface clock detect, SOG Serial bus; digital interface and analog interface activity detect; SOG, band gap reference; red, green, and blue outputs Serial bus; analog interface and digital interface clock detect; SOG, band gap reference; red, green, and blue outputs Serial bus; analog interface and digital interface clock detect; SOG, band gap reference; red and green outputs only Same as Analog Interface on 4:4:4 Mode Same as Analog Interface on 4:2:2 Mode Same as Digital Interface Mode
1
0
1
0
X
X
Analog 1 Interface On 4:4:4 Format Analog 1 Interface On 4:2:2 Format Serial Bus Arbitrated Interface Serial Bus Arbitrated Interface Serial Bus Arbitrated Interface Override to Analog Interface Override to Analog Interface Override to Digital Interface Absolute PowerDown 1
1
0
0
X
0
1
0
0
X
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
X
1
1
X
1
0
0
Same as Analog Interface 4:4:4 Mode Same as Analog Interface 4:2:2 Mode Same as Digital Interface Mode
1
1
X
1
0
1
1
X
1
1
1
X
0
X
X
X
X
X
Serial Bus
NOTES 1 Power-down is controlled via Bit 1 in Serial Bus Register 14H. 2 Analog Interface Detect is determined by OR-ing Bits 7, 6, and 5 in Serial Bus Register 15H. 3 Digital Interface Detect is determined by Bit 4 in Serial Bus Register 15H.
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AD9882
THEORY OF OPERATION (INTERFACE DETECTION) Active Interface Detection and Selection
The AD9882 includes circuitry to detect whether an interface is active or not. See Table III. For detecting the analog interface, the circuitry monitors the presence of Hsync, Vsync, and Sync-on-Green. The result of the detection circuitry can be read from the 2-wire serial interface bus at Address 15H, Bits 7, 5, and 6, respectively. If one of these sync signals disappears, the maximum time it takes for the circuitry to detect it is 100 ms. For detecting the digital interface, there are two stages of detection. The first stage searches for the presence of the digital interface clock. The circuitry for detecting the digital interface clock is active even when the digital interface is powered down. The result of this detection stage can be read from the 2-wire serial interface bus at Address 15H, Bit 4. If the clock disappears, the maximum time it takes for the circuitry to detect it is 100 ms. Once a digital interface clock is detected, the digital interface is powered up and the second stage of detection begins. During the second stage, the circuitry searches for 32 consecutive DEs. Once 32 DEs are found, the detection process is complete. There is an override for the automatic interface selection. It is the AIO (Active Interface Override) bit, Register 0FH, Bit 2. When the AIO bit is set to logic "0," the automatic circuitry will be used. When the AIO bit is set to logic "1," the AIS (Active Interface Select) bit (Register 0FH, Bit 1) will be used to determine the active interface rather than the automatic circuitry.
Power Management
THEORY OF OPERATION AND DESIGN GUIDE (ANALOG INTERFACE) General Description
The AD9882 is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel monitors or projectors. The device is ideal for implementing a computer interface for HDTV monitors or as the front end to high performance video scan converters. Implemented in a high performance CMOS process, the interface can capture signals with pixel rates of up to 140 MHz. The AD9882 includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. All controls are programmable via a 2-wire serial interface. Full integration of these sensitive analog functions makes the system design straightforward and less sensitive to the physical and electrical environment. With a typical power dissipation of only 875 mW and an operating temperature range of 0C to 70C, the device requires no special environmental considerations.
Input Signal Handling
The AD9882 has three high impedance analog input pins for the RED, GREEN, and BLUE channels. They will accommodate signals ranging from 0.5 V to 1.0 V p-p. Signals are typically brought onto the interface board via a DVI-I connector, a 15-pin D connector, or BNC connectors. The AD9882 should be located as close as practical to the input connector. Signals should be routed via matched-impedance traces (normally 75 W) to the IC input pins. At that point, the signal should be resistively terminated (75 W to the signal ground return) and capacitively coupled to the AD9882 inputs through 47 nF capacitors. These capacitors form part of the dc restoration circuit. See Figure 1. In an ideal world of perfectly matched impedances, the best performance can be obtained with the widest possible signal bandwidth. The wide bandwidth inputs of the AD9882 (300 MHz) can track the input signal continuously as it moves from one pixel level to the next and digitize the pixel during a long, flat pixel time. In many systems, however, there are mismatches, reflections, and noise, which can result in excessive ringing and distortion of the input waveform. This makes it more difficult to establish a sampling phase that provides good image quality. It has been shown that a small inductor in series with the input is effective in rolling off the input bandwidth slightly and providing a high quality signal over a wider range of conditions. Using a Fair-Rite #2508051217Z0 High Speed Signal Chip Bead inductor in the circuit of Figure 1 gives good results in most applications.
RGB INPUT 75 47nF RAIN GAIN BAIN
The AD9882 is a dual interface device with shared outputs. Only one interface can be used at a time. For this reason, the chip automatically powers down the unused interface. When the analog interface is being used, most of the digital interface circuitry is powered down, and vice versa. This helps to minimize the AD9882 total power dissipation. In addition, if neither interface has activity on it, then the chip powers down both interfaces. The AD9882 uses the activity detect circuits, the active interface bits in Serial Register 15H, the active interface override bits in Register 0FH, Bits 2 and 1, and the power-down bit in Register 14H, Bit 1, to determine the correct power state. In a given power mode, not all circuitry in the inactive interface is powered down completely. When the digital interface is active, the band gap reference Hsync, Vsync, and SOG detect circuitry remain powered up. When the analog interface is active, the digital interface clock detect circuit is not powered down. Table IV summarizes how the AD9882 determines what power mode to be in and what circuitry is powered on/off in each of these modes. The powerdown command has priority, then the active interface override, and then the automatic circuitry.
Figure 1. Analog Input Interface Circuit
REV. A
-13-
AD9882
Hsync, Vsync Inputs
The AD9882 receives a horizontal sync signal and uses it to generate the pixel clock and clamp timing. This can be either a sync signal directly from the graphics source or a preprocessed TTL or CMOS level signal. The Hsync input includes a Schmitt trigger buffer and is capable of handling signals with long rise times, with superior noise immunity. In typical PC based graphic systems, the sync signals are simply TTL level drivers feeding unshielded wires in the monitor cable. As such, no termination is required.
Serial Control Port
These are both 8-bit values, providing considerable flexibility in clamp generation. The clamp timing is referenced to the trailing edge of Hsync since the back porch (black reference) always follows Hsync. A good starting point for establishing clamping is to set the clamp placement to 08H (providing eight pixel periods for the graphics signal to stabilize after sync) and set the clamp duration to 14H (giving the clamp 20 pixel periods to re-establish the black reference). The value of the external input coupling capacitor affects the performance of the clamp. If the value is too small, there can be an amplitude change during a horizontal line time (between clamping intervals). If the capacitor is too large, then it will take excessively long for the clamp to recover from a large change in incoming signal offset. The recommended value (47 nF) results in recovery from a step error of 100 mV to within one-half LSB in 10 lines using a clamp duration of 20 pixel periods on a 75 Hz SXGA signal.
YUV Clamping
The serial control port is designed for 3.3 V logic. If there are 5 V drivers on the bus, these pins should be protected with 150 W series resistors placed between the pull-up resistors and the input pins.
Output Signal Handling
The digital outputs are designed and specified to operate from a 3.3 V power supply (VDD). They can also work with a VDD as low as 2.5 V for compatibility with other 2.5 V logic.
Clamping RGB Clamping
To properly digitize the incoming signal, the dc offset of the input must be adjusted to fit the range of the on-board A/D converters. Most graphics systems produce RGB signals with black at ground and white at approximately 0.75 V. However, if sync signals are embedded in the graphics, the sync tip is often at ground and black is at 300 mV; white will be approximately 1.0 V. Some common RGB line amplifier boxes use emitter-follower buffers to split signals and increase drive capability. This introduces a 700 mV dc offset to the signal, which is removed by clamping for proper capture by the AD9882. The key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. Originating from CRT displays, the electron beam is "blanked" by sending a black level during horizontal retrace to prevent disturbing the image. Most graphics systems maintain this format of sending a black level between active video lines. An offset is then introduced, which results in the A/D converters producing a black output (code 00H) when the known black input is present. The offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. In systems with embedded sync, a blacker-than-black signal (Hsync) is produced briefly to signal the CRT that it is time to begin a retrace. For obvious reasons, it is important to avoid clamping on the tip of Hsync. Fortunately, there is virtually always a period following Hsync called the back porch, in which a good black reference is provided. This is the time when clamping should be done. The clamp timing is established by the AD9882 internal clamp timing generator. The Clamp Placement Register (05H) is programmed with the number of pixel times that should pass after the trailing edge of Hsync before clamping starts. A second register (Clamp Duration, 06H) sets the duration of the clamp.
YUV signals are slightly different from RGB signals in that the dc reference level (black level in RGB signals) will be at the midpoint of the U and V video. For these signals, it can be necessary to clamp to the midscale range of the A/D converter range (80H) rather than the bottom of the A/D converter range (00H). Clamping to midscale rather than ground can be accomplished by setting the clamp select bits in the serial bus register. Each of the three converters has its own selection bit so that they can be clamped to either midscale or ground independently. These bits are located in Register 11H and are Bits 4-6. The midscale reference voltage that each A/D converter clamps to is provided on the MIDBYPASS pin (Pin 74). This pin should be bypassed to ground with a 0.1 mF capacitor (even if midscale clamping is not required).
Gain and Offset Control
The AD9882 can accommodate input signals with inputs ranging from 0.5 V to 1.0 V full scale. The full-scale range is set in three 8-bit registers (RED Gain, GREEN Gain, and BLUE Gain). A code of 0 establishes a minimum input range of 0.5 V; 255 corresponds with the maximum range of 1.0 V. Note that INCREASING the gain setting results in an image with LESS contrast. The offset control shifts the entire input range, resulting in a change in image brightness. Three 7-bit registers (RED Offset, GREEN Offset, BLUE Offset) provide independent settings for each channel. The offset controls provide a 63 LSB adjustment range. This range is connected with the full-scale range, so if the input range is doubled (from 0.5 V to 1.0 V), the offset step size is also doubled (from 2 mV per step to 4 mV per step). Figure 2 illustrates the interaction of gain and offset controls. The magnitude of an LSB in offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. The change is minimal if the offset setting is near midscale. When changing the offset, the full-scale range is not affected, but the full-scale level is shifted by the same amount as the zero-scale level.
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REV. A
AD9882
The stability of this clock is a very important element in providing the clearest and most stable image. During each pixel time, there is a period during which the signal is slewing from the old pixel amplitude and settling at its new value. Then there is a time when the input voltage is stable, before the signal must slew to a new value (Figure 4). The ratio of the slewing time to the stable time is a function of the bandwidth of the graphics DAC and the bandwidth of the transmission system (cable and termination). It is also a function of the overall pixel rate. Clearly, if the dynamic characteristics of the system remain fixed, then the slewing and settling time is likewise fixed. This time must be subtracted from the total pixel period, leaving the stable period. At higher pixel frequencies, the total cycle time is shorter, and the stable pixel time becomes shorter as well.
PIXEL CLOCK
OFFSET = 3FH 00H
OFFS ET = 00H
O FF SE T
T SE FF O = H 3F
1.0 V
INPUT RANGE
=
0.5 V
= ET FS OF
H T = 7F OFFSE
7F H
H 00
INVALID SAMPLE TIMES
0.0 V
FFH
GAIN
Figure 2. Gain and Offset Control
Sync-on-Green (SOG)
The Sync-on-Green input operates in two steps. First, it sets a baseline clamp level off of the incoming video signal with a negative peak detector. Second, it sets the Sync trigger level (nominally 150 mV above the negative peak). The exact trigger level is variable and can be programmed via Register 0FH, Bits 7-3. The Sync-on-Green input must be ac-coupled to the green analog input through its own capacitor as shown in Figure 3. The value of the capacitor must be 1 nF 20%. If Sync-on-Green is not used, this connection is not required and SOGIN should be left unconnected. (Note: The Sync-on-Green signal is always negative polarity.) Please refer to the Sync Processing section for further information.
RAIN 47nF BAIN GAIN 47nF SOGIN 1nF 47nF
Figure 4. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the sampling time can be determined and must also be subtracted from the stable pixel time. Considerable care has been taken in the design of the AD9882's clock generation circuit to minimize jitter. As indicated in Figure 5, the clock jitter of the AD9882 is less than 6% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible.
10
PIXEL CLOCK JITTER (p-p) - %
8
6
Figure 3. Typical Clamp Configuration
Clock Generation
4
A Phase Locked Loop (PLL) is employed to generate the pixel clock. The Hsync input provides a reference frequency for the PLL. A Voltage Controlled Oscillator (VCO) generates a much higher pixel clock frequency. This pixel clock is divided by the PLL divide value (Registers 01H and 02H) and phase compared with the Hsync input. Any error is used to shift the VCO frequency and maintain lock between the two signals.
2
0 25.1 31.5 36.0 40.0 50.0 56.2 65.0 75.0 78.7 85.5 94.5 108.0 135.0 PIXEL CLOCK FREQUENCY - MHz
Figure 5. Pixel Clock Jitter vs. Frequency
REV. A
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AD9882
The PLL characteristics are determined by the loop filter design, the PLL charge pump current, and the VCO range setting. The loop filter design is illustrated in Figure 6. Recommended settings of VCO range and charge pump current for VESA standard display modes are listed in Table VII.
CP 0.0082 F CZ 0.082 F RZ 2.74k FILT PVD
Table V. VCO Frequency Ranges
PV1 0 0 1
PV0 0 1 0
Pixel Clock Range (MHz) 12-41 41-82 82-140
3. The 3-bit Charge Pump Current Register (Register 03H, Bits 3-5). This register allows the current that drives the low-pass loop filter to be varied. The possible current values are listed in Table VI.
Table VI. Charge Pump Current/Control Bits
Figure 6. PLL Loop Filter Detail
Four programmable registers are provided to optimize the performance of the PLL. These registers are: 1. The 12-bit Divisor Register (Registers 01H and 02H). The input Hsync frequencies range from 15 kHz to 110 kHz. The PLL multiplies the frequency of the Hsync signal, producing pixel clock frequencies in the range of 12 MHz to 140 MHz. The Divisor Register controls the exact multiplication factor. This register may be set to any value between 221 and 4095. (The divide ratio that is actually used is the programmed divide ratio plus one.) 2. The 2-bit VCO Range Register (Register 03H, Bits 6 and 7). To improve the noise performance of the AD9882, the VCO operating frequency range is divided into three overlapping regions. The VCO Range register sets this operating range. The frequency ranges for the lowest and highest regions are shown in Table V.
Ip2 0 0 0 0 1 1 1 1
Ip1 0 0 1 1 0 0 1 1
Ip0 0 1 0 1 0 1 0 1
Current (mA) 50 100 150 250 350 500 750 1500
4. The 5-bit Phase Adjust Register (Register 04H, Bits 3-7). The phase of the generated sampling clock may be shifted to locate an optimum sampling point within a clock cycle. The Phase Adjust Register provides 32 phase-shift steps of 11.25 each. The Hsync signal with an identical phase shift is available through the HSOUT pin.
Table VII. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Standard VGA
Refresh Resolution 640 480
Horizontal Rate (Hz) 60 72 75 85 56 60 72 75 85 60 70 75 80 85 60 75
Frequency (kHz) 31.5 37.7 37.5 43.3 35.1 37.9 48.1 46.9 53.7 48.4 56.5 60.0 64.0 68.3 64.0 80.0
Pixel Rate (MHz) 25.175 31.500 31.500 36.000 36.000 40.000 50.000 49.500 56.250 65.000 75.000 78.750 85.500 94.500 108.000 135.000
VCORNGE 00 00 00 00 00 00 01 01 01 01 01 01 10 10 10 11
CURRENT 101 101 101 110 101 110 101 101 101 101 110 110 101 101 101 110
SVGA
800 600
XGA
1024 768
SXGA
1280 1024
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REV. A
AD9882
The COAST function allows the PLL to continue to run at the same frequency, in the absence of the incoming Hsync signal or during disturbances in Hsync (such as equalization pulses). This may be used during the vertical sync period, or any other time that the Hsync signal is unavailable. Also, the polarity of the Hsync signal may be set through the Hsync Polarity Bit (Register 10H, Bit 6). If not using automatic polarity detection, the Hsync polarity bit should be set to match the polarity of the Hsync input signal.
TIMING (ANALOG INTERFACE)
Register (Register 04H) to optimize the pixel sampling time. Display systems use Hsync to align memory and display write cycles, so it is important to have a stable timing relationship between Hsync output (HSOUT) and data clock (DATACK). Three things happen to Horizontal Sync in the AD9882. First, the polarity of Hsync input is determined and will thus have a known output polarity. The known output polarity can be programmed either active high or active low (Register 10H, Bit 5). Second, HSOUT is aligned with DATACK and data outputs. Third, the duration of HSOUT (in pixel clocks) is set via Register 07H. HSOUT is the sync signal that should be used to drive the rest of the display system.
Coast Timing
The following timing diagrams show the operation of the AD9882. The Output Data Clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally.
tPER tDCYCLE
DATACK
In most computer systems, the Hsync signal is provided continuously on a dedicated wire. In these systems, the COAST function is unnecessary and should be disabled using Register 11H, Bits 1-3. In some systems, however, Hsync is disturbed during the Vertical Sync period (Vsync). In other cases, Hsync pulses disappear. In other systems, such as those that employ Composite Sync (Csync) signals or embedded Sync-on-Green (SOG), Hsync includes equalization pulses or other distortions during Vsync. To avoid upsetting the clock generator during Vsync, it is important to ignore these distortions. If the pixel clock PLL sees extraneous pulses, it will attempt to lock to this new frequency and will have changed frequency by the end of the Vsync period. It will then take a few lines of correct Hsync timing to recover at the beginning of a new frame, resulting in a "tearing" of the image at the top of the display. The COAST function is provided to eliminate this problem. It is an internally generated signal, created by the sync processing engine that disables the PLL input and allows the clock to free-run at its then-current frequency. The PLL can free-run for several lines without significant frequency drift.
tSKEW
DATA HSOUT
Figure 7. Output Timing
Hsync Timing
Horizontal Sync (Hsync) is processed in the AD9882 to eliminate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data. The Hsync input is used as a reference to generate the pixel sampling clock. The sampling phase can be adjusted, with respect to Hsync, through a full 360 in 32 steps via the Phase Adjust
REV. A
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AD9882
TIMING DIAGRAMS
RGBIN P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS 5 PIPE DELAY ADCCK
DATACK
DATAOUT
D0
D1
D2
D3
D4
D5
D6
D7
HSOUT
VARIABLE DURATION
Figure 8. 4:4:4 Mode (for RGB and YPbPr)
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PXCK HS 5 PIPE DELAY ADCCK
DATACK
GOUTA ROUTA
Y0 Pb0
Y1 Pr0
Y2 Pb2
Y3 Pr2
Y4 Pb4
Y5 Pr4
Y6 Pb6
Y7 Pr6
HSOUT
VARIABLE DURATION
Figure 9. 4:2:2 Mode (for YPbPr Only)
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REV. A
AD9882
Table VIII. Digital Interface Pin List
Pin Type Digital Video Data Inputs
Mnemonic RX0+ RX0- RX1+ RX1- RX2+ RX2- RXC+ RXC- RTERM DE HSOUT VSOUT CTL0, CTL1, CTL2, CTL3 DDCSCL DDCSDA MCL MDA VD PVD VDD GND
Function Digital Input Channel 0 True Digital Input Channel 0 Complement Digital Input Channel 1 True Digital Input Channel 1 Complement Digital Input Channel 2 True Digital Input Channel 2 Complement Digital Data Clock True Digital Data Clock Complement Control Pin for Setting the Internal Termination Resistance Data Enable Hsync Output Vsync Output Decoded Control Bit Outputs HDCP Slave Serial Port Data Clock HDCP Slave Serial Port Data I/O HDCP Master Serial Port Data Clock HDCP Master Serial Port Data I/O Main Power Supply PLL Power Supply Output Power Supply Ground Supply
Value
Pin Number 33 32 36 35 39 38 41 42 28
Digital Video Clock Inputs Termination Control Outputs
3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.15 V to 3.45 V 3.15 V to 3.45 V 2.2 V to 3.6 V 0V
86 88 87 22-25 53 54 81 82
HDCP
Power Supply
DIGITAL INTERFACE PIN DESCRIPTIONS DIGITAL DATA INPUTS
OUTPUTS DE
Data Enable Output
RX0+ RX0- RX1+ RX1- RX2+ RX2-
Positive Differential Input Data (Channel 0) Negative Differential Input Data (Channel 0) Positive Differential Input Data (Channel 1) Negative Differential Input Data (Channel 1) Positive Differential Input Data (Channel 2) Negative Differential Input Data (Channel 2)
This pin outputs the state of data enable (DE). The AD9882 decodes DE from the incoming stream of data. The DE signal will be HIGH during active video and will be LOW while there is no active video.
DDCSCL HDCP Slave Serial Port Data Clock
These six pins receive three pairs of differential, low voltage swing input pixel data from a DVI transmitter.
For use in communicating with the HDCP enabled DVI transmitter.
DDCSDA HDCP Slave Serial Port I/O
DIGITAL CLOCK INPUTS
RXC+ RXC-
Positive Differential Input Clock Negative Differential Input Clock
MCL
For use in communicating with the HDCP enabled DVI transmitter.
HDCP Master Serial Port Data Clock
These two pins receive the differential, low voltage swing input pixel clock from a DVI transmitter.
TERMINATION CONTROL RTERM Internal Termination Set Pin
Connects to the EEPROM for reading the encrypted HDCP keys.
MDA HDCP Master Serial Port Data I/O
This pin is used to set the termination resistance for all of the digital interface high speed inputs. To set, place a resistor of value equal to 10 the desired input termination resistance between this pin (Pin 28) and ground supply. Typically, the value of this resistor should be 500 W.
Connects to the EEPROM for reading the encrypted HDCP keys.
CTL Digital Control Outputs
These pins output the control signals for the Red and Green channels. CTL0 and CTL1 correspond to the Red channel's input, while CTL2 and CTL3 correspond to the Green channel's input.
REV. A
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AD9882
POWER SUPPLY VD Main Power Supply Data Decoder
It should be as quiet as possible.
PVD VDD PLL Power Supply
It should be as quiet as possible.
Outputs Power Supply
The data decoder receives frames of data and sync signals from the data capture block (in 10-bit parallel words) and decodes them into groups of eight RGB bits, two control bits, and a data enable bit (DE).
HDCP
The power for the data and clock outputs. It can run at 3.3 V or 2.5 V.
GND Ground
The ground return for all circuitry on the device. It is recommended that the application circuit board have a single, solid ground plane.
THEORY OF OPERATION (DIGITAL INTERFACE) Capturing of the Encoded Data
The AD9882 contains all the circuitry necessary for decryption of a high bandwidth digital content protection encoded DVI video stream. A typical HDCP implementation is shown in Figure 10. Several features of the AD9882 make this possible and add functionality to ease the implementation of HDCP. The basic components of HDCP are included in the AD9882. A slave serial bus connects to the DDC clock and DDC data pins on the DVI connector to allow the HDCP enabled DVI transmitter to coordinate the HDCP algorithm with the AD9882. A second serial port (MDA/MCL) allows the AD9882 to read the HDCP keys and key selection vector (KSV) stored in an external serial EEPROM. When transmitting encrypted video, the DVI transmitter enables HDCP through the DDC port. The AD9882 then decodes the DVI stream using information provided by the transmitter, HDCP keys, and KSV. The AD9882 allows the MDA and MCL pins to be three-stated using the MDA/MCL three-state bit (Register 1B, Bit 7) in the configuration registers. The three-state feature allows the EEPROM to be programmed in-circuit. The MDA/MCL port must be three-stated before attempting to program the EEPROM using an external master. The keys will be stored in an I2C compatible 3.3 V serial EEPROM of at least 512 bytes in size. The EEPROM should have a device address of A0H. Proprietary software licensed from Analog Devices encrypts the keys and creates properly formatted EEPROM images for use in a production environment. Encrypting the keys helps maintain the confidentiality of the HDCP keys as required by the HDCP v1.0 specification. The AD9882 includes hardware for decrypting the keys in the external EEPROM. ADI will provide a royalty free license for the proprietary software needed by customers to encrypt the keys between the AD9882 and the EEPROM only after customers provide evidence of a completed HDCP Adopter's license agreement and sign ADI's software license agreement. The Adopter's license agreement is maintained by Digital Content Protection, LLC, and can be downloaded from www.digital-cp.com. To obtain ADI's software license agreement, contact the Display Electronics Product Line directly by sending an email to flatpanel_apps@analog.com.
The first step in recovering the encoded data is to capture the raw data. To accomplish this, the AD9882 employs a high speed phase locked loop (PLL) to generate clocks capable of oversampling the data at the correct frequency. The data capture circuitry continuously monitors the incoming data during horizontal and vertical blanking times (when DE is low) and selects the best sampling phase for each data channel independently. The phase information is stored and used until the next blanking period (one video line).
Data Frames
The digital interface data is captured in groups of 10 bits each, which are called data frames. During the active data period, each frame is made up of the nine encoded video data bits and one dc balancing bit. The data capture block receives this data serially but outputs each frame in parallel 10-bit words.
Special Characters
During periods of horizontal or vertical blanking time (when DE is low), the digital transmitter will transmit special characters. The AD9882 will receive these characters and use them to set the video frame boundaries and the phase recovery loop for each channel. There are four special characters that can be received. They are used to identify the top, bottom, left side, and right side of each video frame. The data receiver can differentiate these special characters from active data because the special characters have a different number of transitions per data frame.
Channel Resynchronization
The purpose of the channel resynchronization block is to resynchronize the three data channels to a single internal data clock. Coming into this block, all three data channels can be on different phases of the 3 oversampling PLL clock (0, 120, and 240). This block can resynchronize the channels from a worst-case skew of one full input period (8.93 ns at 112 MHz).
3.3V DVI CONNECTOR DDC CLOCK DDC DATA 5k PULL-UP RESISTORS DDC SCL MCL MDA
3.3V 5k PULL-UP RESISTORS SCL EEPROM SDA
AD9882
D S 3.3V 150 SERIES RESISTORS DDC SDA
Figure 10. HDCP Implementation Using the AD9882
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REV. A
AD9882
GENERAL TIMING DIAGRAMS (DIGITAL INTERFACE)
80% 80%
TCIP , R CIP TCIH , R CIH
20% DLHT DHLT
20%
TCIL , R CIL
Figure 11. Digital Output Rise and Fall Times
Figure 12. Clock Cycle/High/Low Times
RX0 VDIFF = 0V RX1 TCSS RX2 VDIFF = 0V
Figure 13. Channel-to-Channel Skew Timing
TIMING MODE DIAGRAMS (DIGITAL INTERFACE)
INTERNAL ODCLK TST
DATACK
DE
FIRST PIXEL DATAOUT
SECOND PIXEL
THIRD PIXEL
FOURTH PIXEL
Figure 14. DVI CLK Invert = 1 (Register 14, Bit 4)
INTERNAL ODCLK TST DATACK
DE FIRST PIXEL DATAOUT SECOND PIXEL THIRD PIXEL FOURTH PIXEL
Figure 15. DVI CLK Invert = 0 (Register 14, Bit 4)
REV. A
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AD9882
2-WIRE SERIAL REGISTER MAP
The AD9882 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the Control Registers through the 2-wire serial interface port.
Table IX. Control Register Map
Hex Address 00 01
Read and Write or Read Only RO R/W
Bit 7-0 7-0
Default Value
Register Name Chip Revisions
Function An 8-bit register that represents the silicon level. Revision 0 = 0000 0000 This register is for Bits [11:4] of the PLL divider. Larger values mean the PLL operates at a faster rate. This register should be loaded first whenever a change is needed. (This will give the PLL more time to lock.)1 Bits [3:0] LSBs of the PLL divider word. Links to PLL MSB to make a 12-bit register.1 Selects VCO frequency range. Varies the current that drives the PLL loop filter. ADC clock phase adjustment. Larger values mean more delay (1 LSB = T/32). Places the clamp signal an integer number of clock periods after the trailing edge of Hsync. Number of clock periods that the clamp signal is actively clamping. Sets the number of pixel clocks that HSOUT will remain active. Controls the ADC input range (contrast) of the red channel. Larger values give less contrast. Controls the ADC input range (contrast) of the green channel. Larger values give less contrast. Controls the ADC input range (contrast) of the blue channel. Larger values give less contrast. Controls the dc offset (brightness) of the red channel. Larger values decrease brightness. Controls the dc offset (brightness) of the green channel. Larger values decrease brightness. Controls the dc offset (brightness) of the blue channel. Larger values decrease brightness. Sets how many pixel clocks to count before toggling high or low. This should be set to some number greater than the maximum Hsync or equalization pulsewidth. Sets the voltage level of the Sync-on-Green slicer's comparator. 0 = No override 1 = User overrides, interface set by 0FH, Bit 1 0 = Analog interface active 1 = Digital interface active This interface is selected only if Register 0FH, Bit 2 is set to 1, or if both interfaces are active.
0110 1001
PLL Div MSB
02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
7-4 7-6 5-3 7-3 7-0 7-0 7-0 7-0 7-0 7-0 7-1 7-1 7-1 7-0
1101 **** 01** **** **00 1*** 1000 0*** 0000 1000 0001 0100 0010 0000 1000 0000 1000 0000 1000 0000 1000 000* 1000 000* 1000 000* 0010 0000
PLL Div LSB VCO Range Charge Pump Phase Adjust Clamp Placement Clamp Duration Hsync Output Pulsewidth Red Gain Green Gain Blue Gain Red Offset Green Offset Blue Offset Sync Separator Threshold
0F
R/W
7-3 2 1
0111 1*** **** *0** **** **0*
Sync-On-Green Threshold Active Interface Override Active Interface Select
NOTE 1 The AD9882 only updates the PLL divide ratio when the LSBs are written to Register 02H.
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REV. A
AD9882
Table IX. Control Register Map (continued)
Hex Address 10
Read and Write or Read Only R/W
Bit 7 6 5 4 3
Default Value 0*** **** *1** **** **0* **** ***0 **** **** 0***
Register Name Hsync Polarity Override Input Hsync Polarity Output Hsync Polarity Active Hsync Override Active Hsync Select
Function 0 = Polarity determined by chip 1 = Polarity set by 10H, Bit 6 0 = Active low polarity 1 = Active high polarity 0 = Active high sync signal 1 = Active low sync signal 0 = No override 1 = User overrides, analog Hsync set by 10H, Bit 3 0 = Analog Hsync from the Hsync input pin 1 = Analog Hsync from SOG This bit is used if Register 10H, Bit 4 is set to 1 or if both syncs are active. 0 = Invert 1 = Not inverted 0 = No override 1 = User overrides, analog Vsync set by 10H, Bit 0 0 = Analog Vsync from the Vsync input pin 1 = Analog Vsync from sync separator 0 = Clamping with internal clamp 1 = Clamping disabled 0 = Clamp to ground 1 = Clamp to midscale for red channel 0 = Clamp to ground 1 = Clamp to midscale for green channel 0 = Clamp to ground 1 = Clamp to midscale for blue channel 0 = Disabled coast 1 = Coasting with internally generated coast signal 0 = Coast polarity determined by the chip 1 = Coast polarity set by 11H, Bit 1 This bit must be set to 1 to disable coast. 0 = Active low coast signal 1 = Active high coast signal This bit must be set to 1 to disable coast. Number of Hsync periods that coast goes active prior to Vsync. Number of Hsync periods before coast goes inactive following Vsync. Selects among high, medium, and low output drive strength. 0 = Low bandwidth of 10 MHz 1 = High bandwidth of 300 MHz 0 = DVI data clock output not inverted 1 = DVI data clock output inverted For digital interface only. 0 = Normal outputs 1 = High impedance outputs Address Bit 0 = 0 for HDCP Slave Port Address Bit 1 = 1 for HDCP Slave Port 0 = Full chip power-down
2 1 0 11 R/W 7 6 5 4 3 2
**** *0** **** **0* **** ***0 0*** **** *0** **** **0* **** ***0 **** **** 1*** **** *0**
Output Vsync Polarity Active Vsync Override Active Vsync Select Clamp Function Red Clamp Select Green Clamp Select Blue Clamp Select Coast Select Coast Polarity Override
1
**** **1*
Input Coast Polarity
12 13 14
R/W R/W R/W
7-0 7-0 7-6 5 4
0000 0000 0000 0000 11** **** **1* **** ***0 ****
Pre-Coast Post-Coast Output Drive Select Programmable Bandwidth DVI Clock Invert
3 2 1
**** 0*** **** *0** **** **1*
DVI PDO Three-State HDCP Address Power-Down
REV. A
-23-
AD9882
Table IX. Control Register Map (continued)
Hex Address 14 15
Read and Write or Read Only R/W RO
Bit 0 7 6 5 4 3
Default Value **** ***0
Register Name Enable 4:2:2 Analog Hsync Active Analog SOG Active Analog Vsync Active DVI Active Active Interface Active Hsync Hsync Polarity Detected Active Vsync Vsync Polarity Detected Coast Polarity Detected
Function 0 = 4:4:4 mode 1 = 4:2:2 mode 0 = Hsync not detected 1 = Hsync detected 0 = Sync signal not detected on green channel 1 = Sync signal detected on green channel 0 = Vsync not detected 1 = Vsync detected 0 = Digital interface clock not detected 1 = Digital interface clock detected 0 = Analog interface active 1 = DVI interface active 0 = Hsync from the Hsync input pin 1 = Hsync from the SOG input 0 = Active low polarity detected 1 = Active high polarity detected 0 = Vsync from the Vsync input pin 1 = Vsync from SOG 0 = Active high polarity detected 1 = Active low polarity detected 0 = Active low polarity detected 1 = Active high polarity detected This function works only with internal coast. 0 = Not detected 1 = Detected Must be set to 1000 0000 for proper operation. Must be set to 1100 000x for proper operation. Must be set to 0111 110x for proper operation. Must be set to default for proper operation. 0 = MDA and MCL three-stated 1 = MDA and MCL not three-stated Must be set to *110 0111 for proper operation. Must be set to default for proper operation. Reserved for future use. Reserved for future use.
16
RO
7 6 5 4 3
2 17 18 19 1A 1B R/W R/W R/W R/W R/W 7-0 7-0 7-0 7-0 7 6-0 1C 1D 1E R/W RO RO 7-0 7-0 7-0 0000 0000 0000 000X 0000 010X 0011 1111 1*** **** *111 0000 0000 1111
HDCP Keys Detected Test Register Test Register Test Register Test Register MDA and MCL Test Register Test Register Test Register Test Register
-24-
REV. A
AD9882
2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 00 7-0 Chip Revision Table X. VCO Ranges
VCORNGE 00 01 10
Pixel Rate Range 12-41 41-82 82-140
An 8-bit register that represents the silicon revision. Revision 0 = 0000 0000.
PLL DIVIDER CONTROL 01 7-0 PLL Divide Ratio MSBs
The power-up default value is VCORNGE = 01.
The eight most significant bits of the 12-bit PLL divide ratio PLLDIV. (The operational divide ratio is PLLDIV + 1.) The PLL derives a pixel clock from the incoming Hsync signal. The pixel clock frequency is then divided by an integer value, such that the output is phase-locked to Hsync. This PLLDIV value determines the number of pixel times (pixels plus horizontal blanking overhead) per line. This is typically 20% to 30% more than the number of active pixels in the display. The 12-bit value of the PLL divider supports divide ratios from 221 to 4095. The higher the value loaded in this register, the higher the resulting clock frequency with respect to a fixed Hsync frequency. VESA has established some standard timing specifications that will assist in determining the value for PLLDIV as a function of the horizontal and vertical display resolution and frame rate (Table VII). However, many computer systems do not conform precisely to the recommendations, and these numbers should be used only as a guide. The display system manufacturer should provide automatic or manual means for optimizing PLLDIV. An incorrectly set PLLDIV will usually produce one or more vertical noise bars on the display. The greater the error, the greater the number of bars produced. The power-up default value of PLLDIV is 1693 (PLLDIVM = 69H, PLLDIVL = DxH). The AD9882 updates the full divide ratio only when the LSBs are changed. Writing to this register by itself will not trigger an update.
02 7-4 PLL Divide Ratio LSBs
03
5-3
CURRENT
Charge Pump Current
Three bits that establish the current driving the loop filter in the clock generator.
Table XI. Charge Pump Currents
Charge Pump 000 001 010 011 100 101 110 111
Current (mA) 50 100 150 250 350 500 750 1500
CHARGE PUMP must be set to correspond with the desired operating frequency (incoming pixel rate). See Table XI for the charge pump current for each register setting. The power-up default value is CURRENT = 001.
04 7-3 Phase Adjust
A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25 shift in sampling phase. The power-up default Phase adjust value is 10H.
CLAMP TIMING 05 7-0 Clamp Placement
The four least significant bits of the 12-bit PLL divide ratio PLLDIV. The operational divide ratio is PLLDIV + 1. The power-up default value of PLLDIV is 1693 (PLLDIVM = 69H, PLLDIVL = DxH). The AD9882 updates the full divide ratio only when this register is written.
03 7-6 VCO Range Select
An 8-bit register that sets the position of the internally generated clamp. When CLAMP FUNCTION (Register 11H, Bit 7) = 0, a clamp signal is generated internally at a position established by the clamp placement and for a duration set by the clamp duration. Clamping is started (Clamp Placement) an integral number of pixel periods after the trailing edge of Hsync. The clamp placement may be programmed to any value between 1 and 255. The clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between Hsync and the image. When CLAMP FUNCTION = 1, this register is ignored.
06 7-0 Clamp Duration
Two bits that establish the operating range of the clock generator. VCORNGE must be set to correspond with the desired operating frequency (incoming pixel rate). The PLL VCO gives the best jitter performance while operating at high frequencies. For this reason, in order to output low pixel rates and still get good jitter performance, the PLL VCO actually operates at a higher frequency but then divides down the clock rate afterward. Table X shows the pixel rates for each VCO range setting. The PLL output divisor is automatically selected with the VCO range setting.
An 8-bit register that sets the duration of the internally generated clamp. For the best results, the clamp duration should be set to include the majority of the black reference signal time that follows the Hsync signal trailing edge. Insufficient clamping time can produce brightness changes at the top of the screen and a slow recovery from large changes in the Average Picture Level (APL) or brightness. When CLAMP FUNCTION = 1, this register is ignored.
REV. A
-25-
AD9882
HSYNC OUTPUT PULSEWIDTH 07 7-0 Hsync Output Pulsewidth 0F 7-3 Sync-on-Green Slicer Threshold
An 8-bit register that sets the duration of the Hsync output pulse. The leading edge of the Hsync output is triggered by the internally generated, phase adjusted PLL feedback clock. The AD9882 then counts a number of pixel clocks equal to the value in this register minus one. This triggers the trailing edge of the Hsync output, which is also phase adjusted.
INPUT GAIN 08 7-0 REDGAIN
This register allows the comparator threshold of the Sync-on-Green slicer to be adjusted. This register adjusts it in steps of 10 mV, with the minimum setting equaling 10 mV and the maximum setting equaling 330 mV. The default setting is 15 decimal and corresponds to a threshold value of 170 mV.
0F 2 AIO Active Interface Override
RED Gain
An 8-bit word that sets the gain of the RED channel. The AD9882 can accommodate input signals with a full-scale range of between 0.5 V and 1.0 V p-p. Setting REDGAIN to 255 corresponds to an input range of 1.0 V. A REDGAIN of 0 establishes an input range of 0.5 V. Note that INCREASING REDGAIN results in the picture having LESS CONTRAST (the input signal uses fewer of the available converter codes). See Figure 2.
09 7-0 GREENGAIN GREEN Gain
This bit is used to override the automatic interface selection (Bit 3 in Register 15H). To override, set this bit to logic 1. When overriding, the active interface is set via Bit 1 in this register.
Table XII. Active Interface Override Settings
AIO 0 1
Result Autodetermine the active interface. Override, Bit 1 determines the active interface.
The default for this register is 0.
An 8-bit word that sets the gain of the GREEN channel. See REDGAIN (08).
0A 7-0 BLUEGAIN BLUE Gain
0F
1
AIS
Active Interface Select
An 8-bit word that sets the gain of the BLUE channel. See REDGAIN (08).
INPUT OFFSET 0B 7-1 RED Channel Offset Adjust
This bit is used under two conditions. It is used to select the active interface when the override bit is set (Register 0FH, Bit 2). Alternatively, it is used to determine the active interface when not overriding but both interfaces are detected.
Table XIII. Active Interface Select Settings
A 7-bit offset binary word that sets the dc offset of the RED channel. One LSB of offset adjustment equals approximately one LSB change in the ADC offset. Therefore, the absolute magnitude of the offset adjustment scales as the gain of the channel is changed. A nominal setting of 64 results in the channel nominally clamping the back porch (during the clamping interval) to code 00. An offset setting of 127 results in the channel clamping to code 63 of the ADC. An offset setting of 0 clamps to code -64 (off the bottom of the range). Increasing the value of RED offset DECREASES the brightness of the channel.
0C 7-1 GREEN Channel Offset Adjust
AIS 0 1
Result Analog interface Digital interface
The default for this register is 0.
10
7
Hsync Input Polarity Override
This register is used to override the internal circuitry that determines the polarity of the Hsync signal going into the PLL.
Table XIV. Hsync Input Polarity Override Settings
A 7-bit offset binary word that sets the dc offset of the GREEN channel. See REDOFST (0B).
0D 7-1 BLUE Channel Offset Adjust
Override Bit 0 1
Result Hsync polarity determined by chip. Hsync polarity determined by Register 10H, Bit 6.
A 7-bit offset binary word that sets the dc offset of the BLUE channel. See REDOFST (0B).
0E 7-0 Sync Separator Threshold
The default for Hsync polarity override is 0. (Polarity determined by chip.)
This register is used to set the responsiveness of the sync separator. It sets how many internal 5 MHz clock periods the sync separator must count to before toggling high or low. It works like a low-pass filter to ignore Hsync pulses in order to extract the Vsync signal. This register should be set to some number greater than the maximum Hsync pulsewidth. Note: the sync separator threshold uses an internal dedicated clock with a frequency of approximately 5 MHz. The default for this register is 20H.
10
6
HSPOL
Hsync Input Polarity
A bit that must be set to indicate the polarity of the Hsync signal that is applied to the PLL Hsync input.
Table XV. Hsync Input Polarity Settings
HSPOL 0 1
Function Active LOW Active HIGH
Active LOW means the leading edge of the Hsync pulse is negativegoing. All timing is based on the leading edge of Hsync, which is the FALLING edge. The rising edge has no effect.
-26-
REV. A
AD9882
Active HIGH means the leading edge of the Hsync pulse is positive-going. This means that timing will be based on the leading edge of Hsync, which is now the RISING edge. The device will operate if this bit is set incorrectly, but the internally generated clamp position, as established by Clamp Placement (Register 05H), will not be placed as expected, which may generate clamping errors. The power-up default value is HSPOL = 1.
10 5 Hsync Output Polarity 10 1 Active Vsync Override
This bit is used to override the automatic Vsync selection. To override, set this bit to logic 1. When overriding, the active interface is set via Bit 0 in this register.
Table XX. Active Vsync Override Settings
Override 0 1
Result Autodetermine the active Vsync Override. Bit 0 determines the active Vsync.
One bit that determines the polarity of the Hsync output and the SOG output. Table XVI shows the effect of this option. SYNC indicates the logic state of the sync pulse.
Table XVI. Hsync Output Polarity Settings
The default for this register is 0.
10
0
Active Vsync Select
This bit is used to select the active Vsync when the override bit is set (Bit 1).
Table XXI. Active Vsync Select Settings
Setting 0 1
SYNC Logic 1 (positive polarity) Logic 0 (negative polarity) Select 0 1
Result Vsync input Sync separator output
The default setting for this register is 0.
10
4
Active Hsync Override
This bit is used to override the automatic Hsync selection. To override, set this bit to logic 1. When overriding, the active Hsync is set via Bit 3 in this register.
Table XVII. Active Hsync Override Settings
The default for this register is 0.
11
7
Clamp Function
A bit that enables/disables clamping.
Table XXII. Clamp Input Signal Source Settings
Override 0 1
Result Autodetermine the active Hsync. Override. Bit 3 determines the active Hsync.
Clamp Function 0 1
Function Internally generated clamp enabled Clamping disabled
The default for this register is 0.
10
3
Active Hsync Select
This bit is used under two conditions. It is used to select the active Hsync when the override bit is set (Bit 4). Alternately, it is used to determine the active Hsync when not overriding, but both Hsyncs are detected.
Table XVIII. Active Hsync Select Settings
A 0 enables the clamp timing circuitry controlled by clamp placement and clamp duration. The clamp position and duration is counted from the trailing edge of Hsync. A 1 disables clamping. The three channels are clamped when the CLAMP signal is active. Power-up default value is CLAMP FUNCTION = 0.
11 6 RED Clamp Select
Select 0 1
Result Hsync input Sync-on-Green input
The default for this register is 0.
A bit that determines whether the RED channel is clamped to ground or to midscale. For RGB video, all three channels are referenced to ground. For YPbPr, the Y channel is referenced to ground, but the PbPr channels are referenced to midscale. Clamping to midscale actually clamps to Pin 74.
Table XXIII. RED Clamp Select Settings
10
2
Vsync Output Polarity
One bit that determines the polarity of the Vsync output. Table XIX shows the effect of this option. SYNC indicates the logic state of the sync pulse.
Table XIX. Vsync Output Polarity Settings
Clamp 0 1
Function Clamp to ground Clamp to midscale (Pin 74)
The default setting for this register is 0.
Setting 1 0
SYNC Not invert Invert
The default setting for this register is 0.
REV. A
-27-
AD9882
11 5 GREEN Clamp Select 12 7-0 Pre-Coast
A bit that determines whether the GREEN channel is clamped to ground or to midscale.
Table XXIV. GREEN Clamp Select Settings
This register allows the coast signal to be applied prior to the Vsync signal. This is necessary in cases where pre-equalization pulses are present. This register defines the number of edges that will be filtered before Vsync on a composite sync. The default is 0.
13 7-0 Post-Coast
Clamp 0 1
Function Clamp to ground Clamp to midscale (Pin 74)
The default setting for this register is 0.
11
4
BLUE Clamp Select
A bit that determines whether the BLUE channel is clamped to ground or to midscale.
Table XXV. BLUE Clamp Select Settings
This register allows the coast signal to be applied following the Vsync signal. This is necessary in cases where post-equalization pulses are present. The step size for this control is one Hsync period. This register defines the number of edges that will be filtered after Vsync on a composite sync. The default is 0.
14 7-6 Output Drive
Clamp 0 1
Function Clamp to ground Clamp to midscale (Pin 74)
The default setting for this register is 0.
The two bits select the drive strength for the high speed digital outputs (all data output and clock output pins). Higher drive strength results in faster rise/fall times, and in general makes it easier to capture data. Lower drive strength results in slower rise/fall times and helps reduce EMI and digitally generated power supply noise.
Table XXIX. Output Drive Strength Settings
11
3
Coast Select
This bit is used to enable or disable the coast signal. If coast is enabled, the additional decision of using the Vsync input pin or the output from the sync separator needs to be made (Register 10H, Bits 1, 0). To disable coast, the user must set Register 11H, Bit 2 to 1 and 11H, Bit 1 to 1.
Table XXVI. Coast Enable Settings
Bit 7 1 0 0
Bit 6 X 1 0
Result High drive strength Medium drive strength Low drive strength
Select 0 1
Result Coast disabled Internally generated coast signal
The default for this register is 11, high drive strength. (This option works on both the analog and digital interfaces.)
14
5
Programmable Analog Bandwidth
Bits that select the analog bandwidth.
Table XXX. Analog Bandwidth Control
The default for this register is 1.
11
2
Coast Input Polarity Override
This register is used to override the internal circuitry that determines the polarity of the coast signal going into the PLL. When disabling coast, Register 11, Bit 2 must be set to 1 and Register 11H, Bit 1 must be set to 1. This register only works when Coast is disabled. It does not work with internal Coast.
Table XXVII. Coast Input Polarity Override Settings
Bit 5 0 1
14 4
Analog Bandwidth 10 MHz 300 MHz
Clk Inv Data Output Clock Invert
Override Bit 0 1
Result Coast polarity determined by chip Coast polarity determined by user
A control bit for the inversion of the output data clock (Pin 85). This function works only for the digital interface. When not inverted, data is output on the falling edge of the data clock. See the timing diagrams, Figures 14 and 15, to see how this affects timing.
Table XXXI. Clock Output Invert Settings
The default for coast polarity override is 0.
11
1
Coast Input Polarity
Clk Inv 0 1
Function Not inverted Inverted
A bit to indicate the polarity of the coast signal that is applied to the PLL coast input. This register can only be used when coast is disabled and Register 11H, Bit 2 is set to 1.
Table XXVIII. Coast Input Polarity Settings
The default for this register is 0 (not inverted).
CSTPOL 0 1
Function Active LOW Active HIGH -28- REV. A
The power-up default value is CSTPOL = 1.
AD9882
14 3 PDO Power-Down Outputs 15 7 Hsync Detect
A bit that can put the outputs in a high impedance mode. This applies to the 24 data output pins, HSOUT, VSOUT, and DE Pins.
Table XXXII. Power-Down Output Settings
This bit is used to indicate when activity is detected on the Hsync input pin (Pin 79). If Hsync is held high or low, activity will not be detected.
Table XXXVII. Hsync Detection Results
PDO 0 1
Function Normal operation Three-state Detect 0 1
Function No activity detected Activity detected
The default for this register is 0. (This option works on both the analog and digital interfaces.)
14
2
HDCP Address
The Sync Processing Block Diagram, Figure 18, shows where this function is implemented.
This bit is used to set the HDCP Slave Port address.
Table XXXIII. HDCP Address Settings
15
6
Sync-on-Green Detect
This bit is used to indicate when sync activity is detected on the Sync-on-Green input pin (Pin 64).
Table XXXVIII. Sync-on-Green Detection Results
Address Bit 0 1
14 1
Result 0 for HDCP Slave Port 1 for HDCP Slave Port
Detect 0 1
Function No activity detected Activity detected
The default for this register is 0.
PWRDN
This bit is used to control chip power-down. See the section on power management for details about which blocks are actually powered down.
Table XXXIV. Power-Down Settings
The Sync Processing Block Diagram, Figure 18, shows where this function is implemented.
Note: If no Sync signal is presented on the GREEN video input, normal video may still trigger activity.
15 5 Vsync Detect
Select 0 1
14 0
Result Power-down Normal operation
4:2:2 Output Mode Select
This bit is used to indicate when activity is detected on the Vsync input pin (Pin 80). If Vsync is held high or low, activity will not be detected.
Table XXXIX. Vsync Detection Results
The default for this register is 1.
Detect 0 1
Function No activity detected Activity detected
A bit that configures the output data in 4:2:2 mode. This mode can be used to reduce the number of data lines used from 24 to 16 for applications using YPbPr graphics signals. A timing diagram for this mode is shown in Figure 9. Recommended input and output configurations are shown in Table XXXVI. In 4:2:2 mode, the RED and BLUE channels can be interchanged to help satisfy board layout or timing requirements, but the GREEN channel must be configured for Y.
Table XXXV. 4:2:2 Output Mode Select
The Sync Processing Block Diagram, Figure 18, shows where this function is implemented.
15
4
Digital Interface Clock Detect
This bit is used to indicate when activity is detected on the digital interface clock input.
Table XL. Digital Interface Clock Detection Results
Select 0 1
Output Mode 4:4:4 4:2:2
Table XXXVI. 4:2:2 Input/Output Configuration
Detect 0 1
Function No activity detected Activity detected
The Sync Processing Block Diagram, Figure 18, shows where this function is implemented.
Channel RED GREEN BLUE
Input Connection Pr Y Pr
Output Format Pb/Pr Y High impedance
REV. A
-29-
AD9882
15 3 Active Interface 16 5 AVS Active Vsync
This bit is used to indicate which interface should be active, analog or digital. It checks for activity on the analog interface and for activity on the digital interface, then determines which should be active according to Table XLI. Specifically, analog interface detection is determined by OR-ing Bits 7, 6, and 5 in this register. Digital interface detection is determined by Bit 4 in this register. If both interfaces are detected, the user can determine which has priority via Bit 1 in Register 0FH. The user can override this function via Bit 2 in Register 0FH. If the override bit is set to logic 1, then this bit will be forced to the same state as Bit 1 in Register 0FH.
Table XLI. Active Interface Results
This bit indicates which Vsync source is being used for the analog interface: the Vsync input or output from the sync separator. If the override bit (10H, Bit 1) is set to logic 1, then this bit will be forced to the same state as Bit 0 in Register 10H.
Table XLIV. Active Vsync Results
Vsync Detect Register 16H Bit 5 0 1 X
Override Register 10H Bit 1 0 0 1
AVS 0 1 Bit 0 in 10H
Bits 7, 6, or 5 (Analog Detection) 0
Bit 4 (Digital Detection) 0
Override 0
AI Soft Power-Down (Seek Mode) 1 0 Bit 1 in 0FH Bit 1 in 0FH
AVS = 0 means Vsync input AVS = 1 means Sync separator The override bit is in Register 10H, Bit 1.
16
4
Detected Vsync Output Polarity Status
0 1 1 X
1 0 1 X
0 0 0 1
This bit reports the status of the Vsync output polarity detection circuit. It can be used to determine the polarity of the Vsync output. The detection circuit's location is shown in the Sync Processing Block Diagram, Figure 18.
Table XLV. Detected Vsync Input Polarity Status
AI = 0 means analog interface AI = 1 means digital interface The override bit is in Register 0FH, Bit 2.
Vsync Polarity Status 0 1
16 3
Result Vsync polarity is active high. Vsync polarity is active low.
16
7
AHS
Active Hsync
This bit indicates which Hsync input source is being used by the PLL (Hsync input or Sync-on-Green). Bits 6 and 7 in Register 15H determine which source is used. If both Hsync and SOG are detected, the user can determine which has priority via Bit 3 in Register 10H. The user can override this function via Bit 4 in Register 10H. If the override bit is set to logic 1, then this bit will be forced to the same state as Bit 3 in Register 10H.
Table XLII. Active Hsync Results
Detected Coast Polarity Status
This bit reports the status of the coast input polarity detection circuit. The detection circuit's location is shown in the Sync Processing Block Diagram, Figure 18. This bit only applies to the internal Coast and does not apply when Coast is disabled.
Table XLVI. Detected Coast Input Polarity Status
Hsync Detect SOG Detect Override Register 15H Register 15H Register 10H Bit 7 Bit 6 Bit 4 0 0 1 1 X 0 1 0 1 X 0 0 0 0 1
AHS Register 16H Bit 7 Bit 3 in 10H 1 0 Bit 3 in 10H Bit 3 in 10H
Hsync Polarity Status 0 1
16 2
Result Coast polarity is negative/active low. Coast polarity is positive/active high.
Key Read Verification
This bit reports wherever HDCP keys are detected.
Table XLVII. Key Read Verification
AHS = 0 means use the Hsync pin input for Hsync AHS = 1 means use the SOG pin input for Hsync The override bit is in Register 10H, Bit 4.
Detect 0 1
1B 7
Function Not detected Detected
MDA and MCL Three-State
16
6
Detected Hsync Input Polarity Status
This bit reports the status of the Hsync input polarity detection circuit. It can be used to determine the polarity of the Hsync input. The detection circuit's location is shown in the Sync Processing Block Diagram, Figure 18.
Table XLIII. Detected Hsync Input Polarity Status
Hsync Polarity Status 0 1
Result Hsync polarity is negative/active low. Hsync polarity is positive/active high.
The MDA and MCL three-state feature allows the EEPROM to be programmed in-circuit. The MDA/MCL port must be threestated before attempting to program the EEPROM using an external master. The keys will be stored in an I2C compatible 3.3 V serial EEPROM of at least 512 bytes. The EEPROM should have a device address of A0H.
-30-
REV. A
AD9882
2-WIRE SERIAL CONTROL PORT Data Transfer via Serial Interface
A 2-wire serial control interface is provided. Two AD9882 devices may be connected to the 2-wire serial interface, with each device having a unique address. The 2-wire serial interface comprises a clock (SCL) and a bidirectional data (SDA) pin. The analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. When the serial interface is not active, the logic levels on SCL and SDA are pulled HIGH by external pull-up resistors. Data received or transmitted on the SDA line must be stable for the duration of the positive-going SCL pulse. Data on SDA must change only when SCL is LOW. If SDA changes state while SCL is HIGH, the serial interface interprets that action as a start or stop sequence. There are five components to serial bus operation: Start signal Slave address byte Base register address byte Data byte to read or write Stop signal When the serial interface is inactive (SCL and SDA are HIGH), communications are initiated by sending a start signal. The start signal is a HIGH-to-LOW transition on SDA while SCL is HIGH. This signal alerts all slaved devices that a data transfer sequence is coming. The first eight bits of data transferred after a start signal comprise a 7-bit slave address (the first seven bits) and a single R/W bit (the eighth bit). The R/W bit indicates the direction of data transfer: read from (1) or write to (0) the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA input pin in Table XLVIII), the AD9882 acknowledges by bringing SDA LOW on the ninth SCL pulse. If the addresses do not match, the AD9882 does not acknowledge.
Table XLVIII. Serial Port Addresses
For each byte of data read or written, the MSB is the first bit of the sequence. If the AD9882 does not acknowledge the master device during a write sequence, the SDA remains HIGH so the master can generate a stop signal. If the master device does not acknowledge the AD9882 during a read sequence, the AD9882 interprets this as "end of data." The SDA remains HIGH so the master can generate a stop signal. Writing data to specific control registers of the AD9882 requires that the 8-bit address of the control register of interest be written after the slave address has been established. This control register address is the base address for subsequent write operations. The base address autoincrements by one for each byte of data written after the data byte intended for the base address. If there are more bytes transferred than there are available addresses, the address will not increment and will remain at its maximum value of 1Eh. Any base address higher than 1Eh will not produce an acknowledge signal. Data are read from the control registers of the AD9882 in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation. Reading (the R/W bit of the slave address byte HIGH) begins at the previously established base address. The address of the read register autoincrements after each byte is transferred. To terminate a read/write sequence to the AD9882, a stop signal must be sent. A stop signal comprises a LOW-to-HIGH transition of SDA while SCL is HIGH. The timing for the read/write is shown in Figure 16, and a typical byte transfer is shown in Figure 17. A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines.
Bit 7 A6 (MSB) 1 1
Bit 6 A5 0 0
Bit 5 A4 0 0
Bit 4 A3 1 1
Bit 3 A2 1 1
Bit 2 A1 0 0
Bit 1 A0 (LSB) 0 1
SDA
tBUFF tSTAH
tDHO tDAL
tDSU
tSTASU
tSTOSU
SCL
tDAH
Figure 16. Serial Port Read/Write Timing
REV. A
-31-
AD9882
Serial Interface Read/Write Examples
Write to one control register Start signal Slave address byte (R/W bit = LOW) Base address byte Data byte to base address Stop signal Write to four consecutive control registers Start signal Slave address byte (R/W bit = LOW) Base address byte Data byte to base address Data byte to (base address + 1) Data byte to (base address + 2) Data byte to (base address + 3) Stop signal
Read from one control register Start signal Slave address byte (R/W bit = LOW) Base address byte Start signal Slave address byte (R/W bit = HIGH) Data byte from base address Stop signal Read from four consecutive control registers Start signal Slave address byte (R/W bit = LOW) Base address byte Start signal Slave address byte (R/W bit = HIGH) Data byte from base address Data byte from (base address + 1) Data byte from (base address + 2) Data byte from (base address + 3) Stop signal
SDA
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACK
SCL
Figure 17. Serial Interface, Typical Byte Transfer
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REV. A
AD9882
SYNC STRIPPER NEGATIVE PEAK CLAMP SOG
ACTIVITY DETECT SYNC SEPARATOR COMP SYNC INTEGRATOR 1/S MUX 1 SOG OUT PLL MUX 4 VSYNC
HSYNC IN
ACTIVITY DETECT
POLARITY DETECT HSYNC OUT CLOCK GENERATOR PIXEL CLOCK
HSYNC MUX 2 COAST
HSYNC OUT MUX 5
POLARITY DETECT VSYNC IN
VSYNC OUT ACTIVITY DETECT MUX 3 MUX 6 HSYNC DVI VSYNC DE DE
Figure 18. Sync Processing Block Diagram
Table XLIX. Control of the Sync Block Muxes via the Serial Register
Mux Number(s) 1 and 2 3 4, 5, and 6
Serial Bus Control Bit 10H: Bit 3 10H: Bit 0 0FH: Bit 1
Control Bit State 0 1 0 1 0 1
Result Pass Hsync Pass Sync-on-Green Pass Vsync Pass Sync Separator Signal Pass Analog Interface Signals Pass Digital Interface Signals
REV. A
-33-
AD9882
THEORY OF OPERATION Sync Stripper
This section is devoted to the basic operation of the sync processing engine. (Refer to Figure 18.) The purpose of the sync stripper is to extract the sync signal from the green graphics channel. A sync signal is not present on all graphics systems; only those with Sync-on-Green. The sync signal is extracted from the GREEN channel in a two-step process. First, the SOG input is clamped to its negative peak (typically 0.3 V below the black level). Next, the signal goes to a comparator with a variable trigger level, nominally 0.15 V above the clamped level. The output signal is typically a composite sync signal containing both Hsync and Vsync.
Sync Separator
Place the 75 W termination resistors (see Figure 1) as close to the AD9882 chip as possible. Any additional trace length between the termination resistors and the input of the AD9882 increases the magnitude of reflections, which will corrupt the graphics signal. Use 75 W matched impedance traces. Trace impedances other than 75 W will also increase the chance of reflections. The AD9882 has a very high input bandwidth (300 MHz). While this is desirable for acquiring a high resolution PC graphics signal with fast edges, it means that it will also capture any high frequency noise present. Therefore, it is important to reduce the amount of noise that gets coupled to the inputs. Avoid running any digital traces near the analog inputs. Due to the high bandwidth of the AD9882, sometimes low-pass filtering the analog inputs can help to reduce noise. (For many applications, filtering is unnecessary.) Experiments have shown that placing a series ferrite bead prior to the 75 W termination resistor is helpful in filtering out excess noise. Specifically, the part used was the #2508051217Z0 from Fair-Rite, but different applications may work best with different bead values. Alternatively, placing a 100 W to 120 W resistor between the 75 W termination resistor and the input coupling capacitor can also be beneficial.
Digital Interface Inputs
A sync separator extracts the Vsync signal from a composite sync signal. It does this through a low-pass filter-like or integratorlike operation. It works on the idea that the Vsync signal stays active for a much longer time than the Hsync signal. So, it rejects any signal shorter than a threshold value, which is somewhere between an Hsync pulsewidth and a Vsync pulsewidth. The sync separator on the AD9882 is simply an 8-bit digital counter with a 5 MHz clock. It works independently of the polarity of the composite sync signal. (Polarities are determined elsewhere on the chip.) The basic idea is that the counter counts up when Hsync pulses are present. But since Hsync pulses are relatively short in width, the counter only reaches a value of N before the pulse ends. It then starts counting down, eventually reaching 0 before the next Hsync pulse arrives. The specific value of N will vary for different video modes, but will always be less than 255. For example, with a 1 ms width Hsync, the counter will only reach 5 (1 ms/200 ns = 5). Now, when Vsync is present on the composite sync the counter will also count up. However, since the Vsync signal is much longer, it will count to a higher number M. For most video modes, M will be at least 255. So, Vsync can be detected on the composite sync signal by detecting when the counter counts to higher than N. The specific count that triggers detection (T) can be programmed through the serial register (0EH). Once Vsync has been detected, a similar process detects when it goes inactive. At detection, the counter first resets to 0, then starts counting up when Vsync goes away. In a way similar to the previous case, it will detect the absence of Vsync when the counter reaches the threshold count (T). In this way, it will reject noise and/or serration pulses. Once Vsync is determined to be absent, the counter resets to 0 and begins the cycle again.
PCB LAYOUT RECOMMENDATIONS
Many of the same techniques that are recommended for the analog interface inputs should also be used for the digital interface inputs. It is important to minimize trace lengths, then make the input trace impedances match the input termination (typically 50 W). Each differential input pair (RX0+, RX0-, RXC+, RXC-, and so on) should be routed together using 50 W strip line routing techniques and should be kept as short as possible. No other components, e.g., no clamping diodes, should be placed on these inputs. Every effort should be made to route these signals on a single layer (component layer) with no vias.
Power Supply Bypassing
Bypassing each power supply pin with a 0.1 mF capacitor is recommended. The exception is the case in which two or more supply pins are adjacent to each other. For these groupings of powers/grounds, it is necessary to have one bypass capacitor. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the side of the PC board opposite the AD9882, as that interposes resistive vias in the path. The bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power plane AE capacitor AE power pin. Do not make the power connection between the capacitor and the power pin. Placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. It is particularly important to maintain low noise and good stability of PVD (the clock generator supply). Abrupt changes in PVD can result in similarly abrupt changes in sampling clock phase and frequency. This can be avoided by careful attention to regulation, filtering, and bypassing. It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (VD and PVD).
The AD9882 is a high precision, high speed analog device. In order to derive the maximum performance out of the part, it is important to have a well laid out board. The following is a guide for designing a board using the AD9882.
Analog Interface Inputs
Using the following layout techniques on the graphics inputs is extremely important. Minimize the trace length running into the graphics inputs. This is accomplished by placing the AD9882 as close as possible to the graphics VGA connector. Long input trace lengths are undesirable because they will pick up more noise from the board and other external sources.
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REV. A
AD9882
Some graphic controllers use levels of power when active (during active picture time) that are substantially different from those used when they are idle (during horizontal and vertical sync periods). This can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. This can be mitigated by regulating the analog supply, or at least PVD, from a different, cleaner, power source (for example, from a 12 V supply). Using a single ground plane for the entire board is also recommended. Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller than one common ground plane, and long ground loops can result. In some cases, using separate ground planes is unavoidable. For those cases where they must be used, it is recommended that at least a single ground plane be placed under the AD9882. The location of the split should be at the receiver of the digital outputs. For this case, it is even more important to place components wisely because the current loops will be much longer (current takes the path of least resistance). The following is an example of a current loop: power plane AE AD9882 AE digital output trace AE digital data receiver AE digital ground plane AE analog ground plane.
PLL Outputs (Data and Clocks)
Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance and require more current, which causes more internal digital noise. Shorter traces reduce the possibility of reflections. Adding a series resistor with a value of 22 W to 100 W can suppress reflections, reduce EMI, and reduce the current spikes inside of the AD9882. However, if 50 W traces are used on the PCB, the data output should not need these resistors. A 22 W resistor on the DATACK output should provide good impedance matching that will reduce reflections. If EMI or current spiking is a concern, use a lower drive strength setting by adjusting register 14H. If series resistors are used, place them as close to the AD9882 pins as possible (but avoid adding vias or extra length to the output trace in order to get the resistors closer). If possible, limit the capacitance that each of the digital outputs drives to less than 10 pF. This can be accomplished easily by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance will increase the current transients inside the AD9882, creating more digital noise on its power supplies.
Digital Inputs
Place the PLL loop filter components as close to the FILT pin as possible. Do not place any digital or other high frequency traces near these components. Use the values suggested in the data sheet with 10% or smaller tolerances.
The digital inputs on the AD9882 were designed to work with 3.3 V signals, but are tolerant of 5.0 V signals. No extra components need to be added if 5.0 V logic is used. Any noise that gets onto the Hsync input trace will add jitter to the system. Therefore, minimize the trace length and do not run any digital or other high frequency traces near it.
Voltage Reference
Bypass with a 0.1 mF capacitor. Place as close to the AD9882 pin as possible. Make the ground connection as short as possible.
REV. A
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AD9882
OUTLINE DIMENSIONS 100-Lead Quad Flatpack [LQFP] (ST-100)
Dimensions shown in millimeters
16.00 BSC SQ
1.60 MAX
14.00 BSC SQ
0.75 0.60 0.45
SEATING PLANE
12 TYP
100 1
76 75
TOP VIEW
0.15 0.05 0.08 MAX LEAD COPLANARITY
0.20 0.09
7 3.5 0
(PINS DOWN)
12.00 REF
VIEW A
25 26 51 50
SEATING PLANE
VIEW A
ROTATED 90 CCW
0.50 BSC
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BED THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION
Revision History
Location 1/03--Data Sheet changed from REV. 0 to REV. A. Page
Edits to PIN CONFIGURATION headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edits to Table IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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REV. A
PRINTED IN U.S.A.
C02889-0-1/03(A)

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