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Ordering number : ENN6236
CMOS IC
LC895127, 895127K
40x CD-ROM Decoder with SCSI Interface
Functions
* * * * CD-ROM ECC function SCSI I/F function Subcode I/F function CAV audio function
* CAV audio function * Supports 20 MBytes/s transfers * Package: SQFP-144
Package Dimensions
unit: mm 3214-SQFP144
[LC895127, 895127K]
1.25
109
Features
* SCSI interface (includes on-chip SCAM selection register) * Supports 20x speed and a 10 MBytes/s transfer rate when using 16-bit 70-ns EDO DRAM * Supports 40x speed and a 10 MB/s transfer rate when using 16-bit 50-ns EDO DRAM * Up to 4 M bits of buffer RAM can be used. * The user can freely set up the CD main channel and the C2 flag areas in buffer RAM. * Batch transfer function (Allows the CD main channel, the C2 flags, and other data to be sent in a single operation.) * Multi-block transfer function (Allows multiple blocks to be sent automatically in a single operation.) * Subcode buffering and CD-TEXT support
0.5
108
22.0 20.0
1.25
73 72
0.145
22.0 20.0 0.5
1.25
1.6max
144
37 1
0.20
36
0.1 1.4
1.25
0.5
0.5
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Maximum supply voltage Input/output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature (pin part only) Symbol VDD max VI, VO Pd max Topr Tstg 10 s Ta = 25C Ta = 25C Ta 70C Conditions
SANYO: SQFP144
Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 550 -30 to +70 -55 to +125 260
Unit V V mW C C C
Allowable Operating Ranges at Ta = -30C to +70C, VSS = 0 V
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 4.5 0 typ 5.0 max 5.5 VDD Unit V V
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D1599TH (OT)/30899TH (OT) No. 6236-1/8
LC895127, 895127K DC Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output low-level voltage Input leakage current Pull-up resistance Applicable pin sets are as follows. INPUT (1) (2) (3) (4) TEST0 to TEST4, CSCTRL, SUA0 to SUA6, C2P0, SDATA, BCK, LRCK, SCOR, WFCK, SBS0, MCK2SEL RESET CS, RD, WR SCSISEL, XTALSEL Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIH4 VIL4 VIH5 VIL5 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH2 VOL2 VOL4 IIL RUP TTL levels with pull-up resistor IOH1 = -12 mA IOL1 = 12 mA IOH2 = -8 mA IOL2 = 8 mA IOH2 = -2 mA IOL2 = 2 mA IOL4 = 48 mA VI = VSS, VDD Conditions Applicable pins Ratings min 2.2 0.8 2.2 -- 2.2 -- 0.8 VDD -- 2.0 -- -- -- -- -- -- -- 0.8 -- 0.8 -- 0.2 VDD -- 0.8 2.2 -- VDD - 2.1 -- 2.4 0.4 2.4 0.4 0.4 -25 60 120 +25 240 -- -- -- -- 0.8 -- 0.4 typ max Unit V V V V V V V V V V V V V V V V V V V A k
TTL levels TTL levels with pull-up resistor TTL levels Schmitt CMOS levels Schmitt
(1)
(9)
(2)
(3)
(4), (8), (10)
(11)
(6)
(7)
(9), (5), (11) (10) All input pins (5), (9), (11)
OUTPUT (5) (6) (7) INT0, INT1, SWAIT MCK EXCK, DSDATA, DLRCK, DBCK, RAS0, CAS0, CAS1, OE, UWE, LWE, RA0 to RA8
INOUT (8) (9) ACK, ATN D0 to D7, IO0 to IO15, IOP0 to IOP7
(10) DB0 to DB7, DBP, BSY, I/O, MSG, SEL, RST, REQ, C/D (11) IOP0 to IOP7 Note: Pins XTAL0, XTALCK0, XTAL1, XTALCK1, and X1EN are not included in DC characteristics.
No. 6236-2/8
LC895127, 895127K SCSI Pin Input Characteristics
Parameter Symbol Vt+t1 Vt-t1 Vtt1 Conditions Ratings min typ 1.60 0.80 0.41 1.10 0.5 max 2.00 Unit V V V
Input threshold voltage Hysteresis width
VDD = 4.50 to 5.50 V VDD = 5.0 V
Active-Low Output Characteristics
Parameter Output high-level voltage Output low-level voltage Symbol VOH VOL Conditions Ratings min 2.5 0.4 typ max Unit V V
Note: Only applies to the active-low output pins DB0 to DB7, REQ, DBPB
SCSI driver
TP 47 5 %
Rise time test circuit
15 pF 5 % + 2.5 V -
A12526
Recommended Oscillator and PLL Circuits LC895127 LC895127 PLL
XTALCK0 PN27 R1 XTAL0 PN28 R2 R3 C4 PN69 PN70 R4 C5 C3 R5 PN71
C1
C2
A12527
A12528
R1 = 120 k, R2 = 47 , C1 = 30 pF Crystal oscillator frequency XTALCK0 = 16.9344 MHz R3 = 7.5 k, R4 = 200 , R5 = 10 k, C3 = 0.1 F C4 = 0.1 F, C5 = 0.002 F to 0.01 F Note: The values listed above for R3, R4, R5, and C3 also apply when the XTALKC0 frequency is 33.8688 MHz. Applications must be designed so that the analog VDD and VSS power supply system is completely independent of the logic system power supply and is not affected by the logic system power supply fluctuation in any way. Note: Since the exact values of these components will vary depending on the characteristics of the printed circuit board used and other factors, consult the manufacturer of the crystal element when designing the oscillator circuit.
No. 6236-3/8
LC895127, 895127K Pin Functions
I O Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Pin name VSS0 IO2 IO1 IO0 MCK2SEL C2PO SDATA BCK LRCK EXCK WFCK SBSO SCOR DSDATA DLRCK DBCK MCK VDD VSS0 RESET CSCTRL TEST3 TEST0 TEST1 TEST2 VSS0 XTALCK0 XTAL0 TEST4 VSS0 VSS0 VSS0 VSS0 IOP7 IOP6 VSS0 VDD IOP5 IOP4 IOP3 IOP2 IOP1 IOP0 VSS0 RD WR CS SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 Type P B B B I I I I I O I I I O O O O P P I I I I I I P I O I P P P P I I P P I I I I I I P I I I I I I I I I Microcontroller register selection signals Microcontroller data read signal input Microcontroller data write signal input Register chip select input from the microcontroller General-purpose I/O ports. These pins include built-in pull-up resistors. General-purpose I/O ports. These pins include built-in pull-up resistors. Crystal oscillator circuit input Crystal oscillator circuit output Test pin. This pin must be connected to VSS0 in normal operation. Test pins. These pins must be connected to VSS0 in normal operation. IC reset. The IC is reset on a low-level input MC (Microcontroller) CSL0, Hi XTALCLK0 1/1, 1/2, and stop output D/A converter outputs Subcode I/O Subcode I/O CD DSP interface Buffer RAM data I/O These pins have built-in pull-up resistors. PLL frequency selection. Currently, this pin must be connected to VDD. INPUT OUTPUT B P Pin functions Type BIDIRECTION POWER NC NOT CONNECT
Continued on next page. No. 6236-4/8
LC895127, 895127K
Continued from preceding page.
Pin No. 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 DBP VDD DB7 DB6 VSS1 DB5 DB4 VDD DB3 DB2 VSS1 DB1 DB0 SCSISEL XTALSEL VDD VSS1 MSG RST VSS1 ACK BSY VSS1 ATN VDD VSS1 I/O REQ VSS1 C/D SEL Pin VDD VSS0 SUA6 D0 D1 D2 D3 D4 D5 VSS0 D6 D7 INT0 INT1 SWAIT X1EN XTALCK1 XTAL1 VSS0 VDD I/O P P I B B B B B B P B B O O O I I O P P NC B B P B B NC P P B B P B B B B P P NC B P B B P B B P B B P B B I I SCSI interface SCSI pin layout selection. (This pin must be connected to VSS0.) PLL XTAL oscillator selection SCSI interface SCSI interface SCSI interface SCSI interface SCSI interface SCSI interface SCSI interface SCSI interface SCSI interface Microcontroller data signals Interrupt request signal output to the microcontroller (ECC side. Set by setting a register value.) Interrupt request signal output to the microcontroller (SCSI side. Set by setting a register value.) Wait signal output to the microcontroller Used by the PLL. This pin must be connected to VDD through a resistor. Used by the PLL. Used by the PLL. Analog VSS Analog VDD Microcontroller data signals Microcontroller register selection signals Function
Continued on next page.
No. 6236-5/8
LC895127, 895127K
Continued from preceding page.
Pin No. 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin VSS1 VDD VSS0 RAS0 VDD CAS0 CAS1 OE UWE (RA9) LWE VSS0 RA0 RA1 RA2 RA3 RA4 RA5 RA6 VDD VSS0 RA7 RA8 IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8 VSS0 IO7 IO6 IO5 IO4 IO3 VDD I/O P P P O P O O O O O P O O O O O O O P P O O B B B B B B B B P B B B B B P Buffer RAM data I/O These pins have built-in pull-up resistors. Buffer RAM data I/O These pins have built-in pull-up resistors. Buffer RAM address signal outputs Buffer RAM address signal outputs Buffer RAM CAS signal output 0 (Normally held fixed at 0 (low).) Buffer RAM RAS signal output 1 Buffer RAM output enable Buffer RAM upper write enable (RA9 when 8M or more DRAM is used.) Buffer RAM lower write enable Buffer RAM RAS signal output 0 Function
Unused ("NC") pins must be left open. Pins whose name is under a bar operate with inverted (negative) logic. VSS0 is the logic system ground and VSS1 is the SCSI interface driver ground. If DRAM is used, applications must adopt measures to prevent undershoot and other DRAM problems. Such measures include inserting resistors in the RAS and CAS lines and inserting capacitors between VSS pins. See the article on Designing with the Latest Microcontrollers and Memory in special issue number 25 of Transistor Technology for details on these measures. Since this device includes buffers that sink a current of 48 mA, applications must take adequate noise prevention measures.
No. 6236-6/8
LC895127, 895127K Block Diagram
Data bus[0:7] *10
RAM Data bus[0:15] Address bus[0:21]
LC895127
*1 CD-DSP EXCK
Sub-code I/F de-interleve Address generator
*2
CD-DSP I/F & SYNC Detector
De-scramble & Buffering Address generator
ECC & EDC Address generator HOST
Each Block Bus control signal External Bus Arbiter & RAM controller *7 *8 Buffer
*3 *4 Each Block Register
SCSI I/F Block
INT0, 1 Micro controller *5 *6 SWAIT XTALCK XTAL
DRAM Data output input I/F Address generator
decoder
Microcontroller RAM access Clock generator & PLL Address generator
CAV-Audio control Address generator
*9
MCK
Each Block
DAC
A12529
*1 *2 *3 *4 *5 *6 *7 *8 *9
WFCK, SBSO, SCOR BCK, SDATA, LRCK, C2PO DB0 to DB7, DBP, BSY, MSG, SEL, RST, REQ, I/O, C/D ACK, ATN RD, WR, SUA0 to SUA6, ZCS, CSCTRL D0 to D7 IO0 to IO15 RA0 to RA10, RAS1, CAS0, CAS1, OE, UWE, LWE DBCK, DLRCK, DSDATA
*10 IOP7 to IOP0
No. 6236-7/8
LC895127, 895127K
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1999. Specifications and information herein are subject to change without notice. PS No. 6236-8/8

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