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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21352-1E
ASSP
Single Serial Input PLL Frequency Synthesizer
On-Chip 1.2 GHz Prescaler
MB15E03L
s DESCRIPTION
The Fujitsu MB15E03L is serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz prescaler. A 64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation. The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 2.5 mA typ. This operates with a supply voltage of 3.0 V (typ.) Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result of this, MB15E03L is ideally suitable for digital mobile communications, such as GSM(Global System for Mobile Communications), PDC(800MHz)(Personal Digital Cellular).
s FEATURES
* * * * * * * High frequency operation: 1.2 GHz max Low power supply voltage: VCC = 2.7 to 3.6 V Very Low power supply current : ICC = 2.5 mA typ. (VCC = 3 V) Power saving function : IPS = 0.1 A typ. Pulse swallow function: 64/65 or 128/129 Serial input 14-bit programmable reference divider: R = 5 to 16,383 Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 5 to 2,047 * Wide operating temperature: Ta = -40 to 85C * Plastic 16-pin SSOP package (FPT-16P-M05) and 16-pin BCC package (LCC-16P-M02)
s PACKAGES
16-pin, Plastic SSOP 16-pin, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M02)
This device contains circuitry to protect the inputs against damage due to high static voltages or electroc fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
MB15E03L
s PIN ASSIGNMENTS
SSOP-16 pin
OSCin OSCout Vp Vcc Do GND Xfin fin
1 2 3 4
16 15 14
R P LD/fout ZC PS LE Data Clock
TOP 13 VIEW 5 12 6 7 8 11 10 9
(FPT-16P-M05) BCC-16 pin
OSCin OSCout VP VCC Do GND Xfin 1 2 3 4 5 6 7 fin 8 TOP VIEW 16 15
R 14 13 12 11 10 9 P LD/fout ZC PS LE Data
Clock
(LCC-16P-M02)
2
MB15E03L
s PIN DESCRIPTIONS
Pin no. SSOP 1 BCC 16 Pin name I/O Descriptions Programmable reference divider input. Oscillator input. Connection for an crystal or a TCXO. TCXO should be connected with a coupling capacitor. Oscillator output. Connection for an external crystal. Power supply voltage input for the charge pump. Power supply voltage input. Charge pump output. Phase of the charge pump can be reversed by FC bit. Ground. Prescaler complementary input, and should be grounded via a capacitor. Prescaler input. Connection with an external VCO should be done with AC coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Control bit = "H" ; Data is transmitted to the programmable reference counter. Control bit = "L" ; Data is transmitted to the programmable counter. Load enable signal input (Open is prohibited.) When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. Power saving mode control. This pin must be set at "L" at Power-ON. (Open is prohibited.) PS = "H" ; Normal mode PS = "L" ; Power saving mode Forced high-impedance control for the charge pump (with internal pull up resistor.) ZC = "H" ; Normal Do output. ZC = "L" ; Do becomes high impedance. Lock detect signal output(LD)/phase comparator monitoring output (fout). The output signal is selected by LDS bit in the serial data. LDS = "H" ; outputs fout (fr/fp monitoring output) LDS = "L" ; outputs LD ("H" at locking, "L" at unlocking.) Phase comparator output for an external charge pump. Nch open drain output. Phase comparator output for an external charge pump. CMOS output.
OSCIN
I
2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8
OSCOUT VP VCC DO GND Xfin fin Clock
O - - O - I I I
10
9
Data
I
11
10
LE
I
12
11
PS
I
13
12
ZC
I
14
13
LD/fout
O
15 16
14 15
P R
O O
3
MB15E03L
s BLOCK DIAGRAM
OSCIN 1
fr
Crystal Oscillator circuit
OSCOUT 2
fp
Programmable reference divider
Binary 14-bit reference counter fr LD
Phase comparator
16 R
15 P
Lock detector
PS 12
Intermittent mode control (power save)
LE
SW LDS
17-bit latch
FC
14-bit latch 1-bit control latch
3-bit latch
fp
LD/fr/fp selector
14 LD/fout
LE 11
19-bit shift register
Data 10
C N T
13 ZC
19-bit shift register Super charger
3 VP
Clock 9
5 DO
LE
18-bit latch 7-bit latch 11-bit latch
SW
Programmable divider
XfIN 7 fIN 8
Prescaler 64/65, 128/129
Binary 7-bit swallow counter
Binary 11-bit programmable counter
fp
GND 6
VCC 4
MD
Control Circuit
Note: SSOP-16 pin
4
MB15E03L
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Output current Storage temperature Symbol VCC VP VI VO IO I Od Tstg Rating Min. -0.5 VCC -0.5 -0.5 -10 -25 -55 Max. +4.0 +6.0 VCC +0.5 VCC +0.5 +10 +25 +125 Unit V V V V mA mA C Except D O output D O output Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VP VI Ta Value Min. 2.7 VCC GND -40 Typ. 3.0 - - - Max. 3.6 6.0 VCC +85 Unit V V V C Remark
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always yse semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with repect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
Handling Precautions
* This device should be transported and stored in anti-static containers. * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workerbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15E03L
s ELECTRICAL CHARACTERISTICS
(VCC = 2.7 to 3.6 V, Ta = -40 to +85C) Value Unit Min. Typ. Max. - - 100 3 -10 0.5 Vcc x 0.7 - -1.0 -1.0 -1.0 -100 0 -100 - Vcc - 0.4 - Vp - 0.4 - - 1.0 -1.0 - -11 8 2.5 0.1 - - - - - - - - - - - - - - - - - - - - - - - - 10 1200 40 +2 VCC - Vcc x 0.3 +1.0 +1.0 +1.0 0 +100 0 0.4 - 0.4 - 0.4 3.0 - - 1.0 -6 mA 15 nA mA mA V V mA mA MHz MHz dBm Vp-p
Parameter Power supply current*1 Power saving current Operating frequency Crystal oscillator operating frequency Input sensitivity fin*3 OSCin*3 Data, Clock, LE, PS, ZC Data, Clock, LE, PS Input current ZC OSCin P R, LD/fout
Symbol ICC*1 Ips*2 fin
*3
Condition fin = 1200 MHz, fosc = 12 MHz ZC = "H", PS = "L", -- -- 50 system (Refer to the test circuit.) -- -- -- -- -- -- Pull up input -- -- Open drain output Vcc = 3V, IOH = -1mA Vcc = 3V, IOL = 1mA Vcc = 3V, IDOH = -1mA Vcc = 3V, IDOL =1 mA Vcc = 3V, VP = 6V VOOP = GND to 6V Open drain output -- -- VCC = Vp = 3 V, VDOH = 2.0 V VCC = Vp = 3 V, VDOL = 1.0 V
fOSC Vfin VOSC VIH VIL IIH*4 IIL*4 IIH*4 IIL
*4
Input voltage
A A A V V
IIH IIL*4 VOL VOH VOL VDOH VDOL
Output voltage
Do High impedance cutoff current
Do P R, LD/fout
IOFF IOL IOH
*4
IOL IDOH*4
Output current Do*5 IDOL *1: *2: *3: *4: *5: 6
*4
Conditions; VCC = 3.0 V, Ta = 25C, in locking state. Vcc = 3.0V, fosc=12.8MHz, Ta = 25C in power saving mode AC coupling with a 1000pF capacitor connected. The symbol "-"(minus) means direction of current flow. Ta = +25C
MB15E03L
s FUNCTION DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation: fVCO = [(M x N) + A] x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (5 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) M : Preset divide ratio of modules prescaler (64 or 128)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high, stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT) H L Destination of serial data 17 bit latch (for the programmable reference divider) 18 bit latch (for the programmable divider)
Shift Register Configuration
Programmable Reference Counter (LSB)
1 C N T 2 R 1 3 R 2 4 R 3 5 R 4 6 R 5
(Data Flow)
7 R 6 8 R 7 9 R 8 10 R 9 11 R 10 12 R 11 13 R 12 14 R 13 15 16
(MSB)
17 18
R 14 SW FC LDS
CNT : Control bit R1 to R14: Divide ratio setting bit for the programmable reference counter (5 to 16,383) SW : Divide ratio setting bit for the prescaler (64/65 or 128/129) FC : Phase control bit for the phase comparator LDS : LD/fout signal select bit Note: Start data input with MSB first
[Table. 1] [Table. 2] [Table. 5] [Table. 7] [Table. 6]
7
MB15E03L
Programmable Reference Counter (LSB)
1 C N T 2 A 1 3 A 2 4 A 3 5 A 4 6 A 5 7 A 6 8 A 7
Data Flow
9 N 1 10 N 2 11 N 3 12 N 4 13 N 5 14 N 6 15 N 7 16 N 8 17 N 9
(MSB)
18 N 10 19 N 11
CNT : Control bit N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) Note: Start data input with MSB first
[Table. 1] [Table. 3] [Table. 4]
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 5 6 16383 R 14 0 0 1 R 13 0 0 1 R 12 0 0 1 R 11 0 0 1 R 10 0 0 1 R 9 0 0 1 R 8 0 0 1 R 7 0 0 1 R 6 0 0 1 R 5 0 0 1 R 4 0 0 1 R 3 1 1 1 R 2 0 1 1 R 1 1 0 1
Note: Divide ratio less than 5 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) 5 6 2047 N 11 0 0 1 N 10 0 0 1 N 9 0 0 1 N 8 0 0 1 N 7 0 0 1 N 6 0 0 1 N 5 0 0 1 N 4 0 0 1 N 3 1 1 1 N 2 0 1 1 N 1 1 0 1
Note: * Divide ratio less than 5 is prohibited. * Divide ratio (N) range = 5 to 2,047
8
MB15E03L
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide ratio (A) 0 1 127 A 7 0 0 1 A 6 0 0 1 A 5 0 0 1 A 4 0 0 1 A 3 0 0 1 A 2 0 0 1 A 1 0 1 1
Note: * Divide ratio (A) range = 0 to 127
Table. 5 Prescaler Data Setting
SW H L Prescaler Divide ratio 64/65 128/129
Table. 6 LD/fout Output Select Data Setting
LDS H L fout signal LD signal LD/fout output signal
Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the phase comparator output (R, P) are reversed according to the FC bit. Also, the monitor pin (fOUT) output is controlled by the FC bit. The relationship between the FC bit and each of DO, R, and P is shown below.
Table. 7 FC Bit Data Setting (LDS = "H")
FC = High Do fr > fp fr < fp fr = fp H L Z* R L H L P L Z* Z* fout = fr LD/fout Do L H Z* H L L FC = Low R P Z* L Z* fout = fr LD/fout
* : High impedance
9
MB15E03L
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
: When the LPF and VCO characteristics are
similar to (1), set FC bit high. : When the VCO characteristics are similar to (2), set FC bit low. VCO Output Frequency
(1)
PLL
LPF
VC
LPF Input Voltage
(2)
Table.8 PS Pin Setting
PS pin H L Normal mode Power saving mode Status
Table.9 ZC Pin Setting
ZC pin H L Do output Normal output High impedance
10
MB15E03L
3. Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to 10A (max.). Setting PS pin to High, power saving mode is released so that the IC works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from the power saving mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up, thus keeping the loop locked. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 A (max.). At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high impedance. A VCO control voltage is naturally kept at the locking voltage which defined by a LPF"s time constant. As a result of this, VCO's frequency is kept at the locking frequency. Note: * While the power saving mode is executed, ZC pin should be set at "H" or open. If ZC is set at "L" during power saving mode, approximately 10 A current flows. * PS pin must be set "L" at Power-ON. * The power saving mode can be released (PS : L H) 1s later after power supply remains stable. * During the power saving mode, it is possible to input the serial data.
ON V CC
Clock Data LE
,,,, ,,,, ,,,, ,,,, ,,,, ,,,,
(1) (2) (3)
PS
(1) PS = L (power saving mode) at Power-ON. (2) Set serial data after power supply remains stable. (3) Release saving mode (PS: LH) after setting serial data.
11
MB15E03L
4. Serial Data Input Timing
1st. data 2nd. data
Control bit Invalid data ~ Data MSB ~ ~ Clock t1 t7 LE ~ t4 t5 t2 t3 t6 LSB
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
t1 t2 t3 t4
Min.
20 20 30 30
Typ.
- - - -
Max.
- - - -
Unit
ns ns ns ns
Parameter
t5 t6 t7
Min.
100 20 100
Typ.
- - -
Max.
- - -
Unit
ns ns ns
12
MB15E03L
PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp tWU LD [ FC = "H" ] P tWL
R H Do Z L
[ FC = "L" ] P
R
H Do L Z
Notes: 1. Phase error detection range: -2 to +2 2. Pulses on Do output signal during locked state are output to prevent dead zone. 3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cysles or more. 4. tWU and tWL depend on OSCin input frequency.
tWU > 4/fosc (e. g. tWU > 312.5ns, foscin = 12.8 MHz) tWL < 8/fosc (e. g. tWL < 625.0ns, foscin = 12.8 MHz)
5. LD becomes high during the power saving mode (PS = "L".)
13
MB15E03L
s TEST CIRCUIT
For Measuring Input Sensitivity fin/OSCin
VCC = VP = 3V 0.1F 1000pF S*G 50 1000pF 87654321 9 10 11 12 13 14 15 16 Oscilloscope Controller (setting divide ratio)
Note: SSOP-16 pin
1000pF 0.1F 50 S*G
Vcc
14
MB15E03L
s TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
(dBm) +10
Input sensitivity vs. Input frequency
0 Inpt sensitivity V fin -10 -20
,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,,
SPEC 500 1000 Input frequency fin 1500
Ta = +25C
-30 -40 0
V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V 2000 (MHz)
2. OSCin Input Sensitivity
(dBm) +10 0
V OSC
-10
,,,,,,,,, ,,,,,,,,, ,,,,,,,,,
SPEC
Input senstiviry vs. Input frequency
Ta = +25C
Input sensitivity
-20
-30 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V 0 50 Input frequency OSC IN 100 (MHz)
-40
15
MB15E03L
3. DO Output Current
V OH vs. I OH
(V) 5.0 Ta = +25C V CC = 3 V V P = 3 V, 5 V
4.0
V OH
3.0
2.0
1.0
0 0 -5 -10 I OH -15 -20 (mA)
V OL vs. I OL
(V) 5.0 Ta = +25C V CC = 3 V V P = 3 V, 5 V
4.0
V OL
3.0
2.0
1.0
0 0 5 10 I OL 15 20 (mA)
16
MB15E03L
4. fin Input Impedance
fIN
1: 277.41 -614.31 100 MHz 2: 26.438 -173.77 400 MHz 3: 12.141 -75.824 800 MHz 4: 9.9883 -36.469 1.2 GHz
1
4
2
3 START 100.000 000 MHz STOP 1 200.000 000 MHz
5. OSCIN Input Impedance
OSC IN
1:
6.776 k -20.479 k 3 MHz 797.75 -5.6205 k 10 MHz 408.0 -2.9011 k 20 MHz
2:
3: 4
1 3 4: 134.75 3 -1.5911 k 40 MHz
START 1.000 000 MHz
STOP 50.000 000 MHz
17
MB15E03L
s REFERENCE INFORMATION (lock up time, phase noise, reference leakage)
S.G.
OSC IN
DO
LPF
fin Spectrum Analyzer
VCO
f VCO=810.45 MHz k V=17 MHz/V fr=25 kHz f OSC=14.4MHz
* LPF
9.1 k Do 2.7 k 6800 pF 0.068 F 1500 pF VCO
(Continued)
18
MB15E03L
(Continued)
PLL lock up time = 1.6 ms 810.45MHz 826.45 MHz 1 kHz
PLL lock up time = 1.6 ms 826.45MHz 810.45 MHz 1 kHz
Mkr X: 1.59998172 ms Y: 15.35108 MHz 50.00000 MHz
Mkr X: 1.60000413 ms Y: -14.91665 MHz 50.00000 MHz
10.00000 MHz/div
5.00000 MHz/div
0 Hz 25.1761s 4.9751761 ms Meas # 40
25.00000 MHz 25.1463 s 4.9753963 ms Meas # 40
Mkr X: 1.59998172 ms Y: 15.35108 MHz 30.00500 MHz
Mkr X: 1.60000413 ms Y: -14.91665 MHz 30.00500 MHz
2.000 kHz/div
2.00 MHz/div
29.99500 MHz 25.1761s 4.9751761 ms Meas # 40
29.99500 MHz 25.1463 s 4.9753963 ms Meas # 40
(Continued)
19
MB15E03L
(Continued)
* PLL phase noise
REF -5.0 dB m
ATT 10 dB
MKR
2.18 kHz -52.3 dB
72.3 dBc/Hz RBW 100 Hz VBW 100 Hz
SWP 10 s
SPAN 20.0 kHz
CENTER 810.4500 MHz
* PLL reference leakage
REF -5.0 dB m
ATT 10 dB
MKR
25.0 kHz -77.6 dB
77.6 dBc/Hz RBW 1 kHz VBW 1 kHz
SWP 1.0 s
SPAN 200 kHz
CENTER 810.450 MHz
20
MB15E03L
s APPLICATION EXAMPLE
V PX (6 V)
10 k 12 k 12 k LPF VCO
OUTPUT
10 k Lock Det.
From a controller
R 16 15
P
LD/fout 14 13
ZC 12
PS 11
LE
Data 10
Clock 9
MB15E03L
1 OSC IN X' tal
2 OSC OUT
3 VP 3V
4 V CC 3V
5 DO
6 GND
7 Xfin
8 fin 1000 pF
1000 pF C1 C2 0.1 F 0.1 F
C1, C2: Depend on the crystal parameters Vp: 6V Max
21
MB15E03L
s ORDERING INFORMATION
Part number MB15E03L PFV1 MB15E03L PV Package 16 pin, Plastic SSOP (FPT-16P-M05) 16 pin, Plastic BCC (LCC-16P-M02) Remarks
22
MB15E03L
s PACKAGE DIMENSIONS
16 pins, Plastic SSOP (FPT-16P-M05)
* 5.000.10(.197.004)
* : These dimensions do not include resin protrusion.
1.25 -0.10 +.008 .049 -.004
+0.20
0.10(.004)
INDEX
*4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 +.004 .009 -.002
+0.10
"A"
0.15 -0.02 +.002 .006 -.001
+0.05
Details of "A" part 0.100.10(.004.004) (STAND OFF)
4.55(.179)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in mm (inches).
(Continued)
23
MB15E03L
(Continued)
16-pin, Plastic BCC (LCC-16P-M02)
4.550.10 (.179.004) 0.80(.032)MAX
9
3.40(.134)TYP
9
14
(Mounting height)
0.65(.026)TYP
14
0.400.10 (.016.004) 3.400.10 (.1339.0039) 45 2.45(.096) TYP "A" "B" 1.15(.045)TYP
0.80(.032) TYP
1
E-MARK
6
0.40(.016) 0.0850.04 (.003.002) (STAND OFF)
6
0.3250.10 (.013.004)
1.725(.068) TYP
1
Details of "A" part 0.05(.002) 0.750.10 (.030.004)
Details of "B" part 0.600.10 (.024.004)
0.400.10 (.016.004)
0.600.10 (.024.004)
C
1996 FUJITSU LIMITED C16013S-1C-1
Dimensions in mm (inches)
24
MB15E03L
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9707 (c) FUJITSU LIMITED
Printed in Japan
28

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