View MB15E07SL_80259.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21358-3E
ASSP
Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler
MB15E07SL
s DESCRIPTION
The Fujitsu MB15E07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse swallowing operation. The supply voltage range is between 2.4 V and 3.6 V. The MB15E07SL uses the latest BiCMOS process, as a result the supply current is typically 3.5 mA at 2.7 V. A refined charge pump supplies well-balanced output currents of 1.5 mA and 6 mA. The charge pump current is selectable by serial data. MB15E07SL is ideally suited for wireless mobile communications, such as GSM (Global System for Mobile Communications) and PCS.
s FEATURES
* High frequency operation: 2.5 GHz max * Low power supply voltage: VCC = 2.4 to 3.6 V * Ultra Low power supply current: ICC = 3.5 mA typ. (VCC = Vp = 2.7 V, Ta = +25C, in locking state) ICC = 4.0 mA typ. (VCC = Vp = 3.0 V, Ta = +25C, in locking state) * Direct power saving function: Power supply current in power saving mode Typ. 0.1 A (VCC = Vp = 3.0 V, Ta = +25C), Max. 10 A (VCC = Vp = 3.0 V) * Dual modulus prescaler: 32/33 or 64/65 * Serial input 14-bit programmable reference divider: R = 3 to 16,383 * Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 * Software selectable charge pump current * On-chip phase control for phase comparator * Operating temperature: Ta = -40 to +85C * Pin compatible with MB15E07, MB15E07L
s PACKAGES
16-pin plastic SSOP 16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M06) 1
MB15E07SL
s PIN ASSIGNMENTS
16-pin SSOP
OSCIN OSCOUT VP VCC DO GND Xfin fin 1 2 3 4 5 6 7 8
Top view
16-pad BCC
R P LD/fout ZC PS LE Data Clock OSCOUT VP VCC DO GND Xfin 1 2 16 15 14 13 3 Top view 12 4 11 5 10 6 7 8 9
16 15 14 13 12 11 10 9
OSCIN R P LD/fout ZC PS LE Data
fin Clock
(FPT-16P-M05)
(LCC-16P-M06)
2
MB15E07SL
s PIN DESCRIPTIONS
Pin no. SSOP 1 2 3 4 5 6 7 8 9 10 11 BCC 16 1 2 3 4 5 6 7 8 9 10 Pin name OSCIN OSCOUT VP VCC DO GND Xfin fin Clock Data LE I/O I O - - O - I I I I I Descriptions Programmable reference divider input. Connection to a TCXO. Oscillator output. Power supply voltage input for the charge pump. Power supply voltage input. Charge pump output. Phase of the charge pump can be selected via programming of the FC bit. Ground. Prescaler complementary input, which should be grounded via a capacitor. Prescaler input. Connection to an external VCO should be done via AC coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Load enable signal input. (Open is prohibited.) When LE is set high, the data in the shift register is transferred to a latch according to the control bit in the serial data. Power saving mode control. This pin must be set at "L" at Power-ON. (Open is prohibited.) PS = "H"; Normal mode PS = "L"; Power saving mode Forced high-impedance control for the charge pump (with internal pull up resistor.) ZC = "H"; Normal Do output. ZC = "L"; Do becomes high impedance. Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected via programming of the LDS bit. LDS = "H"; outputs fout (fr/fp monitoring output) LDS = "L"; outputs LD ("H" at locking, "L" at unlocking.) Phase comparator N-channel open drain output for an external charge pump. Phase can be selected via programming of the FC bit. Phase comparator CMOS output for an external charge pump. Phase can be selected via programming of the FC bit.
12
11
PS
I
13
12
ZC
I
14
13
LD/fout P R
O
15 16
14 15
O O
3
MB15E07SL
s BLOCK DIAGRAM
(16) OSCIN 1
fr Reference oscillator circuit
Phase comparator
(15) 16 R
(1) OSCOUT 2
Binary 14-bit reference counter
(14) 15 P SW FC LDS CS
Lock detector
(2) VP 3
14-bit latch .. C N T
4-bit latch fp
LD/fr/fp selector
(13) 14 LD/fout
(3) VCC 4
19-bit shift register
(12) 13 ZC
...
Current switch Charge pump
...
7-bit latch Binary 7-bit swallow counter
11-bit latch
Binary 11-bit programmable counter
(4) DO 5
Intermittent mode control (power save)
(11) 12 PS
(5) GND 6 1-bit control latch (6) Xfin 7 Prescaler 32/33 64/65 MD
(10) 11 LE
(9) 10 Data
(7) fin 8
(8) 9 Clock
: SSOP ( ) : BCC
4
MB15E07SL
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VP VI VO VO Tstg Condition - - - Except Do Do - Rating Min. -0.5 VCC -0.5 GND GND -55 Max. 4.0 6.0 VCC +0.5 VCC VP +125 Unit V V V V V C Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VP VI Ta Value Min. 2.4 VCC GND -40 Typ. 3.0 - - - Max. 3.6 5.5 VCC +85 Unit V V V C Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15E07SL
s ELECTRICAL CHARACTERISTICS
(VCC = 2.4 to 3.6 V, Ta = -40 to +85C) Parameter Power supply current*1 Power saving current Operating frequency fin OSCIN fin*3 OSCIN*3 "H" level input voltage "L" level input voltage "H" level input current "L" level input current "H" level input current "L" level input current "H" level input current "L" level input current "L" level output voltage "H" level output voltage Data, Clock, LE, PS, ZC Data, Clock, LE, PS OSCIN ZC P Symbol ICC*1 IPS fIN OSCIN Pfin VOSC VIH VIL IIH*4 IIL*4 IIH IIL IIL
*4
Condition fin = 2500 MHz, VCC = VP = 2.7 V (VCC = VP = 3.0 V) ZC = "H" or open - - 50 system (Refer to the measurement circuit.) - - - - - - - - Pull up input Open drain output VCC = VP = 3.0 V, IOH = -1 mA VCC = VP = 3.0 V, IOL = 1 mA VCC = VP = 3.0 V, IDOL = 0.5 mA VCC = VP = 3.0 V, VOFF = 0.5 V to VP - 0.5 V Open drain output - - VCC = 3 V, VP = 3 V, VDO = VP/2 Ta = +25C CS bit = "H" CS bit = "L" CS bit = "H" CS bit = "L"
Value Min. - - 100 3 -15 0.5 VCC x 0.7 - -1.0 -1.0 0 -100 -1.0 -100 - VCC - 0.4 - - - 1.0 - 1.0 - - - - - - - Typ. 3.5 (4.0) 0.1*2 - - - - - - - - - - - - - - - - - - - - - -6.0 -1.5 6.0 1.5 3 10 10 Max. - 10 2500 40 +2 VCC - VCC x 0.3 +1.0 +1.0 +100 0 +1.0 0 0.4 - 0.4 - 0.4 2.5 - -1.0 - - - - - - - -
Unit mA A MHz MHz dBm Vp-p V
Input sensitivity
A A A V V V nA mA mA
IIH*4
*4
VOL VOH VOL VDOH VDOL IOFF IOL IOH IOL IDOH*4
R, "L" level output voltage LD/fout "H" level output voltage "L" level output voltage High impedance cutoff current "L" level output current "H" level output current Do Do P
VCC = VP = 3.0 V, IDOH = -0.5 mA VP - 0.4
R, "L" level output current LD/fout "H" level output current Do "L" level output current
mA
IDOL
IDOL/IDOH IDOMT*5 VDO = VP/2 Charge pump current rate vs VDO vs Ta IDOVD*6 0.5 V VDO VP - 0.5 V IDOTA*7 - 40C Ta +85C
% % %
6
MB15E07SL
*1: *2: *3: *4: *5: *6: *7: Conditions; fosc = 12 MHz, Ta = +25C, in locking state. VCC = VP = 3.0 V, fosc = 12.8 MHz, Ta = +25C, in power saving mode AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency. The symbol "-" (minus) means direction of current flow. VCC = VP = 3.0 V, Ta = +25C (|I3| - |I4|) / [(|I3| + |I4|) /2] x 100(%) VCC = VP = 3.0 V, Ta = +25C [(|I2| - |I1|) /2] / [(|I1| + |I2|) /2] x 100(%) (Applied to each IDOL, IDOH) VCC = VP = 3.0 V, VDO = VP/2 (|IDO(85C) - IDO(-40C)| /2) / (|IDO(85C) + IDO(-40C)| /2) x 100(%) (Applied to each IDOL, IDOH)
I1 IDOL
I3 I2
IDOH
I2
I4 I1 0.5 Vp/2 Vp - 0.5 V Vp
Charge Pump Output Voltage (V)
7
MB15E07SL
s FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation: fVCO = [(M x N) + A] x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) M : Preset divide ratio of modulus prescaler (32 or 64)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
Control bit (CNT) H L (1) Shift Register Configuration Programmable Reference Counter LSB Data Flow 1 C N T 2 R 1 3 R 2 4 R 3 5 R 4 6 R 5 7 R 6 8 R 7 9 R 8 10 R 9 11 R 10 12 R 11 13 R 12 14 R 13 15 R 14 16 17 18 19 MSB Destination of serial data For the programmable reference divider For the programmable divider
SW
FC LDS CS
CNT R1 to R14 SW FC LDS CS
: Control bit : Divide ratio setting bit for the programmable reference counter (3 to 16,383) : Divide ratio setting bit for the prescaler (32/33 or 64/65) : Phase control bit for the phase comparator : LD/fOUT signal select bit : Charge pump current select bit
[Table 1] [Table 2] [Table 5] [Table 8] [Table 7] [Table 6]
Note: Start data input with MSB first.
8
MB15E07SL
Programmable Counter LSB 1 C N T 2 A 1 3 A 2 4 A 3 5 A 4 6 A 5 7 A 6 8 A 7 MSB Data Flow 9 N 1 10 N 2 11 N 3 12 N 4 13 N 5 14 N 6 15 N 7 16 N 8 17 N 9 18 N 10 19 N 11
CNT : Control bit N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) Note: Data input with MSB first.
[Table 1] [Table 3] [Table 4]
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 3 4 16383 R 14 0 0 1 R 13 0 0 1 R 12 0 0 1 R 11 0 0 1 R 10 0 0 1 R 9 0 0 1 R 8 0 0 1 R 7 0 0 1 R 6 0 0 1 R 5 0 0 1 R 4 0 0 1 R 3 0 1 1 R 2 1 0 1 R 1 1 0 1
Note: * Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) 3 4 2047 N 11 0 0 1 N 10 0 0 1 N 9 0 0 1 N 8 0 0 1 N 7 0 0 1 N 6 0 0 1 N 5 0 0 1 N 4 0 0 1 N 3 0 1 1 N 2 1 0 1 N 1 1 0 1
Note: * Divide ratio less than 3 is prohibited.
9
MB15E07SL
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio (A) 0 1 127 A 7 0 0 1 A 6 0 0 1 A 5 0 0 1 A 4 0 0 1 A 3 0 0 1 A 2 0 0 1 A 1 0 1 1
Table 5. Prescaler Data Setting
SW H L Prescaler divide ratio 32/33 64/65
Table 6. Charge Pump Current Setting
CS H L Current value 6.0 mA 1.5 mA
Table 7. LD/fout Output Select Data Setting
LDS H L fout signal LD signal LD/fOUT output signal
(2) Relation between the FC Input and Phase Characteristics The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the phase comparator output (R, P) are reversed according to the FC bit. Also, the monitor pin (fOUT) output is controlled by the FC bit. The relationship between the FC bit and each of DO, R, and P is shown below.
Table 8. FC Bit Data Setting (LDS = "H")
FC = High DO fr > fP fr < fP fr = fP H L Z* R L H L P L Z* Z* fout = fr LD/fout DO L H Z* H L L FC = Low R P Z* L Z* fout = fp LD/fout
* : High impedance
10
MB15E07SL
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
* : When the LPF and VCO characteristics are similar to (1), set FC bit high. * : When the VCO characteristics are similar to (2), set FC bit low.
(1)
VCO Output Frequency
PLL
LPF
VCO
(2)
LPF Output Voltage
3. Do Output Control Table 9. ZC Pin Setting
ZC pin H L Normal output High impedance Do output
4. Power Saving Mode (Intermittent Mode Control Circuit) Table 10. PS Pin Setting
PS pin H L Normal mode Power saving mode Status
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the signal PLL, the lock detector, LD, remains high, indicating a locked condition. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Note: When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 s.
11
MB15E07SL
Note: * PS pin must be set "L" for Power-ON.
OFF tV 1 s
ON
VCC Clock Data LE
tPS 100 nS PS (1) (2) (3)
(1) PS = L (power saving mode) at Power ON (2) Set serial data 1 s later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS: L H) 100 nS later after setting serial data.
12
MB15E07SL
s SERIAL DATA INPUT TIMING
1st data Control bit Data MSB Clock LSB Invalid data
2nd data
t1 t7 LE
t2
t3 t6 t4 t5
On the rising edge of the clock, one bit of data is transferred into the shift register. Parameter t1 t2 t3 t4 Min. 20 20 30 30 Typ. - - - - Max. - - - - Unit ns ns ns ns Parameter t5 t6 t7 Min. 100 20 100 Typ. - - - Max. - - - Unit ns ns ns
Note: LE should be "L" when the data is transferred into the shift register.
13
MB15E07SL
s PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[FC = "H"]
DO
[FC = "L"]
DO
Notes: 1. Phase error detection range: -2 to +2 2. Pulses on Do signal during locked state are output to prevent dead zone. 3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. 4. tWU and tWL depend on OSCIN input frequency. tWU > 2/fosc (s) (e. g. tWU > 156.3 ns, fosc = 12.8 MHz) tWU < 4/fosc (s) (e. g. tWL < 312.5 ns, fosc = 12.8 MHz) 5. LD becomes high during the power saving mode (PS = "L").
14
MB15E07SL
s MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
1000 pF 1000 pF S*G 50 fin 8 Xfin GND 7 6 DO 5 VCC 4 VP OSCOUT OSCIN 3 2 1 50 0.1 F 0.1 F 1000 pF S*G
9
10
11
12 PS VCC
13
14
15
16 R Oscilloscope
Clock Data LE Controller (setting divide ratio)
Note: SSOP-16
ZC LD/fout P
15
MB15E07SL
s TYPICAL CHARACTERISTICS
1. fin input impedance
Input sensitivity - Input frequency (Prescaler: 64/65) 20 10 0 -10 -20 -30 -40 -50 0 200 400 600 800
Ta = +25 C
Input sensitivity Pfin (dBm)
,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,
SPEC VCC = 2.4 V VCC = 3.0 V VCC = 3.6 V 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 Input frequency fin (MHz)
Input sensitivity - Input frequency (Prescaler: 32/33) 10 0 Input sensitivity Pfin (dBm) -10 -20 -30 -40 -50 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200
,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,
SPEC 2400
Ta = +25 C
VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 2600 2800 3000
Input frequency fin (MHz)
16
MB15E07SL
2. OSCIN input frequency
10 Input sensitivity VOSC (dBm) 0 -10 -20 -30 -40 -50 -60
,,,,,, ,,,,,,
SPEC
Input sensitivity - Input frequency
Ta = +25 C
VCC = 2.4 V VCC = 3.0 V VCC = 3.6 V 0 50 100 Input frequency fOSC (MHz) 150 200
17
MB15E07SL
3. Do output current 1.5 mA mode
VDO - IDO Ta = +25C VCC = 3.0 V Vp = 3.0 V
10.00
Charge pump output current IDO (mA)
2.000 /div
IDOL
0
IDOH
-10.00 0 .6000/div Charge pump output voltage VDO (V) 4.800
6.0 mA mode
VDO - IDO Ta = +25C VCC = 3.0 V Vp = 3.0 V IDOL 2.000 /div
10.00
Charge pump output current IDO (mA)
0
IDOH
-10.00 0 .6000/div Charge pump output voltage VDO (V) 4.800
18
MB15E07SL
4. fin input impedance
1 : 12.646 -57.156 1 GHz 2 : 22.156 -12.136 1.5 GHz 4 3 : 33.805 11.869 2 GHz 4 : 23.715 8.9629 2.5 GHz
3 2
1 START 500.000 000 MHz STOP 2 500.000 000 MHz
5. OSCIN input impedance
1:
9.917 -3.643 3 MHz
2 : 3.7903 -4.812 10 MHz 3: 4 1.574 -3.4046 20 MHz
3 2 1 4 : 453.12 -1.9213 40 MHz
START
1.000 000 MHz
STOP
50.000 000 MHz
19
MB15E07SL
s REFERENCE INFORMATION
Test Circuit S.G OSCIN fin Do LPF fVCO = 810.45 MHz KV = 17 MHz/V fr = 25 kHz fOSC = 14.4 MHz LPF VCC =VP = 3.0 V VVCO = 2.3 V Ta = +25 C CP : 6 mA mode 9.1 k
Spectrum Analyzer
4700 pF VCO
4.2 k 0.047 F
1500 pF
PLL Reference Leakage
REF -5.0 dBm 10 dB/
ATT 10 dB
MKR
25.0 kHz -78.0 dB
RBW 1 kHz SAMPLE VBW 1 kHz
SWP 1.0 s
SPAN 200 kHz
CENTER 810.000 MHz
PLL Phase Noise
REF -5.0 dBm 10 dB/
ATT 10 dB
MKR
2.28 kHz -53.1 dB
RBW 100 Hz SAMPLE VBW 100 Hz
SWP 10 s
SPAN 20.0 kHz
CENTER 810.000 MHz
(Continued)
20
MB15E07SL
(Continued)
PLL Lock Up time 810 MH826 MHz within 1 KHz LchHch 1.30 ms 846.000 MHz
PLL Lock Up time 826 MH810 MHz within 1 KHz HchLch 1.28 ms 838.000 MHz
826.000 MHz
818.000 MHz
806.000 MHz 500.0 s/div
798.000 MHz 500.0 s/div 810.004000MHz
826.004000 MHz
826.000000 MHz
810.000000MHz
825.996000 MHz 500.0 s/div
809.996000MHz 500.0 s/div
21
MB15E07SL
s APPLICATION EXAMPLE
VP 10 k 12 k 12 k LPF VCO
OUTPUT
10 k Lock Det. From a controller
R 16
P 15
LD/fout 14
ZC 13
PS 12
LE 11
Data 10
Clock 9
MB15E07SL
1 OSCIN
2 OSCOUT
3 VP
4 VCC
5 DO
6 GND
7 Xfin
8 fin 1000 pF
1000 pF 1000 pF TCXO 0.1 F 0.1 F
VP: 5.5 V Max Notes: 1. SSOP-16 2. In case of using a crystal resonator, it is necessary to optimize matching between the crystal and this LSI, and perform detailed system evaluation. It is recommended to consult with a supplier of the crystal resonator. (Reference oscillator circuit provides its own bias, feedback resistor is 100 k (typ).)
22
MB15E07SL
s USAGE PRECAUTIONS
To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting device into or removing device from a socket. -Protect leads with a conductive sheet when transporting a board-mounted device.
s ORDERING INFORMATION
Part number MB15E07SLPFV1 MB15E07SLPV1 Package 16-pin, Plastic SSOP (FPT-16P-M05) 16-pad, Plastic BCC (LCC-16P-M06) Remarks
23
MB15E07SL
s PACKAGE DIMENSIONS
16-pin plastic SSOP (FPT-16P-M05)
* : These dimensions do not include resin protrusion.
* 5.000.10(.197.004)
1.25 -0.10 .049 -.004
+0.20 +.008
(Mounting height)
0.10(.004)
INDEX
* 4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 .009
+0.10 +.004 -.002
"A"
0.15 -0.02 .006 -.001
+0.05 +.002
Details of "A" part 0.100.10(.004.004) (STAND OFF)
4.55(.179)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in mm (inches)
(Continued)
24
MB15E07SL
(Continued)
16-pad plastic BCC (LCC-16P-M06)
4.550.10 (.179.004)
14 9
0.80(.031)MAX Mounting height 0.400.10 (.016.004) 0.80(.031) REF 0.65(.026) TYP
9
3.40(.134)TYP 0.3250.10 (.013.004)
14
INDEX AREA 3.400.10 (.134.004) 2.45(.096) TYP "A" "B" 1.15(.045) REF
1
6
0.0750.025 (.003.001) (Stand off)
6
1.725(.068) REF
1
Details of "A" part 0.750.10 (.030.004) 0.05(.002)
Details of "B" part 0.600.10 (.024.004)
0.400.10 (.016.004)
0.600.10 (.024.004)
C
1999 FUJITSU LIMITED C16017S-1C-1
Dimensions in mm (inches)
25
MB15E07SL
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9904 (c) FUJITSU LIMITED Printed in Japan
26

▲Up To Search▲

Price & Availability of MB15E07SL

	To Download MB15E07SL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .