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INTEGRATED CIRCUITS
PCA9556 Octal SMBus Registered Interface
Product specification 1998 Dec 18
Philips Semiconductors
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
FEATURES
* SMBus compliance with fixed 3.3V voltage levels * Operating power supply voltage range of 3.0V - 3.6V * Active high polarity inverter register * Write protect register * Active low reset pin * Low leakage current on power-down * Noise filter on SCL/SDA inputs * No glitch on power-up * Internal power-on reset * 8 I/O pins which default to 8 inputs * High impedance open drain on I/O
DESCRIPTION
The PCA9556 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus applications. The PCA9556 consists of an 8-bit input port register, 8-bit output port register, and an SMBus interface. It has low current consumption and a high impedance open drain output pin, I/O0. The SMBus system master can reset the PCA9556 in the event of a timeout by asserting a LOW on the reset input. The SMBus system master can also invert the PCA9556 inputs by writing to their active HIGH polarity inversion bits. Finally, the SMBus system master can enable the PCA9556's I/Os as either inputs or outputs by writing to their I/O configuration bits. The power-on reset sets the registers to their default values and initializes the SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
PIN CONFIGURATION
SCL 1 SDA 2 16 VDD 15 RESET 14 I/O7 13 I/O6 12 I/O5 11 I/O4 10 I/O3 9 I/O2
A0 3 A1 4 A2 5 I/O0 6 I/O1 7 VSS 8
su01045
Figure 1. Pin configuration
PIN DESCRIPTION
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL SCL SDA A0 A1 A2 I/O0 I/O1 VSS I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 RESET VDD FUNCTION Serial clock line Serial data line Address input 0 Address input 1 Address input 2 I/O0 (open drain) I/O1 Supply GROUND I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 External reset (active LOW) Supply voltage
ORDERING INFORMATION
PACKAGES 16-Pin Plastic TSSOP16 Type I TEMPERATURE RANGE 0C to +70C OUTSIDE NORTH AMERICA PCA9556 PW DRAWING NUMBER SOT403-1
1998 Dec 18
2
853-2138 20549
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
BLOCK DIAGRAM
A0 A1 A2 SCL SDA INPUT FILTER 8-BIT INPUT/ OUTPUT PORTS I/O0 I/O1 I/O2 SMBUS CONTROL I/O3 I/O4 I/O5 I/O6 I/O7 POWERON RESET
WRITE pulse READ pulse VDD VSS RESET
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
su01046
Figure 2. Block diagram
REGISTERS Command Byte
Command 0 1 2 3 Protocol Read byte Read/write byte Read/write byte Read/write byte Function Input port register Output port register Polarity inversion register I/O configuration register
Register 2 - Polarity Inversion Register
bit
default
N7
1
N6
1
N5
1
N4
1
N3
0
N2
0
N1
0
N0
0
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read.
This register enables polarity inversion of pins defined as inputs by register 3. If a bit in this register is set (written with `1'), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a `0'), the corresponding port pin's original polarity is retained.
Register 3 - Input/Output Configuration Register
bit C7
1
C6
1
C5
1
C4
1
C3
1
C2
1
C1
1
C0
1
Register 0 - Input Port Register
I7 I6 I5 I4 I3 I2 I1 I0 This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by register 3. Writes to this register have no effect.
default
This register configures the directions of the I/O pins. If a bit in this register is set (written with `1'), the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is cleared (written with `0'), the corresponding port pin is enabled as an output.
Register 1 - Output Port Register
bit
default O7 0 O6 0 O5 0 O4 0 O3 0 O2 0 O1 0 O0 0
RESET Power-on Reset
When power is applied to VDD, an internal power-on reset holds the PCA9556 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9556 registers and SMBus state machine will initialize to their default states.
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by register 3. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin value.
External Reset
A reset can be accomplished by holding the RESET pin low for a minimum of TW. The PCA9556 registers and SMBus state machine will be held in their default state until the RESET input is once again high. This input contains an internal pull-up, therefore, it may be left open if not used.
1998 Dec 18
3
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
SIMPLIFIED SCHEMATIC OF I/O0
DATA FROM SHIFT REGISTER INPUT/OUTPUT MASK REGISTER DATA FROM SHIFT REGISTER D FF WRITE MASK PULSE CK Q Q WRITE REGISTER D FF I/O0 WRITE PULSE CK Q ESD PROTECTION DIODE Q OUTPUT PORT REGISTER DATA
READ REGISTER D FF READ PULSE CK Q Q
VSS
INPUT PORT REGISTER DATA
POLARITY REGISTER DATA FROM SHIFT REGISTER WRITE POLARITY PULSE D FF CK Q Q POLARITY REGISTER DATA
NOTE: ON POWER-UP OR RESET, ALL REGISTERS RETURN TO DEFAULT VALUES
su01047
Figure 3. Simplified schematic of I/O0
1998 Dec 18
4
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
SIMPLIFIED SCHEMATIC OF I/O1 TO I/O7
DATA FROM SHIFT REGISTER INPUT/OUTPUT MASK REGISTER DATA FROM SHIFT REGISTER D FF WRITE MASK PULSE CK Q Q WRITE REGISTER D FF I/O1 TO I/O7 WRITE PULSE CK Q ESD PROTECTION DIODE Q ESD PROTECTION DIODE OUTPUT PORT REGISTER DATA VDD
READ REGISTER D FF READ PULSE CK Q Q
VSS
INPUT PORT REGISTER DATA
POLARITY REGISTER DATA FROM SHIFT REGISTER WRITE POLARITY PULSE NOTE: ON POWER-UP OR RESET, ALL REGISTERS RETURN TO DEFAULT VALUES D FF CK Q Q POLARITY REGISTER DATA
su01055
Figure 4. Simplified schematic of I/O1 to I/O7
1998 Dec 18
5
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
SMBus Address
slave address
0
0
1
1
A2
A1
A0 R/W
fixed
programmable
su01048
Figure 5. PCA9556 address
SMBus Transactions
Data is transmitted to the PCA9556 registers using Write Byte transfers (see Figures 6 and 7). Data is read from the PCA9556 registers using Read and Receive Byte transfers (see FIgures 8 and 9).
SCL
1
2
3
4
5
6
7
8
9 command byte
slave address
data to port
SDA
S
0
0
1
1
A2
A1
A0
0 R/W
A
0
0
0
0
0
0
0
1
A acknowledge from slave
DATA 1
A acknowledge from slave
start condition
acknowledge from slave
WRITE TO PORT
DATA OUT FROM PORT tpv
DATA 1 VALID
su01049
Figure 6. WRITE to output port register via Write Byte Protocol
SCL
1
2
3
4
5
6
7
8
9
slave address
command byte
data to register
SDA
S
0
0
1
1
A2
A1
A0
0 R/W
A
0
0
0
0
0
0
1
1/0
A acknowledge from slave
DATA
A acknowledge from slave
start condition
acknowledge from slave
su01050
Figure 7. WRITE to I/O configuration or polarity inversion registers via Write Byte Protocol
1998 Dec 18
6
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
slave address
acknowledge from slave
acknowledge from slave
slave address
acknowledge from slave
data from register
acknowledge from master
S
0
0
1
1
A2 A1 A0
0 R/W
A
COMMAND BYTE
A
S
0
0
1
1
A2 A1 A0
1 R/W
A
DATA first byte
A
at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter data from register no acknowledge from master
DATA last byte
NA
P
su01052
Figure 8. READ from register via Read byte protocol
slave address
data from port
data from port
SDA
S
0
0
1
1
A2
A1
A0
1 R/W
A acknowledge from slave
DATA 1
A acknowledge from master
DATA 4
NA
P stop condition
start condition
no acknowledge from master
READ FROM PORT
DATA INTO PORT tph
DATA 2
DATA 3 tps
DATA 4
Notes: 1. This figure assumes the command byte has previously been programmed with 00h. 2. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost.
su01051
Figure 9. READ input port register via Receive byte protocol
1998 Dec 18
7
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER VDD Supply voltage VI Input voltage II DC input current VI/O DC voltage on an I/O as an input other than I/O0 VI/O0 DC voltage on I/O0 as an input II/O0 II/O IDD ISS Ptot PO Tstg Tamb DC in ut current on I/O0 input DC output current on an I/O Supply current Supply current Total power dissipation Power dissipation per output Storage temperature range Operating ambient temperature CONDITIONS MIN -0.5 VSS - 0.5 - VSS - 0.5 VSS - 0.5 - - - - - - - -65 0 MAX +4.6 VDD + 0.5 20 VDD + 0.5 4.6 +400 -20 20 UNIT V V mA V V A mA mA mA mA mW mW C C
+150 +70
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under "Handling MOS devices".
DC CHARACTERISTICS
VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = 0 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS Supplies VDD Supply voltage Operating mode; VDD = 3.3 V; no load; VI = VDD or VSS; IDD Supply current fSCL = 100 kHz Standby mode; VDD = 3.3 V Istb Standby current no load; VI = VDD or VSS VDD = 3.3 V VPOR Power-on reset voltage no load; VI = VDD or VSS; note 1 input SCL; input/output SDA VIL LOW level input voltage VIH HIGH level input voltage IOL LOW level output current VOL = 0.4V IL Leakage current VI = VDD = VSS CI Input capacitance VI = VSS I/Os VIL LOW level input voltage VIH HIGH level input voltage Maximum allowed input current through IIHL(max) VI VDD or VI VSS protection diode (I/O1 - I/O7) IOL LOW level output current VOL = 0.55V; VDD = 3.3V HIGH level output current except I/O0 VOH = 2.4V; VDD = 3.3V VDD = 3.6V; VOH = 4.6V IOH HIGH level out ut current on I/O0 output VDD = 0V; VOH = 3.3V IL Input leakage current VDD = 3.6V; VI = 0 or VDD CI Input capacitance CO Output capacitance Select Inputs A0, A1, A2, and RESET VIL LOW level input voltage VIH HIGH level input voltage ILI Input leakage current
MIN 3.0
TYP
MAX 3.6
UNIT V A A V V V mA A pF V V A mA mA A A pF pF V V A
300 25 1.3 -0.5 2.1 3 -1 - -0.5 2.0 - 8 4 - - - 10 - - - - -
425 50 2.4 0.8 VDD + 0.5 - +1 10 0.8 VDD + 0.5 400 - 1 1 1 10 10 0.8 VDD + 0.5 1
-1 - - -0.5 2.0 -1
NOTE: 1. The power-on reset circuit resets the SMBus logic with VDD < VPOR and sets all I/Os to their default values
1998 Dec 18
8
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
AC SPECIFICATIONS
SYMBOL FSBM TBUF THO:STA TSU:STA THO:DAT TSU:DAT TLOW THIGH TF TR Port Timing TPV TPS TPH Reset TW Reset pulse width 2 ns Output data valid Input data setup time Input data hold time 0 4 4 s s s PARAMETER SMB operating frequency Bus free time between stop and start conditions Hold time after (repeated) start condition Repeated start condition setup time Data hold time Data setup time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time LIMITS MIN 10 4.7 4.0 4.7 300 250 4.7 4.0 300 1000 MAX 100 UNITS KHz s s s ns ns s s ns ns
1998 Dec 18
9
Philips Semiconductors
Product specification
Octal SMbus Registered Interface
PCA9556
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 Dec 18
10
Philips Semiconductors
Product specification
Octal SMbus Registered Interface
PCA9556
NOTES
1998 Dec 18
11
Philips Semiconductors
Product specification
Octal SMbus Registered Interface
PCA9556
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 04-99 Document order number: 9397 750 04974
Philips Semiconductors
1998 Dec 18 12

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