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PRODUCT OVERVIEW
S3C7515/P7515
1
OVERVIEW
PRODUCT OVERVIEW
The S3C7515/P7515 single-chip CMOS microcontroller has been designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The S3P7515 is a microcontroller which has 16-kbyte one-time-programmable EPROM but its functions are same to S3C7515. With its DTMF generator, 8-bit serial I/O interface, and versatile 8-bit timer/counters, the S3C7515/P7515 offers an excellent design solution for a wide variety of telecommunication applications. Up to 55 pins of the 64-pin SDIP or QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the S3C7515/P7515's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
DEVELOPMENT SUPPORT0
The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for S3C7-series microcontrollers that is powerful, reliable, and portable. In addition to its window-based program development structure, the SMDS tool set includes versatile debugging, trace, instruction timing, and performance measurement applications. The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard hex files that also contain program control data for SMDS compatibility.
S MSUN G
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ELECTRONICS
S3C7515/P7515
PRODUCT OVERVIEW
FEATURES SUMMARY
Memory -- 512 x 4-bit RAM -- 16,384 x 8-bit ROM 55 I/O Pins -- Input only: 4 pins -- I/O: 43 pins -- N-channel open-drain I/O: 8 pins Memory-Mapped I/O Structure -- Data memory bank 15 DTMF Generator -- 16 dual-tone frequencies for tone dialing 8-bit Basic Timer -- 4 interval timer functions Two 8-bit Timer/Counters -- Programmable interval timer -- External event counter function -- Timer/counters clock outputs to TCLO0 and TCLO1 pins External clock signal divider Serial I/O interface clock generator Watch Timer -- Time interval generation: 0.5 s, 3.9 ms at 32.768 kHz -- 4 frequency outputs to the BUZ pin Operating Voltage Range 8-bit Serial I/O Interface -- 8-bit transmit/receive mode -- 8-bit receive mode -- LSB-first or MSB-first transmission selectable Package Types -- 64 SDIP, 64 QFP -- 2.0 V to 5.5 V Operating Temperature -- - 40 C to 85 C Instruction Execution Times -- 0.67, 1.33, 10.7 s at 6.0 MHz -- 1.12, 2.23, 17.88 s at 3.579545 MHz -- 122 s at 32.768 kHz Oscillation Sources -- Crystal, ceramic for main system clock -- Crystal oscillator for subsystem clock -- Main system clock frequency: 3.579545 MHz (typical) -- Subsystem clock frequency: 32.768 kHz (typical) -- CPU clock divider circuit (by 4, 8, or 64) Bit Sequential Carrier -- Supports 8-bit serial data transfer in arbitrary format Interrupts -- 3 external interrupt vectors -- 4 internal interrupt vectors -- 2 quasi-interrupts Power-Down Modes -- Idle: Only CPU clock stops -- Stop: System clock stops
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PRODUCT OVERVIEW
S3C7515/P7515
FUNCTION OVERVIEW
SAM47 CPU All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles. CPU REGISTERS Program Counter A 14-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the PC is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not increment the PC is the 1-byte REF instruction which references instructions stored in a look-up table in the ROM. Whenever a reset operation or an interrupt occurs, bits PC13 through PC0 are set to the vector address. Stack Pointer An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in general-purpose data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logic zero. During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction is executed. The stack pointer can access the stack despite data memory access enable flag status. Since the reset value of the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This sets the first register of the stack area to data memory location 0FFH. PROGRAM MEMORY In its standard configuration, the 16,384 x 8-bit ROM is divided into four areas: -- 16-byte area for vector addresses -- 16-byte general-purpose area (0010-001FH) -- 96-byte instruction reference area -- 16,256-byte area for general-purpose program memory The vector address area is used mostly during reset operations and interrupts. These 16 bytes can alternately be used as general-purpose ROM. The REF instruction references 2 x 1-byte or 2-byte instructions stored in reference area locations 0020H- 007FH. REF can also reference three-byte instructions such as JP or CALL. So that a REF instruction can reference these instructions, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused locations in the REF instruction look-up area can be allocated to general-purpose use.
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S3C7515/P7515
PRODUCT OVERVIEW
DATA MEMORY Overview The 512 x 4 bit data memory has four areas: -- 32 x 4-bit working register area -- 224 x 4-bit general-purpose area in bank 0 which is also used as the stack area -- 256 x 4-bit general-purpose area in bank 1 -- 128 x 4-bit area in bank 15 for memory-mapped I/O addresses The data memory area is also organized as three memory banks -- bank 0, bank 1, and bank 15. You use the select memory bank instruction (SMB) to select one of the banks as working data memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable. After a hardware reset, data memory initialization values must be defined by program code. Data Memory Addressing Modes The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When the EMB flag is logic zero, only locations 00H-7FH of bank 0 and bank 15 can be accessed. When the EMB flag is set to logic one, all three data memory banks can be accessed based on the current SMB value. Working Registers The RAM's working register area in data memory bank 0 is also divided into four register banks. Each register bank has eight 4-bit registers. Paired 4-bit registers are 8-bit addressable. Register A can be used as a 4-bit accumulator and double register EA as an 8-bit extended accumulator; double registers WX, WL, and HL are used as address pointers for indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for main programs and banks 1, 2, and 3 for interrupt service routines. Bit Sequential Carrier The bit sequential carrier (BSC) mapped in data memory bank 15 is a 8-bit general register that you can manipulate using 1-, 4-, and 8-bit RAM control instructions. Using the BSC register, addresses and bit locations can be specified sequentially using 1-bit indirect addressing instructions. In this way, a program can generate 8-bit data output by moving the bit location sequentially, incrementing or decrementing the value of the L register. You can also use direct addressing to manipulate data in the BSC.
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PRODUCT OVERVIEW
S3C7515/P7515
CONTROL REGISTERS Program Status Word The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also used to restore a program's execution environment when an interrupt has been serviced. Program instructions can always address the PSW regardless of the current value of data memory access enable flags. Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is completed, PSW values are restored. IS1 C IS0 SC2 EMB SC1 ERB SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0-SC2) can be addressed using 8-bit read instructions only. Select Bank (SB) Register Two 4-bit locations called the SB register store address values used to access specific memory and register banks: the select memory bank register, SMB, and the select register bank register, SRB. 'SMB n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data memory address in the SMB register. The 'SRB n' instruction is used to select register bank 0, 1, 2, or 3, and to store the address data in the SRB. The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and subroutines. CLOCK CIRCUITS Main system and subsystem oscillation circuits generate the internal clock signals for the CPU and peripheral hardware. The main system clock can use a crystal, ceramic, or RC oscillation source, or an externally-generated clock signal. The subsystem clock requires either a crystal oscillator or an external clock source. Bit settings in the 4-bit power control and system clock mode registers select the oscillation source, the CPU clock, and the clock used during power-down mode. The internal system clock signal (fxx) can be divided internally to produce three CPU clock frequencies -- fxx/4, fxx/8, or fxx/64. INTERRUPTS Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or externally by peripheral devices (INT0, INT1, and INT4). There are two quasi-interrupts: INT2 and INTW. INT2/KS0-KS7 detects rising/falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91 milliseconds at the watch timer clock frequency of 32.768 kHz. The following components support interrupt processing: -- Interrupt enable flags -- Interrupt request flags -- Interrupt priority registers -- Power-down termination circuit
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S3C7515/P7515
PRODUCT OVERVIEW
POWER-DOWN To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle mode and the STOP instruction initiates stop mode. In idle mode, only the CPU clock stops while peripherals and the oscillation source continue to operate normally. Stop mode effects only the main system clock -- a subsystem clock, if used, continues oscillating. In stop mode, main system clock oscillation stops completely, halting all operations except for a few basic peripheral functions. RESET or an interrupt (with the exceptions of INT0) can be used to terminate either idle or stop mode. RESET When a RESET signal occurs during normal operation or during power-down mode, the CPU enters idle mode when the reset operation is initiated. When the standard oscillation stabilization interval (36.6 ms at 3.579545 MHz) has elapsed, normal CPU operation resumes. I/O PORTS The S3C7515/P7515 has 14 I/O ports. Pin addresses for all I/O ports are mapped in bank 15 of the RAM. There are 4 input pins, 43 configurable I/O pins, and 8 n-channel open-drain I/O pins, for a total of 55 I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. TIMERS and TIMER/COUNTERS The timer function has four main components: an 8-bit basic interval timer, two 8-bit timer/counters, and a watch timer. The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected CPU clock frequency. The programmable 8-bit timer/counters are used for external event counting, generation of arbitrary clock frequencies for output, and dividing external clock signals. The 8-bit timer/counter 0 generates a clock signal (SCK) for the serial I/O interface. The watch timer has an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Its functions include real-time and watch-time measurement, and frequency outputs for buzzer sound. SERIAL I/O INTERFACE The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The serial interface has the following functional components: -- 8-bit mode register -- Clock selector circuit -- 8-bit buffer register -- 3-bit serial clock counter The serial I/O circuit can be set either to transmit-and-receive or to receive-only mode. MSB-first or LSB-first transmission is also selectable. The serial interface operates with an internal or an external clock source, or using the clock signal generated by the 8-bit timer/counter 0. To modify transmission frequency, the appropriate bits in the serial I/O mode register (SMOD) must be manipulated.
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PRODUCT OVERVIEW
S3C7515/P7515
BLOCK DIAGRAM
INT0, INT1, INT2, INT4 8-BIT TIMER/ COUNTER 0 8-BIT TIMER/ COUNTER 1
P6.0-P6.3 / KS0-KS3 P7.0-P7.3 / KS4-KS7 P8.0-P8.3 P9.0-P9.3
RESET
Xin XTin
Xout XTout
BASIC TIMER
WATCH TIMER
I/O PORT 0 INTERRUPT CONTROL BLOCK CLOCK STACK POINTER SERIAL I/O PORT PROGRAM COUNTER INPUT PORT 1
P0.0 / SCK P0.1 / SO P0.2 / SI P0.3 / BTCO
I/O PORT 6 I/O PORT 7
INTERNAL INTERRUPTS INSTRUCTION DECODER
P1.0 / INT0 P1.1 / INT1 P1.2 / INT2 P1.3 / INT4 P2.0 / TCLO0 P2.1 / TCLO1 P2.2 / CLO P2.3 / BUZ P3.0 / TCL0 P3.1 / TCL1 P3.2 P3.3 P4.0-P4.3
I/O PORT 8 I/O PORT 9 ARITHMETIC AND LOGIC UNIT
PROGRAM STATUS WORD
I/O PORT 2
FLAGS
I/O PORT 3
P10.0-P10.3 P11.0-P11.3
I/O PORT 10 I/O PORT 11 I/O PORT 12 I/O PORT 13 I/O PORT 4 I/O PORT 5 512 x 4-BIT DATA MEMORY 16 K BYTE PROGRAM MEMORY DTMF GENERATOR
P12.0-P12.3
P5.0-P5.3
P13.0-P13.2
DTMF
Figure 1-1. S3C7515/P7515 Simplified Block Diagram
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S3C7515/P7515
PRODUCT OVERVIEW
PIN ASSIGNMENTS
P1.3 / INT4 P1.2 / INT2 P1.1 / INT1 P1.0 / INT0 P13.2 P13.1 P13.0 P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P0.3 / BTCO P0.2 / SI P0.1 / SO P0.0 / SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P12.0 P3.3 P3.2 TEST DTMF VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS P9.0 P9.1 P9.2 P9.3 P8.0 P8.1 P8.2 P8.3 P7.0 / KS4 P7.1 / KS5 P7.2 / KS6 P7.3 / KS7 P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / KS3 XTout XTin Xin Xout RESET P5.0 P5.1 P5.2 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0 / TCL0 P3.1 / TCL1
Figure 1-2. 64-SDIP Pin Assignment Diagrams
(64-SDIP-750)
S3C7515
1-9
1-10 P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P0.3 / BTCO P0.2 / SI P0.1 / SO P0.0 / SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 P8.0 P9.3 P9.2 P9.1 P9.0 VSS P1.3 / INT4 P1.2 / INT2 P1.1 / INT1 P1.0 / INT0 P13.2 P13.1 P13.0 52 53 54 55 56 57 58 59 60 61 62 63 64
PRODUCT OVERVIEW
S3C7515
(64-QFP-1420F)
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
Figure 1-2. 64-QFP Pin Assignment Diagrams (Continued)
P5.3 P4.0 P4.1 P4.2 P4.3 P3.0 / TCL0 P3.1 / TCL1 VDD DTMF TEST P3.2 P3.3 P12.0
P8.1 P8.2 P8.3 P7.0 / KS4 P7.1 / KS5 P7.2 / KS6 P7.3 / KS7 P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / KS3 XTout XTin Xin Xout RESET P5.0 P5.1 P5.2
S3C7515/P7515
S3C7515/P7515
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7515/P7515 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit and 4-bit read and test is possible. 4-bit pull-up resistors are assignable by software to pins P1.0, P1.1, P1.2 and P1.3. Same as port 0. Number 15 (8) 14 (7) 13 (6) 12 (5) Share Pin SCK SO SI BTCO
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3
I
1 (61) 2 (60) 3 (59) 4 (58) 11 (4) 10 (3) 9 (2) 8 (1) 34 (27) 33 (26) 29 (22) 28 (21) 38-35 (31-28) 42-39 (35-32)
INT0 INT1 INT2 INT4 TCLO0 TCLO1 CLO BUZ TCL0 TCL1
I/O
I/O
Same as port 0.
I/O
4-bit I/O ports. N-channel open-drain output up to 9 volts. 1-bit and 4-bit read/write and test is possible. Ports 4 and 5 can be paired to support 8-bit data transfer. 8-bit unit pull-up resistors are assignable by mask option. 4-bit I/O ports. 1-bit or 4-bit read/write and test is possible. Port 6 pins are individually software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins (port 6 only). Ports 6 and 7 can be paired to enable 8-bit data transfer. Same as port 0. 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins.
-
P6.0-P6.3 P7.0-P7.3
I/O
51-48 (44-41) 55-52 (48-45)
KS0-KS3 KS4-KS7
P8.0-P8.3 P9.0-P9.3
I/O I/O
59-56 (52-49) 63-60 (56-53)
- -
*
Parentheses indicate pin number for 64 QFP package.
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PRODUCT OVERVIEW
S3C7515/P7515
Table 1-1. S3C7515/P7515 Pin Descriptions (Continued) Pin Name P10.0-P10.3 P11.0-P11.3 P12.0-P12.3 I/O Pin Type I/O Description Same as port 9. Ports 10 and 11 can be paired to support 8-bit data transfer. 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-down resistors are software assignable; pull-down resistors are automatically disabled for output pins. 3-bit I/O port; characteristics are same as port 9. DTMF output. Serial I/O interface clock signal Serial data output Serial data input Basic timer clock output External interrupts. The triggering edge for INT0 and INT1 is selectable. INT0 is synchronized to system clock. Quasi-interrupt with detection of rising edges External interrupt with detection of rising and falling edges. Timer/counter 0 clock output Timer/counter 1 clock output Clock output 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 32.768 kHz for buzzer sound External clock input for timer/counter 0 External clock input for timer/counter 1 Quasi-interrupt inputs with falling edge detection Number 19-16 (12-9) 23-20 (16-13) 27-24 (20-17) Share Pin -
-
P13.0-P13.2 DTMF SCK SO SI BTCO INT0, INT1
I/O O I/O I/O I/O I/O I
7-5 (64-62) 31 (24) 15 (8) 14 (7) 13 (6) 12 (5) 4, 3 (61, 60) 2 (59) 1 (58) 11 (4) 10 (3) 9 (2) 8 (1)
- - P0.0 P0.1 P0.2 P0.3 P1.0, P1.1
INT2 INT4 TCLO0 TCLO1 CLO BUZ
I I I/O I/O I/O I/O
P1.2 P1.3 P2.0 P2.1 P2.2 P2.3
TCL0 TCL1 KS0-KS3 KS4-KS7
I/O I/O I/O
34 (27) 33 (26) 51-48 (44-41) 55-52 (48-45)
P3.0 P3.1 P6.0-P6.3 P7.0-P7.3
*
Parentheses indicate pin number for 64 QFP package.
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S3C7515/P7515
PRODUCT OVERVIEW
Table 1-1. S3C7515/P7515 Pin Descriptions (Concluded) Pin Name VDD VSS RESET XIN, XOUT Pin Type - - I - Power supply Ground Reset signal Crystal, ceramic, or R/C oscillator signal for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) Crystal oscillator signal for subsystem clock. (For external clock input, use XTIN and input XTIN's reverse phase to XTOUT) No connection (must be connected to VSS) Description Number 32 (25) 64 (57) 43 (36) 45, 44 (38, 37) 46, 47 (39, 40) 30 (23) Share Pin - - - -
XTIN, XTOUT
-
-
NC
-
-
*
Parentheses indicate pin number for 64 QFP package.
1-13
PRODUCT OVERVIEW
S3C7515/P7515
Table 1-2. Overview of S3C7515/P7515 Pin Data Pin Names P0.0-P0.3 P1.0-P1.3 P2.0-P2.3 P3.0-P3.1 P3.2-P3.3 P4.0-P4.3 P5.0-P5.3 P6.0-P6.3 P7.0-P7.3 P8.0-P8.3 P9.0-P9.3 P10.0-P10.3 P11.0-P11.3 P12.0-P12.3 P13.0-P13.2 DTMF XIN, XOUT XTIN, XTOUT RESET NC VDD, VSS Share Pins SCK, SO, SI, BTCO INT0, INT1, INT2, INT4 TCLO0, TCLO1, CLO, BUZ TCL0, TCL1 - - KS0-KS3 KS4-KS7 - - - - - - - - - - I/O Type I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O - I - - Reset Value Input Input Input Input Input
(NOTE)
Circuit Type D-4 A-3 D-2 D-4 D-2 E-6 D-4 D-2 D-2 D-2 D-6 D-2 G-6 - B - -
Input Input Input Input Input Input High impedence - - - -
NOTE: When pull-up resistors are provided: High level When pull-up resistors are not provided: High impedence
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S3C7515/P7515
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
PULL-UP RESISTOR
VDD
P-CHANNEL IN
IN
N-CHANNEL
SCHMITT TRIGGER
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD
PULL-UP RESISTOR PULL-UP RESISTOR ENABLE
IN
P-CHANNEL
IN
SCHMITT TRIGGER
SCHMITT TRIGGER
Figure 1-4. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type B-4
1-15
PRODUCT OVERVIEW
S3C7515/P7515
VDD
VDD
DATA
P-CHANNEL OUT N-CHANNEL
PULL-UP ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE C
P-CHANNEL
I/O
OUTPUT DISABLE
SCHMITT TRIGER
Figure 1-7. Pin Circuit Type C
Figure 1-9. Pin Circuit Type D-4
VDD DATA OUTPUT DISABLE PULL-UP ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE C P-CHANNEL PULL-DOWN ENABLE CIRCUIT TYPE C I/O
N-CHANNEL
I/O
Figure 1-8. Pin Circuit Type D-2
Figure 1-10. Pin Circuit Type D-6
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S3C7515/P7515
PRODUCT OVERVIEW
VDD PULL-UP RESISTOR (MASK OPTION) DATA I/O N-CHANNEL OUTPUT DISABLE
Figure 1-11. Pin Circuit Type E-6
+ OUTPUT DISABLE DTMF OUT
Figure 1-12. Pin Circuit Type G-2
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S3C7515/P7515
ELECTRICAL DATA
14
-- I/O capacitance
ELECTRICAL DATA
In this section, information on S3C7515 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- System clock oscillator characteristics
-- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at Xin and Xout -- TCL timing -- Input timing for RESET -- Input timing for external interrupts -- Serial data transfer timing Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
S3C7515/P7515
Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI1 VO I OH I OL All I/O ports - One I/O port active All I/O ports active Output Current Low One I/O port active Conditions - Rating -0.3 to 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 30 + 30 (Peak value) + 15 * All I/O ports, total + 100 (Peak value) + 60 * Operating Temperature Storage Temperature TA Tstg - -
Duty . C C
Units V V V mA
mA
- 40 to + 85 - 65 to + 150
*
The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter
Input High Voltage
Symbol
VIH1 VIH2 VIH3
Conditions
All input pins except those specified below for VIH2 - VIH4 Ports 0, 1, 3, 6, 7, and RESET Ports 4 and 5 with pull-up resistors assigned Ports 4 and 5 are open-drain XIN,XOUT and XTIN All input pins except those specified below for VIL2 - VIL3 Ports 0, 1, 3, 6, 7, and RESET XIN,XOUT and XTIN
Min
0.7 VDD 0.8 VDD 0.7 VDD 0.7 VDD VDD - 0.1
Typ -
Max
VDD VDD VDD VDD VDD 0.3 VDD 0.2 VDD 0.1
Units
V
VIH4 Input Low Voltage VIL1 VIL2 VIL3
-
-
V
14-2
S3C7515/P7515
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter
Output High Voltage Output Low Voltage
Symbol
VOH VOL1
Conditions
IOH = - 1 mA Ports except 1,4 and 5 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4,5 only VDD = 2.0 to 5.5 V IOL = 1.6mA VDD = 4.5 V to 5.5 V IOL = 4mA all out Ports except ports 4,5 VDD = 2.0 to 5.5 V IOL = 1.6mA VI = VDD All input pins except those specified below for ILIH2
Min VDD -1.0 -
Typ - - -
Max - 2 0.4 2 0.4
Units
V V V V V
VOL2
Input High Leakage Current
ILIH1
-
-
3
A
ILIH2 Input Low Leakage Current ILIL1
VI = VDD XIN, XOUT and XTIN VI = 0 V All input pins except below and RESET
20 - - -3 A
ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH
VI = 0 V XIN, XOUT and XTIN VO= VDD All output pins
- 20 - - 3 A
ILOL
VO = 0 V All output pins
-
-
-3
RL1
VDD = 5 V ; VI = 0 V except RESET and P4.5 VDD = 3 V
25 50 15 10 100 200 25 50
47 95 47 45 220 450 47 95
100 200 70 60 400 800 100 200
k
RL2
VO=VDD-2V, VDD=5V Ports 4 and 5 only VDD=3V
RL3 RL4
VDD = 5 V ; VI = 0 V; RESET VDD = 3 V VDD = 5 V ; VI = VDD; Port 12 VDD = 3 V
Pull-Down Resistor
14-3
ELECTRICAL DATA
S3C7515/P7515
Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (DTMF ON) Conditions Run mode; VDD=5.0V 10% 3.58MHz Crystal oscillator; C1=C2=22pF VDD = 3 V 10% IDD2 Run mode; VDD=5.0V 10% VDD = 3 V 10% IDD3 Idle mode; VDD = 5 V 10% VDD = 3 V 10% IDD4 IDD5 IDD6 Run mode; VDD=3.0V 10% 32 kHz Crystal oscillator Idle mode; VDD=3.0V 10% 32 kHz Crystal oscillator Stop mode; VDD=5.0V 10% VDD=3.0V 10% Row Tone Level VROW VDD = 5 V 10% VDD = 3 V 10% VDD = 2 V RL = 5k VDD = 5 V 10% VDD = 3 V 10% VDD = 2 V RL = 5k VDD = 5 V 10% VDD = 3 V 10% VDD = 2 V RL = 5k, 1MHz band -16 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz Min - Typ 2.2 Max 5.0 Units mA
1.2 3.9 2.0 1.8 0.8 1.3 0.6 0.5 0.4 15.3 6.4 2.5 0.5 -14
3.0 8.0 4.0 4.0 2.3 2.5 1.8 1.5 1.0 30 15 5 3 -11 dBV A
(DTMF OFF) Crystal oscillator; C1=C2=22pF
Ratio of Column to Row Tone
DbCR
1
2
3
dB
Distortion (Dual tone)
THD
-
-
5
%
NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors. 2. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
14-4
S3C7515/P7515
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 2.0 V to 5.5 V) Oscillato r Ceramic Oscillator Clock Configuration
Xin Xout (1)
Parameter Oscillation frequency
Test Condition VDD = 2.7 V to 5.5 V
Min 0.4
Typ -
Max 6.0
Units MHz
C1
C2
VDD = 2.0 V to 5.5 V Stabilization time (2) Crystal Oscillator
Xin Xout
0.4 - 0.4
- - -
4.2 4 6.0 ms MHz
VDD = 3V VDD = 2.7 V to 5.5V
Oscillation frequency
(1)
C1
C2
VDD = 2.0 V to 5.5V Stabilization time (2) External Clock
Xin Xout
0.4 - 0.4
- - -
4.2 10 6.0 ms MHz
VDD = 3 V VDD = 2.7 V to 5.5V
Xin input frequency (1)
VDD = 2.0 V to 5.5V Xin input high and low level width (tXH, tXL) -
0.4 83.3
- -
4.2 1250 ns
NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
14-5
ELECTRICAL DATA
S3C7515/P7515
Table 14-4. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTin XTout (1)
Parameter Oscillation frequency
Test Condition -
Min 32
Typ 32.768
Max 35
Units kHz
C1
C2
Stabilization time (2)
VDD =2.7V to 5.5V VDD =2.0V to 5.5V -
- - 32
1.0 - -
2 10 100
s s kHz
External Clock
XTin
XTout
XTin input frequency
(1)
XTin input high and low level width (tXH, tXL)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs or when stop mode is terminated.
Table 14-5. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
14-6
S3C7515/P7515
ELECTRICAL DATA
Table 14-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Instruction Cycle Time (1) TCL0, TCL1 Input Frequency TCL0, TCL1 Input High, Low Width Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V f TI0, f TI1 VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V tTIH0, tTIL0 VDD = 2.7 V to 5.5 V tTIH1, tTIL1 VDD = 2.0 V to 5.5 V SCK Cycle Time tKCY VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source SCK High, Low Width tKH, tKL VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source SI Hold Time to SCK High tKSI VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source 500 400 600 500 400 - - ns 150 150 tKCY - 2150 100 - - ns tKCY- 250 1600 3800 335 - - ns 670 3200 0.48 1.8 800 - - ns - Min 0.67 0.95 0 - 1.5 1 - MHz MHz s Typ - Max 64 Units s
14-7
ELECTRICAL DATA
S3C7515/P7515
Table 14-6. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Output Delay for SCK to SO Symbol Conditions External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL INT0, INT1, INT2, INT4, KS0-KS7 Input
10
Min -
Typ -
Max 300 250 1000 1000
Units ns
tKSO(NOTE) VDD = 2.7 V to 5.5 V
- -
- -
s s
10
NOTE: R (1 k) and C (100 pF) are the load resistance and load capacitance of the SO output line.
CPU CLOCK 1.5 MHz
Main Osc. Freq. (Divided by 4) 6 MHz
1.05 MHz
4.2 MHz
15.625 kHz 1 2 3 2.7 V SUPPLY VOLTAGE (V) CPU CLOCK = oscillator frequency x 1/n (n = 4, 8, 64) 4 5 6 7
Figure 14-1. Standard Operating Voltage Range
14-8
S3C7515/P7515
ELECTRICAL DATA
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.5 V - Released by RESET Released by interrupt Min 1.5 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 5.5 10 - - -
Unit V A s ms ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-9
ELECTRICAL DATA
S3C7515/P7515
TIMING WAVEFORMS
INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE OPERATING MODE
VDD
EXECUTION OF STOP INSTRUCTION RESET
VDDDR
tWAIT tSREL
Figure 14-2. Stop Mode Release Timing When Initiated By RESET
IDLE MODE STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE
VDD VDDDR
EXECUTION OF STOP INSTRUCTION
tSREL
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST)
Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request
14-10
S3C7515/P7515
ELECTRICAL DATA
0.8 VDD 0.2 VDD MEASUREMENT POINTS
0.8 VDD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for Xin and XTin)
1/fx
tXL
tXH
Xin
VDD - 0.1 V
0.1 V
Figure 14-5. Clock Timing Measurement at Xin (XTin)
1 / fTI
tTIL
TCL
tTIH 0.8 VDD 0.2 VDD
Figure 14-6. TCL0/1 Timing
14-11
ELECTRICAL DATA
S3C7515/P7515
tRSL
RESET
0.2 VDD
Figure 14-7. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4 KS0 to KS7
0.8 VDD 0.2 VDD
Figure 14-8. Input Timing for External Interrupts and Quasi-Interrupts
14-12
S3C7515/P7515
ELECTRICAL DATA
tKCY tKL
SCK
tKH 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD
SI
INPUT DATA
0.2 VDD tKSO
SO OUTPUT DATA
Figure 14-9. Serial Data Transfer Timing
14-13
ELECTRICAL DATA
S3C7515/P7515
CHARACTERISTIC CURVES NOTE The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values.
(TA = 25 C)
7.0 6.0 5.0
IDD 1 (@5.5 V, fx/4)
4.0 3.0
IDD (mA)
2.0 1.0 0.8
IDD 1 (@5.5 V, fx/64) IDD 1 (@3.5 V, fx/4) IDD 3 (@5.5 V, fx/4)
IDD 3 (@3.5 V, fx/4)
0.6 0.4 0.2
0
1
2
3
4
5
fx (MHz)
Figure 14-10. IDD VS. Frequency
14-14
S3C7515/P7515
ELECTRICAL DATA
(TA = 25 C, fx = 4.2 MHz)
6.0 5.0
IDD 1 (Operating mode,
4.0 3.0 2.0
DTMF on) **
IDD 2 (Operating
mode, DTMF off) **
IDD (mA)
IDD 3 (Idle mode) **
1.2 1.0 0.8 0.6 0.4 0.2
IDD 1 (Operating
mode, DTMF on) *
IDD 5 (Stop mode) ** IDD 2 (Operating
mode, DTMF off) *
IDD 3 (Idle mode) *
0
3
4
5
6
VDD (V)
* fx/64 ** fx/4
Figure 14-11. IDD VS. VDD
14-15
ELECTRICAL DATA
S3C7515/P7515
(TA = 25 C, P0, 2, 3, 6 - 13)
100 90 80 70 6.0 V
IOL (mA)
60 50 40 30 20 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
4.5 V
4.0
4.5
5.0
5.5
6.0
VOL (V)
Figure 14-12. IOL VS. VOL (P0, 2, 3, and 6-13)
(TA = 25 C, P0, 2, 3, 6 - 13)
-30 -25
IOH (mA)
-20 -15 -10 -5 4.5 V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.0 V
VOH (V)
Figure 14-13. IOH VS. VOH (P0, 2, 3, and 6-13)
14-16
S3C7515/P7515
ELECTRICAL DATA
(TA = 25 C, P4, 5)
100 90 80 70 6.0 V
IOL (mA)
60 50 40 30 20 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
4.5 V
4.5
5.0
5.5
6.0
VOL (V) Figure 14-14. IOL VS. VOL (P4 and 5) (TA = 25 C, VDD = 5 V)
4.0 3.0
FREQUENCY (MHz)
2.0 1.0 0.8 0.4 0.2 0 0 10 50 100 500 600 Figure 14-16. Frequency VS. Resistor 200 300 400 700 800 900 1000
14-17
S3C7515/P7515
MECHANICAL DATA
15
-- Pad diagram
MECHANICAL DATA
This section contains the following information about the device package: -- Package dimensions in millimeters
-- Pad/pin coordinate data table
20.00 TYP
2.45 MAX
+ 0.1 0.10 - 0.05
14.00 TYP
64-QFP-1420A
19.00 0.3
1.00 TYP
0.40 0.1
+ 0.1 0.15 - 0.05
25.00 0.3
1.20 0.2
NOTE: Typical dimensions are in millimeters.
Figure 15-1. 64-QFP-1420A Package Dimensions
15-1
MECHANICAL DATA
S3C7515/P7515
23.20 0.3 20.00
3.00 MAX
0.15 0.1
(1.00)
64-QFP-1420C
17.20 0.3
0.15
14.00
64 2.65 0.1
#1 (1.00) 0.40 0.1 1.00 + 0.1 - 0.05
0.15
0.80 0.2
NOTE: Typical dimensions are in millimeters.
Figure 15-2 64-QFP-1420C Package Dimensions
15-2
0.80 0.2
S3C7515/P7515
MECHANICAL DATA
57.80 0.2 0 ~ 15
64-SDIP-750
17.00 0.2
19.05 TYP
1.00 0.1
0.25
+0.1 - 0.05
5.08 MAX 3.30 0.3 1.778 TYP 0.45 0.1 0.51 MIN
NOTE: Typical dimensions are in millimeters.
Figure 15-3. 64-SDIP-750 Package Dimensions
15-3
S3C7515/P7515
S3P7515 OTP
16
OVERVIEW
S3P7515 OTP
The S3P7515 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7515 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P7515 is fully compatible with the S3C7515, both in function and in pin configuration. Because of its simple programming requirements, the S3P7515 is ideal for use as an evaluation chip for the S3C7515.
P1.3 / INT4 P1.2 / INT2 P1.1 / INT1 P1.0 / INT0 P13.2 P13.1 P13.0 P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P0.3 / BTCO P0.2 / SI P0.1 / SO P0.0 / SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P12.0 SDAT / P3.3 SCLK / P3.2 VPP / TEST DTMF VDD / VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS / VSS P9.0 P9.1 P9.2 P9.3 P8.0 P8.1 P8.2 P8.3 P7.0 / KS4 P7.1 / KS5 P7.2 / KS6 P7.3 / KS7 P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / KS3 XTout XTin Xin Xout RESET / RESET P5.0 P5.1 P5.2 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0 / TCL0 P3.1 / TCL1
NOTE: The bolds indicate a OTP pin name.
Figure 16-1. S3P7515 Pin Assignments (64-SDIP)
(64-SDIP-750)
S3P7515
16-1
S3P7515 OTP
S3C7515/P7515
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P8.0 P9.3 P9.2 P9.1 P9.0 VSS / VSS P1.3 / INT4 P1.2 / INT2 P1.1 / INT1 P1.0 / INT0 P13.2 P13.1 P13.0 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20
P8.1 P8.2 P8.3 P7.0 / KS4 P7.1 / KS5 P7.2 / KS6 P7.3 / KS7 P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / KS3 XTout XTin Xin Xout RESET / RESET P5.0 P5.1 P5.2
S3P7515 (64-QFP-1420F)
P5.3 P4.0 P4.1 P4.2 P4.3 P3.0 / TCL0 P3.1 / TCL1 VDD / VDD DTMF TEST / VPP P3.2 / SCLK P3.3 / SDAT P12.0
NOTE: The bolds indicate a OTP pin name.
Figure 16-2. S3P7515 Pin Assignments (64-QFP)
16-2
P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P0.3 / BTCO P0.2 / SI P0.1 / SO P0.0 / SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
S3C7515/P7515
S3P7515 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Pin Name Pin No. SDAT SCLK Vpp(TEST) 28 (21) 29 (22) 30 (23) I/O I/O I I During Programming Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming.
RESET VDD / VSS
43 (36) 32 (25) / 64 (57)
I I
NOTE: Parentheses indicate pin number for 64 QFP package.
Table 16-2. Comparison of S3P7515 and S3C7515 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 2.0 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 64SDIP / QFP User Program 1 time 64SDIP / QFP Programmed at the factory S3P7515 16 K byte EPROM S3C7515 2 K byte mask ROM 2.0 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P7515, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 14-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V Vpp (TEST) 5V 12.5V 12.5V 12.5V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection R/W W Mode
NOTE: "0" means Low level; "1" means High level.
16-3
S3P7515 OTP
S3C7515/P7515
Table 16-4. D.C. Electrical Characteristics (TA = - 40C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Supply Current
(1,2)
Symbol IDD1 (DTMF ON)
Conditions Run mode; VDD =5.0V 10% 3.58MHz Crystal oscillator; C1=C2=22pF VDD = 3 V 10%
Min -
Typ 2.2
Max 5.0
Units mA
1.2 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 3.9 2.0 1.8 0.8 1.3 0.6 0.5 0.4 15.3 6.4 2.5 0.5
3.0 8.0 4.0 4.0 2.3 2.5 1.8 1.5 1.0 30 15 5 3 A
IDD2 (DTMF OFF)
Run mode; VDD =5.0V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10%
IDD3
Idle mode; VDD = 5 V 10% VDD = 3 V 10%
6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz
IDD4 IDD5 IDD6
Run mode; VDD =3.0V 10% 32 kHz Crystal oscillator Idle mode; VDD =3.0V 10% 32 kHz Crystal oscillator Stop mode; VDD =5.0V 10% VDD=3.0V 10%
NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors. 2. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
16-4
S3C7515/P7515
S3P7515 OTP
CPU CLOCK 1.5 MHz
Main Osc. Freq. (Divided by 4) 6 MHz
1.05 MHz
4.2 MHz
15.625 kHz 1 2 3 2.7 V SUPPLY VOLTAGE (V) CPU CLOCK = oscillator frequency x 1/n (n = 4, 8, 64) 4 5 6 7
Figure 16-3. Standard Operating Voltage Range
16-5
S3P7515 OTP
S3C7515/P7515
START
Address= First Location
VDD =5V, V PP=12.5V
x= 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO FAIL
Verify Byte
Verify 1 Byte
FAIL
Last Address
NO
Increment Address
VDD = VPP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-4. OTP Programming Algorithm
16-6

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