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CDP1853C/3
March 1997
High-Reliability CMOS N-Bit 1 of 8 Decoder
Description
The CDP1853/3 and CDP1853C/3 are high-reliability 1 of 8 decoders designed for use in general purpose microprocessor systems. These devices, which are functionally identical, are specifically designed for use as gated N-bit decoders and interface directly with the 1800-Series microprocessors without additional components. The CDP1853/3 has a recommended operating voltage range of 4V to 10.5V, and the CDP1853C/3 has a recommended operating voltage range of 4V to 6.5V. When CHIP ENABLE (CE) is high, the selected output will be true (high) from the trailing edge of CLOCK A (high-to-low transition) to the trailing edge of CLOCK B (high-to-low transition). All outputs will be low when the device is not selected (CE = 0) and during conditions of CLOCK A and CLOCK B as shown in Figure 2. The CDP1853/3 inputs N0, N1, N2, CLOCK A, and CLOCK B are connected to 1800series microprocessor outputs N0, N1, N2, TPA, and TPB respectively, when used to decode I/O commands as shown in Figure 5. The CHIP ENABLE (CE) input provides the capability for multiple levels of decoding as shown in Figure 6. The CDP1853/3 can also be used as a general purpose 1 of 8 decoder for I/O and memory system applications as shown in Figure 4.
Features
* Provides Direct Control of Up to 7 Input and 7 Output Devices When used with a CDP1800-Series Microprocessor * CHIP ENABLE (CE) Allows Easy Expansion for Multilevel I/O Systems
Ordering Information
PACKAGE SBDIP TEMP. RANGE 5V 10V PKG. NO. D16.3
-55oC to +125oC CDP1853CD3
Pinout
16 LEAD SBDIP TOP VIEW
CLK A 1 N0 2 N1 3 OUT 0 4 OUT 1 5 OUT 2 6 OUT 3 7 VSS 8 16 VDD 15 CLK B 14 N2 13 CE 12 OUT 4 11 OUT 5 10 OUT 6 9 OUT 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1713.2
4-40
CDP1853/3, CDP1853C/3 CDP1853/3 Functional Diagram
4 N0 2 5 6 N1 3 1 OF 8 DECODER 7 12 11 10 EN 13 CE 9
TRUTH TABLE CE
OUT 0 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7
CL A 0 0 1 1 X
CL B 0 1 0 1 X
EN Qn-1(Note 2) 1 0 1 0
1 1 1 1 0
N2
14
N2 0 0
N1 0 0 1 1 0 0 1 1 X
N0 0 1 0 1 0 1 0 1 X
EN 1 1 1 1 1 1 1 1 0
0 1 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0
2 0 0 1 0 0 0 0 0 0
3 0 0 0 1 0 0 0 0 0
4 0 0 0 0 1 0 0 0 0
5 0 0 0 0 0 1 0 0 0
6 0 0 0 0 0 0 1 0 0
7 0 0 0 0 0 0 0 1 0
1 CLOCK A (TPA)
0
QN
0 1 1 1
15 CLOCK B (TPB)
1 X NOTES: FIGURE 1.
1. 1 = High level, 0 = Low level, X = Don't care. 2. Qn-1 = Enable remains in previous state.
4-41
CDP1853/3, CDP1853C/3
Static Electrical Specifications
CONDITIONS -55oC, +25oC PARAMETER Quiescent Device Current SYMBOL ISS (Note 1) VO (V) Output Low Drive (Sink) Current IOL 0.4 0.5 Output High Drive (Source) Current IOH 4.6 9.5 Output Voltage Low-Level VOL (Note 2) Output Voltage High-Level VOH (Note 2) Input Low Voltage VIL 0.8, 4.2 1, 9 Input High Voltage VIH 0.8, 4.2 1, 9 Input Leakage Low IIL Input Leakage High IIH Input Capacitance Output Capacitance NOTES: 1. The CDP1853C meets all 5V static electrical characteristics of the CDP1853 except quiescent device current for which the limits are: ISS = -500A at -55oC and +25oC and ISS = -1000A at +125oC. 2. Guaranteed but not tested. CIN (Note 2) COUT (Note 2) VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0 0 5 10 VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 MIN -50 -500 2.3 3.7 4.9 9.9 3.5 7 -1 -1 MAX -1.7 -3.7 0.1 0.1 1.5 3 1 1 10 15 LIMITS +125oC MIN -100 -1000 1.6 2.6 4.8 9.8 3.5 7 -5 -5 MAX -1.2 -2.6 0.2 0.2 1.5 3 5 5 10 15 UNITS A A mA mA mA mA V V V V V V V V A A A A pF pF
Dynamic Electrical Specifications
See Figure 2, CL = 100pF, tR, tF = 15ns LIMITS -55oC, +25oC +125oC MIN MAX 275 150 UNITS ns ns
PARAMETER Propagation Delay Time: Chip Enable (CE) to Output High
SYMBOL tEOH
VDD (V) 5 10
MIN -
MAX 175 90
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CDP1853/3, CDP1853C/3
Dynamic Electrical Specifications
See Figure 2, CL = 100pF, tR, tF = 15ns LIMITS -55oC, +25oC PARAMETER Disable to Output Low SYMBOL tEOL VDD (V) 5 10 N Input to Output tNO 5 10 Clock A to Output Low tAO 5 10 Clock B to Output Low tBO 5 10 Pulse Width: Clock A Clock B tCBCB tCACA 5 10 5 10 MIN 50 25 50 25 MAX 295 200 225 120 210 110 295 200 +125oC MIN 75 50 75 50 MAX 400 250 315 165 300 150 400 250 UNITS ns ns ns ns ns ns ns ns ns ns ns ns
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS CDP1853/3 CDP1853C/3 MAX 10.5 VDD MIN 4 VSS MAX 6.5 VDD UNITS V V
PARAMETER DC Operating Voltage Range Input voltage Range
MIN 4 VSS
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CDP1853/3, CDP1853C/3
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1853/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1853C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . 10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 85 22 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Timing Diagrams
N0 - N2
CE
OUTPUT 0 - 7 TN0
OUTPUT 0 - 7 TEOH TEOL
FIGURE 2A. N - INPUTS TO OUTPUTS DELAY TIME
FIGURE 2B. CE TO OUTPUT DELAY TIME
MIN. CLOCK A PULSE WIDTH MIN. CLOCK B PULSE WIDTH CLOCK B TCBCB CLOCK A OUTPUT 0 - 7
TCACA
TAO OUTPUT 0 - 7 TBO (SEE NOTE 1)
NOTE: 1. To measure TAO, Clock B must be tied low. FIGURE 2D. CLOCK A TO OUTPUT DELAY TIME
FIGURE 2C. CLOCK B TO OUTPUT DELAY TIME
FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS
TPA TPB CE EN (NOTE 1) OUTPUT A B C CHIP ENABLE VDD N0 N1 N2 CE
OUT 0 OUT 1 OUT 2 OUT 3 OUT 4
CLK B OUT 5 CLK A OUT 6 OUT 7
NOTE: 1. Output enabled when EN = high. Internal signal shown for reference only (see Figure 1). FIGURE 3. TIMING DIAGRAM
FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER
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CDP1853/3, CDP1853C/3
CDP1802 CPU TPA TPB VDD CLOCK A CLOCK B CE N0 N1 N2 CDP1853 0 1 2-6 7 N0 N1 N2 TPB MRD
CS1 CS2 LOAD VIA 67 INSTRUCTION DATA AVAILABLE DATA CDP1852 OUTPUT PORT 7 SR MODE TPB VDD DATA BUS
CS1 CS2 CDP1852 INPUT PORT 7
READ VIA 6F INSTRUCTION DATA
MODE
STROBE
CLOCK 5 CDP1852 INPUT AND OUTPUT PORTS
CS2 CS1 LOAD VIA 61 INSTRUCTION AVAILABLE CDP1852 OUTPUT PORT 1 SR MODE TPB VDD 7 OUTPUT PORTS
CS1 CS2 CDP1852 INPUT PORT 1 MODE
READ VIA 69 INSTRUCTION DATA
STROBE
CLOCK 7 INPUT PORTS
FIGURE 5. N-BIT DECODER IN A ONE LEVEL I/O SYSTEM
4-45
CDP1853/3, CDP1853C/3
N0 N1 N2
CDP1800 SERIES MRD BUS TPA TPB
DATA BUS TPA CDP1853 1 DECODED "61" INSTRUCTION CL CS1 CS2 CDP1852
NO, N1, N2
CLOCK A CLOCK B CE CDP1853 "62 - 6F" INST.
I/O 7 INPUT, 6 OUTPUT PORTS
NO, N1, N2
CLOCK A CLOCK B CE CDP1853 "62 - 6F" INST. SECTIONS 3 - 7 CLOCK A CLOCK B CE CDP1853 "62 - 6F" INST.
I/O 7 INPUT, 6 OUTPUT PORTS
NO, N1, N2
I/O 7 INPUT, 6 OUTPUT PORTS
NOTE: 1. System shown will select up to 56 input and 48 output ports. With additional decoding, the total number of input and output ports can be further expanded. FIGURE 6. TWO LEVEL I/O USING CDP1853 AND CDP1852
Bias/Static Burn-In Circuit
VDD 1 2 3 4 5 6 7 VSS 8 16 15 14 13 12 11 10 9 VDD VSS VDD
TYPE CDP1853C
VDD 7V
TEMPERATURE +125oC
TIME 160 Hrs.
NOTE: 1. All resistors are 47k 20%.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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