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CDP1872C, CDP1874C, CDP1875C
March 1997
High-Speed 8-Bit Input and Output Ports
Description
The CDP1872C, CDP1874C and CDP1875C devices are high-speed 8-bit parallel input and output ports designed for use in the CDP1800 microprocessor system and for general use in other microprocessor systems. The CDP1872C and CDP1874C are 8-bit input ports; the CDP1875C is an 8-bit output port. These devices have flexible capabilities as buffers and data latches and are reset by CLR input when the data strobe is not active. The CDP1872C and CDP1874C are functionally identical except for device selects.The CDP1872C has one active low and one active high select; the CDP1874C has two active high device selects. These devices also feature Three-state outputs when deselected. Data is strobed into the register on the leading edge of the CLOCK and latched on the trailing edge of the CLOCK. The CDP1875C is an output port with data latched into the registers when the device selects are active. There are two active high and one active low selects. The output buffers are enabled at all times.
Features
* Parallel 8-Bit Input/Output Register with Buffered Outputs * High-Speed Data-In to Data-Out 85ns (Max) at VDD = 5V * Flexible Applications In Microprocessor Systems as Buffers and Latches * High Order Address-Latch Capability in CDP1800Series Microprocessor Systems * Output Sink Current = 5mA (Min) at VDD = 5V * Three-State Output - CDP1872C and CDP1874C
Ordering Information
PART NUMBER CDP1872CE CDP1874CE CDP1875CE TEMP. RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC PACKAGE PDIP PDIP PDIP PKG. NO. E22.4 E22.4 E22.4
Pinouts
CDP1872C INPUT PORT (PDIP) TOP VIEW
CS1 DI0 DO0 DI1 D01 DI2 D02 DI3 D03 CLOCK VSS 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VDD DI7 D07 DI6 D06 DI5 D05 DI4 D04 CLR CS2 CS1 DI0 DO0 DI1 D01 DI2 D02 DI3 D03 CLOCK VSS
CDP1874C INPUT PORT (PDIP) TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VDD DI7 D07 DI6 D06 DI5 D05 DI4 D04 CLR CS2 CS1 DI0 DO0 DI1 D01 DI2 D02 DI3 D03 CS3 VSS
CDP1875C OUTPUT PORT (PDIP) TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VDD DI7 D07 DI6 D06 DI5 D05 DI4 D04 CLR CS2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1255.2
4-76
CDP1872C, CDP1874C, CDP1875C
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . . -0.5V to +7V (Voltage referenced to VSS Terminal) Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
At TA = -40 to +85oC. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS ALL TYPES 4 to 6.5 VSS to VDD
PARAMETER DC Operating-Voltage Range Input Voltage Range
UNITS V V
Static Electrical Specifications
At TA = -40 to +85oC, VDD 5%, Unless Otherwise Specified. LIMITS ALL TYPES VDD (V) 5 5 (NOTE 1) TYP 25 10
TEST CONDITIONS VO (V) IDD IOL IOH VOL VOH VIL VIH IIN IOUT CIN COUT 0.4 VIN (V) 0, 5 0, 5
PARAMETER Quiescent Device Current Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low-Level (Note 2) Output Voltage High-Level (Note 2) Input Low Voltage Input High Voltage Input Leakage Current Three-State Output Leakage Current (Note 3) Input Capacitance Output Capacitance (Note 3) NOTES:
MIN 5
MAX 50 -
UNITS A mA
4.6
0, 5
5
-4
-7
-
mA
-
0, 5
5
-
0
0.1
V
-
0, 5
5
4.9
5
-
V
0.5, 4.5 0.5, 4.5 0, 5
0, 5 0, 5
5 5 5 5
3.5 -
-
1.5 1 5 -
V V A A pF pF
-
-
-
-
15 15
1. Typical values are for TA = +25oC and nominal VDD 5%. 2. IOL = IOH = 1A 3. For CDP1872C and CDP1874C only.
4-77
CDP1872C, CDP1874C, CDP1875C Logic Diagrams
CS1 CS2 DI CLOCK D C R CLR CLR Q DO CS1 CS2 DI CLOCK D C R Q DO
FIGURE 1. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES SHOWN) FOR CDP1872C
DI D C
FIGURE 2. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES SHOWN) for CDP1874C
CS1 CS2 CS3
Q
DO
R CLR
FIGURE 3. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES SHOWN) FOR CDP1875C
Dynamic Electrical Specifications
At TA = 25oC, VDD 5V, tR, tF = 10ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 150pF LIMITS CDP1872C, CDP1874C (NOTE 1) TYP (NOTE 2) MAX
PARAMETER INPUT PORT (FIGURE 4) Output Enable Output Disable Clock to Data Out Clear to Output Data In to Data Out Minimum Data Setup Time Data Hold Time Minimum Clock Pulse Width Minimum Clear Pulse Width NOTES: 1. Typical values are for TA = +25oC and VDD 5%. 2. Maximum values are for TA = +85oC and VDD 5% tEN tDIS tCLO tCRO tDIO tDSU tDH tCL tCR
MIN
UNITS
-
45 45 45 80 50 10 10 30 30
90 90 90 160 85 30 30 60 60
ns ns ns ns ns ns ns ns ns
4-78
CDP1872C, CDP1874C, CDP1875C
CSI * CS2 (CDP1872C) CSI * CS2 (CDP1874C) CLOCK
tDSU tDH tCL
DATA IN tEN DATA BUS (HIGH Z) tDIO CLR tCR tCRO tCLO tDIS
FIGURE 4. TIMING WAVEFORMS FOR CDP1872C AND CDP1874C (INPUT-PORT TYPES)
Dynamic Electrical Specifications
At TA = 25oC, VDD 5V, tR, tF = 10ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 150pF LIMITS CDP1875C (NOTE 1) TYP (NOTE 2) MAX
PARAMETER OUTPUT PORT (FIGURE 5) Clock to Data Out Clear to Output Data In to Data Out Minimum Data Setup Time Data Hold Time Minimum Clear Pulse Width NOTES: 1. Typical values are for TA = +25oC and VDD 5%. 2. Maximum values are for TA = +85oC and VDD 5% tCLO tCRO tDIO tDS tDH tCR
MIN
UNITS
-
50 80 50 10 10 30
100 160 85 30 30 60
ns ns ns ns ns ns
CSI * CS2 * CS3 = CLOCK tDS tDH
DATA IN tDIO DATA OUT tCLO CLR tCR tCRO
FIGURE 5. TIMING WAVEFORMS FOR CDP1875C (OUTPUT PORT)
4-79
CDP1872C, CDP1874C, CDP1875C
CSI DO MRD TPA CLOCK D0 D1 D2 CDP1874C D3 D4 D5 D6 D7 CSI CS2 CS2
CLOCK DI DATA IN
CDP1874C
MA8 * * * MA15
ADDRESS BUS
CDP1802
CS2 CS3
CDP1875C
VDD TPB DATA BUS 0-7 DI CS1 DO DATA OUT
DATA BUS
FIGURE 6. CDP1874C USED AS AN INPUT PORT AND ADDRESS LATCH WITH CDP1875C USED AS AN OUTPUT PORT
CS2 DATA BUS
CLOCK DATA IN
CDP1872C
D0 - D7 Y1 Y2 Y3 Y4 Y5 Y6 Y7 CS1
N0 N1 MRD N2
A0 A1 A2
CS2
CLOCK
CD74HC138
CS1
CDP1802A
DATA BUS
CDP1872C
DATA OUT
FIGURE 7. CDP1872C USED AS AN INPUT PORT AND SELECTED BY CD74HC138
4-80
CDP1872C, CDP1874C, CDP1875C
MRD
CDP1802
N0 N1 N2 DO - D7
CS1
CS2 TPB
CS2 CS3 DI
CS1
DATA IN
DI
DO
DO
DATA OUT
CDP1874C
CDP1875C
CS1
CS2
CS2
CS1
DATA IN
DI
DO
DI
DO
DATA OUT
CDP1874C
TPB MEMORY
CDP1875C
CS3
FIGURE 8. CDP1874C AND CDP1875C USED AS INPUT/OUTPUT BUFFERS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
4-81

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