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CXP881P60
CMOS 8-bit Single Chip Microcomputer
Description The CXP881P60 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuits, PWM output, PWM for tuner, VISS/VASS circuit, 32kHz timer counter, remote control reception circuit, fluorescent display panel (FDP) controller/driver, VSYNC separator and the measurement circuit which measures signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, PROM, RAM and I/O port. They are integrated into a single chip. Also, CXP881P60 provides sleep/stop function which enables to lower power consumption and ultra-low speed instruction mode in 32kHz operation. The CXP881P60 is the PROM-incorporated version of the CXP88160 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 100 pin QFP (Plastic)
Structure Silicon gate CMOS IC
Features * A wide instruction set (213 instructions) which cover various types of data -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation 122s at 32kHz operation * Incorporated PROM capacity 60K bytes * Incorporated RAM capacity 1296 bytes (including fluorescent display area) * Peripheral function -- A/D converter 8 bits, 8 channels, successive approximation system (Conversion time of 20s/16MHz) -- Serial interface Incorporated 8-bit 8-stage FIFO for data (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel -- Timer 8-bit timer/counter, 2 channel 19-bit time base timer 32kHz timer/counter -- High precision timing pattern generator PPG 8 pins, 21-stage programmable circuit RTG 5 pins, 2 channels -- PWM/DA gate output 12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz) DA gate pulse output, 13 bits, 4 channels -- Servo input control Capstan FG, Drum FG/PG, CTL input -- VSYNC separator -- FRC capture unit Incorporated 26-bit and 8-stage FIFO -- PWM output 14 bits, 1 channel -- VISS/VASS circuit Pulse duty auto detection circuit -- Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO -- Fluorescent display panel controller/driver Maximum 144-segment display possible Hardware key scan function (Maximum 16 x 3 key matrix available) Dimmer function High voltage drive output (40V) Incorporated pull-down resistor (mask option) -- Tri-state output PPG 1 pin, RTG 1 pin, output 8 pins -- Pseudo HSYNC output function -- High speed head switching circuit * Interruption 22 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E95325-ST
Block Diagram
AVss INT1/NMI INT2 INT0 EXTAL XTAL TEX TX RST MP VDD Vss Vpp
AVDD
AVREF
2
PORT A
AN0 to AN7 SPC700 CPU CORE 4
PORT B
8 CLOCK GENERATOR/ SYSTEM CONTROL 8
A/D CONVERTER
2
4 PA0 to PA7
FIFO
SERIAL INTERFACE UNIT (CH0)
PB0 to PB7
EC0 EC1 EC2 TO/DDO
PORT D
EC SELECT
8 BIT TIMER/COUNTER 0
INTERRUPT CONTROLLER
2
PROM 60K BYTES
RAM 1296 BYTES
PORT C
CS0 SI0 SO0 SCK0 SI1 SO1 SCK1 8
SERIAL INTERFACE UNIT (CH1)
PC0 to PC7
8 BIT TIMER/COUNTER1
8
PD0 to PD7
V SYNC SEPARATOR 2 2
PORT E
2 6 4 4
PE0 to PE1 PE2 to PE7 PF0 to PF3 PF4 to PF7
SYNC0 SYNC1 EXI0 EXI1 PRESCALER/ TIME BASE TIMER 3 FIFO FRC CAPTURE UNIT FIFO
32kHz TIMER/COUNTER
VISS/VASS
PORT G
PWM
14 BIT PWM GENERATOR 2 2 PROGRAMABLE PATTERN GENERATOR RAM REALTIME PULSE GENERATOR CH0 CH1
PORT I
PORT H
VFDP
T0 to T7
PPO0 to PPO7
RTO3 to RTO7
T8/S15 to T15/S8 S0 to S7
-2-
4 8 5 8 8
DRUM
SERVO INPUT CONTROL
CFG DFG DPG PBCTL
CTL
PORT F
CAPSTAN
RMC
REMOCON INPUT
8
PG0 to PG7
3
PH0 to PH2
12 BIT PWM GENERATOR CH0
7
PI1 to PI7 RAM
PWM0 DAA0 DAB0 PWM1 DAA1 DAB1
12 BIT PWM GENERATOR CH1
FDP CONTROLLER /DRIVER
HGO
PSEUDO HSYNC GENERATOR 8
ADJ
CXP881P60
CXP881P60
Pin Configuration (Top View)
PI3/TO/DDO/ADJ
PI4/INT1/NMI/CS0
PH0/KR0
PH1/KR1
PH2/KR2
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Vpp
VSS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB0 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2 PC1 PC0 PA7/PPO7 (HAMP) PA6/PPO6 (ROTA) PA5/PPO5 (RF-PLS) PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 HGO/PA0/PPO0 PF7 SI1/PF6 SO1/PF5 SCK1/PF4 PF3/AN7 PF2/AN6 PF1/AN5 PF0/AN4 AN3 AN2 AVREF AVSS AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO0 PI7/SI0 VFDP PD0/S0 PD1/S1 PD2/S2 PD3/S3 PD4/S4 PD5/S5 PD6/S6 PD7/S7 S8/T15 S9/T14 S10/T13 S11/T12 S12/T11 S13/T10 S14/T9 S15/T8 T7 T6 T5 T4 T3 T2 T1 T0 PE0/INT0 (ENV-DET) PE1/EC0/INT2 PWM0/PE2
TX
TEX
VDD
PI1/RMC
PI2/PWM
Note) 1. Vpp (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) must be connected to GND.
PG4/SYNC0/EC2
PG3/PBCTL/EC1
PG5/SYNC1
-3-
PE3/PWM1
DAB1/PE7
DAB0/PE6
PE5/DAA1
PE4/DAA0
PG7/EXI1
PG6/EXI0
PG2/DPG
PG1/DFG
PG0/CFG
EXTAL
XTAL
RST
AN1
AN0
VSS
MP
PI5/SCK0
CXP881P60
Pin Description Symbol PA0/PPO0/ HGO PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 PB0 to PB7 PC0 to PC2 PC3/RTO3 to PC7/RTO7 T0 to T7 T8/S15 to T15/S8 PD0/S0 to PD7/S7 PE0/INT0 Output I/O I/O/ Real time output Output Output/Output 8-bit output port. Tri-state can be controlled. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with RTO content by OR-gate and they are output. (8 pins) Output/ Real time output I/O/ Real time output I/O Output/Real time output/Output (Port A) PA0 and PA5 to PA7 are for outputs; PA1 to PA4 are for I/O. I/O can be set in a unit of single bits. Data is gated with PPO content by OR-gate and they are output. (8 pins) Description Pseudo HSYNC output pin. Programmable pattern generator (PPG) output. Functions as high precision realtime pulse output port. (8 pins) Head switching output pins. (2 pins)
Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. (5 pins)
FDP timing signal output pin. (8 pins) Output pins for FDP timing signal and segment signal. (8 pins) (Port D) 8-bit output port. (8 pins)
Output/Output
FDP segment signal output pin. (8 pins) Trigger pulse Input pin to request input pin for head external interruption. switching output. Active when falling edge.
Input/Input
PE1/EC0/ INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/SCK1 PF5/SO1 PF6/SI1 PF7
Input/Input/Input Output/Output Output/Output Output/Output Output/Output Output/Output Output/Output Input Input/Input I/O/I/O I/O/Output I/O/Input I/O
(Port E) 8-bit port. Lower 2 bits are for inputs; upper 6 bits are for outputs. (8 pins)
External event input pin for timer/counter. PWM output pins. (2 pins)
Input pin to request external interruption. Active when falling edge.
DA gate pulse output pins. (4 pins)
Analog input pins to A/D converter. (8 pins)
(Port F) Lower 4 bits are for inputs; upper 4 bits are for I/O. I/O can be set in a unit of single bits. (8 pins)
Serial clock (CH1) I/O pin. Serial data (CH1) output pin. Serial data (CH1) input pin.
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CXP881P60
Symbol PG0/CFG PG1/DFG PG2/DPG PG3/ PBCTL/EC1 PG4/ SYNC0/EC2 PG5/SYNC1 PG6/EXI0 PG7/EXI1 PH0/KR0 to PH2/KR2 PI1/RMC PI2/PWM PI3/TO/ DDO/ADJ PI4/INT1/ NMI/CS0 PI5/SCK0 PI6/SO0 PI7/SI0 EXTAL XTAL TEX TX RST MP VFDP AVDD AVREF AVss VDD Vpp Vss Input
I/O Input/Input Input/Input Input/Input Input/Input/Input (Port G) 8-bit input port. (8 pins)
Description Capstan FG input pin. Drum FG input pin. Drum PG input pin. Playback CTL input pin. External event input pin for timer/counter. External event input pin for timer/counter.
Input/Input/Input Input/Input Input/Input Input/Input
Composite sync signal input pins.
External input pins for FRC capture unit. (Port H) 3-bit I/O port. (3 pins)
I/O/Input
Key return input signal for key scanning at FDP segment signal. (3 pins) Remote control reception circuit input pin. 14-bit PWM output pin.
I/O/Input I/O/Input I/O/Output/ Output/Output I/O/Input/ Input/Input I/O/I/O I/O/Output I/O/Input Input Output Input Output Input Input (Port I) 7-bit I/O port. I/O can be set in a unit of single bits. (7 pins)
Timer/counter, CTL duty detection, 32kHz oscillation adjustment output pin. Input pin to request external interruption, non-maskable interruption and for serial chip select (CH0). Active when falling edge. Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin.
Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (In this time, feedback resistor is not removed.) System reset pin of active "L" level. Test mode pin. Always connect to GND. FDP voltage supply pin when specifying internal resistor by mask option. Positive power supply pin of A/D converter. Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. Positive power supply pin for incorporated PROM writing connect to VDD during normal operation. GND pin. Connect both Vss pins to GND. -5-
CXP881P60
Input/Output Circuit Formats for Pins Pin Port A
HSEL HOUT PPO0
Circuit format
When reset
MPX
PA0/PPO0/ HGO
Data bus
PA0
Hi-Z
RD (Port A)
HSEL HOUTE
MPX
1 pin
Output becomes active from high impedance by data writing to port register. PPO1 PPG control status register bit 0 Tri-state control selection PPO1
PA1/PPO1
PA1 PA1 direction IP Data bus
Hi-Z
1 pin
RD (Port A)
Port A
PPO data
PA2/PPO2 to PA4/PPO4
Port A data
Hi-Z
Port A direction IP Data bus
3 pins Port A
RD (Port A)
PPO data
PA5/PPO5 to PA7/PPO7
Data bus
Port A data
Hi-Z
RD (Port A)
3 pins
Output becomes active from high impedance by data writing to port register.
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CXP881P60
Pin Port B
Port B data
Circuit format
When reset
PB0 to PB7
Data bus RD (Port B) Port B tri-state control
Hi-Z
8 pins Port C
PC0 to PC2
Port C data
Hi-Z
Port C direction IP Data bus
3 pins Port C
RD (Port C)
RTO3
PC3/RTO3
PC3 PC3 direction IP Data bus
Hi-Z
1 pin
RD (Port C) RTO4 RTG interruption control register bit 7 Tri-state control selection RTO4
PC4/RTO4
PC4
Hi-Z
PC4 direction IP Data bus
1 pin
RD (Port C)
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CXP881P60
Pin Port C
Circuit format
When reset
RTO data
PC5/RTO5 to PC7/RTO7
Port C data
Hi-Z
Port C direction IP Data bus
3 pins
RD (Port C)
Port D
Segment output data High voltage drive transistor
PD0/S0 to PD7/S7
Output selection control signal ("0" when reset) Port D data
Hi-Z
Data bus
8 pins
RD (Port D)
High voltage drive transistor Timing output data Output selection control signal ("0" when reset)
T0 to T7 Hi-Z
Pull-down resistor
8 pins
VFDP
Timing output data
High voltage drive transistor
T8/S15 to T15/S8
Output selection control signal ("0" when reset) Segment output data Pull-down resistor
Hi-Z
VFDP
8 pins
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CXP881P60
Pin Port E PE0/INT0 PE1/EC0/INT2 2 pins Port E
IP
Circuit format
Schmitt input INT0 EC0/INT2 Data bus RD (Port E)
When reset
Hi-Z
Port E function select DA gate output or PWM output
PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1
MPX
Hi-Z
Port E data
Data bus
4 pins
RD (Port E)
Hi-Z control
Port E
Port E function select
PE6/DAB0 PE7/DAB1
DA gate output
MPX
High level
Port E data
Data bus
2 pins Port F PF0/AN4 to PF3/AN7 4 pins Port F
Hi-Z control RD (Port E)
Input multiplexer IP To A/D converter
Hi-Z
Port F function select RD (Port F)
SCK1 output enable From serial interface MPX Port F data
Data bus
PF4/SCK1
IP Port F direction
Hi-Z
Data bus
1 pin
RD (Port F) To serial interface Schmitt input
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CXP881P60
Pin Port F
Circuit format
Port F output selection
When reset
From serial interface
PF5/SO1
Port F data Port F direction
MPX
Hi-Z
IP Data bus
1 pin Port F
RD (Port F)
Port F data
PF6/SI1
Data bus
Port F direction
Hi-Z
IP RD (Port F) Schmitt input
1 pin Port F
To serial interface
Port F data
PF7
Port F direction IP RD (Port F)
Hi-Z
Data bus
1 pin PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL/ EC1 PG4/SYNC0/ EC2 PG5/SYNC1 PG6/EXI0 PG7/EXI1 8 pins Port G
Schmitt input IP Data bus RD (Port G)
Hi-Z
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CXP881P60
Pin Port I
Port I function select
Circuit format
When reset
PI2/PWM PI3/TO/ DDO/ADJ
PI2 ... From 14-bit PWM, timer/counter PI3 ... From CTL duty detection circuit, 32kHz timer Port I data Port I direction
MPX
Hi-Z
IP Data bus
2 pins Port I
RD (Port I)
Port I data
PI1/RMC PI4/INT1/ NMI/CS0 PI7/SI0
Port I direction IP
Hi-Z
Data bus RD (Port I) PI1 ... To remote control circuit PI4 ... To interruption circuit PI7 ... To serial CH0 Schmitt input
3 pins
Port I
Port I function select From serial CH0 Port I data Port I direction MPX Note) PI5 is schmitt input RD (Port I) PI5...To serial CH0
PI5/SCK0 PI6/SO0
MPX
Hi-Z
IP
Data bus
2 pins Port H
Schmitt input
Port H data
PH0/KR0 to PH2/KR2
Data bus
Port H direction
Hi-Z
IP RD (Port H)
3 pins
Key input signal
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CXP881P60
Pin
Circuit format
When reset
EXTAL XTAL
EXTAL
IP
* Shows the circuit composition during oscillation. * Feedback resistor is removed during stop.
Hi-Z
2 pins
XTAL
* Shows the circuit composition during oscillation.
TEX TX
TEX
IP
* Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs "L" level and TX pin outputs "H" level.
Oscillation
2 pins
TX
RST
Pull-up resistor Schmitt input
Low level
1 pin
IP
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CXP881P60
Absolute Maximum Ratings Item Symbol VDD Supply voltage Vpp AVDD AVSS Input voltage Output voltage Display output voltage VIN VOUT VOD IOH High level output current IODH1 IODH2 High level total output current Low level output current IOH IODH IOL Rating -0.3 to +7.0 -0.3 to +13 AVss to +7.01 -0.3 to +0.3 -0.3 to +7.02 -0.3 to +7.02 VDD-40 to VDD+0.3 -5 -15 -35 -50 -100 15 130 -10 to +75 -55 to +150 600 Unit V V V V V V V mA mA mA mA mA mA mA C C mW Total for all outputs Incorporated PROM Remarks
(Vss=0V)
As P-channel transistor is open drain, VDD is reference. All pins excluding display outputs (value per pin)3 Display outputs S0 to S7 (value per pin) Display outputs T0 to T7, and T8/S15 to T15/S8 (value per pin) Total for all pins excluding display outputs Total for all display outputs
Low level total output current IOL Operating temperature Storage temperature Allowable power dissipation Topr Tstg PD
1) AVDD and VDD should be set to the same voltage. 2) VIN and VOUT should not exceed VDD+0.3V. 3) It specifies output current of general-purpose I/O port. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
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CXP881P60
Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.5 Vpp Analog power supply AVDD VIH High level input voltage VIHS VIHTS VIHEX VIL Low level input voltage VILS VILTS VILEX Operating temperature Topr Max. 5.5 5.5 5.5 5.5 V V V V V V V V V V C Unit Remarks
(Vss=0V)
Guaranteed range during high speed mode (1/2 dividing clock) operation V Guaranteed range during low speed mode (1/16 dividing clock) operation Guaranteed operation range by TEX clock Guaranteed data hold operation range during STOP 7 1 2 CMOS schmitt input3 TTL schmitt input4 EXTAL pin5 TEX pin6 2 CMOS schmitt input3 TTL schmitt input4 EXTAL pin5 TEX pin6
VDD Supply voltage
Vpp = VDD 4.5 0.7VDD 0.8VDD 2.2 VDD-0.4 0 0 0 -0.3 -10 5.5 VDD VDD VDD VDD+0.3 0.3VDD 0.2VDD 0.8 0.4 +75
1) AVDD and VDD should be set to the same voltage. 2) Normal input port (each pin of PA1 to PA4, PC, PF0 to PF3, PF5, PF7, PH, PI2, PI3 and PI6), MP pin 3) Each pin of RST, PE0/INT0, PE1/EC0/INT2, PF4/SCK1, PF6/SI1, PI1/RMC, PI4/CS0/NMI/INT1, PI5/SCK0, PI7/SI1, PG0/CFG, PG1/DFG, PG2/DPG, PG3/PBCTL/EC, PG6/EXI0, PG7/EXI1. 4) Each pin of PG4/SYNC0/EC2, PG5/SYNC1. 5) It specifies only when the external clock is input. 6) It specifies only when the external event is input. 7) Vpp and VDD should be set to the same voltage.
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CXP881P60
DC Characteristics Item Symbol Pin Condition
(Ta=-10 to +75C, Vss=0V) Min. 4.0 3.5 0.4 0.6 -8 VDD=4.5V, VOH=VDD-2.5V -20 Typ. Max. Unit V V V V mA mA
High level VOH output voltage Low level VOL output voltage
VDD=4.5V, IOH=-0.5mA PA to PC, PE PF4 to PF7, VDD=4.5V, IOH=-1.2mA PH, VDD=4.5V, IOL=1.8mA PI1 to PI7 VDD=4.5V, IOL=3.6mA S0 to S7
Display output current
IOH
S8/T15 to S15/T8, T0 to T7 S0 to S7, S8/T15 to S15/T8, T0 to T7 S8/T15 to S15/T8, T0 to T7 EXTAL
Open drain output leakage current (P-CH ILOL Tr OFF in state) Pull-down resistor RL
VDD=5.5V, VOL=VDD-35V VFDP=VDD-35V
-20
A
VDD=5V, VOD-VFDP=30V VDD=5.5V, VIH=5.5V VDD=5.5V, VIL=0.4V VDD=5.5V, VIH=5.5V VDD=5.5V, VIL=0.4V
60 0.5 -0.5 0.1 -0.1 -1.5
100
270 40 -40 10 -10 -400
k A A A A A
IIHE Input current
IILE IILR
TEX RST
I/O leakage current
IIZ
PA to PC, PE to PI, AN1 to AN3, VDD=5.5V, VI=0, 5.5V MP 16MHz crystal oscillation (C1=C2=15pF), VDD=5V0.5V2 16MHz crystal oscillation (C1=C2=15pF), VDD=5V0.5V, SLEEP mode VDD, Vss 32kHz crystal oscillation (C1=C2=47pF), VDD=3V0.3V 32kHz crystal oscillation (C1=C2=47pF), VDD=3V0.3V, SLEEP mode VDD=5.5V, STOP mode (32kHz, 16MHz oscillation stop) PA1 to PA4 PC0 to PC7 PE0, PE1 AN0 to AN3 Clock 1MHz PF0 to PF7 0V other than the measured pins PG0 to PG7 PH0 to PH2 PI1 to PI7 28 1.7 0.8 3
10
A
IDD1 IDDS1 Supply current1 IDD2 IDDS2 IDDS3
50 8 2 35 30
mA mA mA A A
Input capacity
CIN
10
20
pF
- 15 -
CXP881P60
1) When entire output pins are open. 2) When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock).
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times System clock frequency Event count clock input pulse width Event count clock input rise and fall times 1) Symbol fC Pin XTAL EXTAL XTAL EXTAL XTAL EXTAL
(Ta=-10 to +75C, VDD=4.5 to 5.5V, Vss=0V) Condition Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Min. 1 28 200 Typ. Max. Unit 16 MHz ns ns ns 20 ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
EC0, EC1, Fig. 3 EC2 EC0, EC1, Fig. 3 EC2 TEX TX TEX TEX VDD=2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3
tsys+2001
32.768
kHz
tTL, tTH tTR, tTF
10 20
s ms
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2
bits (CPU clock selection). tsys [ns]=2000/fc (Upper 2 bits="00"), 4000/fc (Upper 2 bits="01"), 16000/fc (Upper 2 bits="11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL XTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied condition
Crystal oscillation Ceramic oscillation External clock 32kHz clock appied condition Crystal oscillation
EXTAL C1
XTAL C2
EXTAL
XTAL C1
TEX
TX C2
74HC04
- 16 -
CXP881P60
Fig. 3. Event count clock timing
TEX EC0 EC1 EC2 0.8VDD 0.2VDD
tEH tTH
tEF tTF
tEL tTL
tER tTR
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 floating delay time CS0 SO0 delay time CS0 SO0 floating delay time CS0 high level width SCK0 cycle time SCK0 high and low level widths SI0 input set-up time (against SCK0 ) SI0 input hold time (against SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0
(Ta=-10 to +75C, VDD=4.5 to 5.5V, Vss=0V) Condition Chip select transfer mode (SCK0=output mode) Chip select transfer mode (SCK0=output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SO0 SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys+200 tsys+200 tsys+200 tsys+200 tsys+200
2tsys+200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys+100
8000/fc-50 100 200
tsys+200
100
tsys+200
100
ns ns
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection). tsys [ns]=2000/fc (Upper 2 bits="00"), 4000/fc (Upper 2 bits="01"), 16000/fc (Upper 2 bits="11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF +1TTL.
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CXP881P60
Fig. 4. Serial transfer timing (CH0)
tWHCS
0.8VDD CS0 0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
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CXP881P60
Serial transfer (CH1) Item SCK1 cycle time SCK1 high and low level widths SI1 input set-up time (against SCK1 ) SI1 input hold time (against SCK1 ) SCK1 SO1 delay time Symbol Pin SCK1 Condition Input mode Output mode SCK1 Input mode Output mode SI1
(Ta=-10 to +75C, VDD=4.5 to 5.5V, Vss=0V) Min. 1000 16000/fc 400 8000/fc-50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
SCK1 input mode SCK1 output mode
SI1
SCK1 input mode SCK1output mode
SO1
SCK1 input mode SCK1 output mode
Note) The load of SCK1 output mode and SO1 output delay time is 50pF +1TTL.
Fig. 5. Serial transfer timing (CH1)
tKCY tKL tKH
0.8VDD SCK1 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
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CXP881P60
(3) A/D converter characteristics (Ta=-10 to +75C, VDD=AVDD=4.5 to 5.5V, AVREF=4.0 to AVDD, Vss=AVss=0V) Item Resolution Linearity error Absolute error Conversion time Sampling time Reference input voltage Analog input voltage
Only for A/D converter operation Ta=25C VDD=AVDD=AVREF=5.0V VSS=AVss=0V
Symbol
Pin
Condition
Min.
Typ.
Max. 8 1 2
Unit Bits LSB LSB s s
tCONV tSAMP
VREF VIAN AVREF AN0 to AN7 Operation mode AVREF=4.0 to 5.5V
160/fADC 12/fADC AVDD-0.5 0 0.6 AVDD AVREF 1.0
V V mA
AVREF current
IREF
AVREF
SLEEP mode STOP mode 32kHz operation mode
10
A
Fig. 6. Definitions of A/D converter terms
FFH FEH
Digital conversion value
The value of fADC is as follows by selecting ADC operation clock (MSC: 01FFH bit 0). When PS2 is selected, fADC=fc/2 When PS1 is selected, fADC=fc
Linearity error 01H 00H VZT Analog input VFT
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CXP881P60
(4) Interruption, reset input Item External interruption high and low level widths Reset input low level width Symbol
(Ta=-10 to +75C, VDD=4.5 to 5.5V, Vss=0V) Pin INT0 INT1 INT2 NMI RST Condition Min. Max. Unit
tIH tIL tRSL
1
s
32/fc
s
Fig. 7. Interruption input timing
tIH INT0 INT1 INT2 NMI (Falling edge) tIL
0.8VDD 0.2VDD
Fig. 8. Reset input timing
tRSL
RST 0.2VDD
(5) Others Item CFG input high and low level widths DFG input high and low level widths DPG minimum pulse width DPG minimum removal time PBCTL input high and low level widths EXI input high and low level widths Symbol Pin CFG DFG DPG DPG PBCTL EXI0 EXI1 Condition
(Ta=-10 to +75C, VDD=4.5 to 5.5V, Vss=0V) Min. Max. Unit ns ns ns ns ns ns
tCFH tCFL tDFH tDFL tDPW trem tCTH tCTL tEIH tEIL
tFRC x 24+200 tFRC x 16+200 tFRC x 8+200 tFRC x 16+200 tsys=2000/fc tsys=2000/fc tFRC x 8+tsys+200 tFRC x 8+tsys+200
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits (CPU clock selection). tsys [ns]=2000/fc (Upper 2 bits="00"), 4000/fc (Upper 2 bits="01"), 16000/fc (Upper 2 bits="11") Note 2) tFRC=1000/fc (ns)
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CXP881P60
Fig. 9. Other timings
tCFH
tCFL
0.8VDD CFG 0.2VDD
tDFH
tDFL
0.8VDD DFG 0.2VDD
trem
tDPW
trem
0.8VDD DPG
tCTH
tCTL
0.8VDD PBCTL 0.2VDD
tEIH
tEIL
EXI0 EXI1
0.8VDD 0.2VDD
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CXP881P60
Supplement Fig. 10. Recommended oscillation circuit
(i) (ii)
EXTAL
XTAL Rd
TEX
TX Rd
C1
C2
C1
C2
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
HC-49/U03
10.00 12.00 16.00 8.00 16 (12) 16 (12) 12 12 30 16 (12) 16 (12) 12 12 18 5 5
0
(i)
KINSEKI LTD.
HC-49/U (-S)
10.00 12.00 16.00
0 0 0 470k (ii) (i)
P3
32.768kHz
Product list Option item Package Mask product 100-pin plastic QFP 16K/20K/24K (CXP88216/88220/88224) 32K/40K (CXP88132/88140) 52K/60K (CXP88152/88160) Existent/non-existent CMOS schmitt /TTL schmitt Existent/non-existent CXP881P60Q-1100-pin plastic QFP 2
ROM capacitance
PROM 60K bytes
Reset pin pull-up resistor Input circuit format1 High voltage drive output port pull-down resistor
Existent TTL schmitt Existent3
1 In PG4/SYNC0/EC2 pin and PG5/SYNC1 pin only. 2 OEM No. 3 No pull-down resistor for PD0/S0 to PD7/S7 pins. - 23 -
CXP881P60
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical)
IDD vs. fc
(VDD = 5.0V, Ta = 25C, Typical)
1/2 dividing mode 10 1/4 dividing mode 1/16 dividing mode 32kHz mode (instruction) SLEEP mode 40
IDD - Supply current [mA]
0.1
32kHz SLEEP mode
IDD - Supply current [mA]
1
1/2 dividing mode
20
1/4 dividing mode
0.01 1/16 dividing mode
0.001 0
SLEEP mode
2.5
3
4 5 VDD - Supply voltage [V]
6
5 10 fc - System clock [MHz]
15
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CXP881P60
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 10
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
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