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H
Low Input Current Logic Gate Optocouplers Technical Data
HCPL-2200 HCPL-2219
Features
* 2.5 kV/s Minimum Common Mode Rejection (CMR) at VCM = 400 V (HCPL-2219) * Compatible with LSTTL, TTL, and CMOS Logic * Wide VCC Range (4.5 to 20 V) * 2.5 Mbd Guaranteed over Temperature * Low Input Current (1.6 mA) * Three State Output (No Pullup Resistor Required) * Guaranteed Performance from 0C to 85C * Hysteresis * Safety Approval UL Recognized -2500 V rms for 1 minute CSA Approved VDE 0884 Approved with VIORM = 630 V peak (HCPL-2219 Option 060 Only) * MIL-STD-1772 Version Available (HCPL-5200/1)
* Ground Loop Elimination * Pulse Transformer Replacement * Isolated Buss Driver * High Speed Line Receiver
Description
The HCPL-2200/2219 are optically coupled logic gates that combine a GaAsP LED and an integrated high gain photo detector. The detector has a three state output stage and has a
detector threshold with hysteresis. The three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. The hysteresis provides differential mode noise immunity and eliminates the potential for output signal chatter. A superior internal shield on the HCPL-2219 guarantees common mode transient immunity of 2.5 kV/s at a common mode voltage of 400 volts.
Functional Diagram
NC 1 ANODE 2 CATHODE 3 NC 4 8 VCC 7 VO 6 VE 5 GND
TRUTH TABLE (POSITIVE LOGIC) LED ENABLE OUTPUT ON Z H OFF Z H ON H L OFF L L
SHIELD
Applications
* Isolation of High Speed Logic Systems * Computer-Peripheral Interfaces * Microprocessor System Interfaces
A 0.1 F bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
1-120 5965-3596E
The Electrical and Switching Characteristics of the HCPL2200/2219 are guaranteed over the temperature range of 0C to 85C and a VCC range of 4.5 volts to 20 volts. Low IF and wide VCC range allow compatibility with
TTL, LSTTL, and CMOS logic and result in lower power consumption compared to other high speed optocouplers. Logic signals are transmitted with a typical propagation delay of 160 nsec.
The HCPL-2200/2219 are useful for isolating high speed logic interfaces, buffering of input and output lines, and implementing isolated line receivers in high noise environments.
Selection Guide
Minimum CMR dV/dt (V/s) 1,000 VCM (V) 50 Input OnCurrent (mA) 1.6 8-Pin DIP (300 Mil) Single Dual Channel Channel Package Package HCPL-2200[1] HCPL-2201 HCPL-2202 HCPL-2231 HCPL-2219[1] HCPL-2211 HCPL-2212 HCPL-2232 Small-Outline Widebody SO-8 (400 Mil) Hermetic Single Single Single and Dual Channel Channel Channel Package Package Packages HCPL-0201 HCNW2201
2,500 5,000[2]
400 300[2]
1.8 1.6 1.6 1.8 2.0
HCPL-0211
HCNW2211
1,000
50
HCPL-52XX HCPL-62XX
Notes: 1. HCPL-2200/2219 devices include output enable/disable functionality. 2. Minimum CMR of 10 kV/s with VCM = 1000 V can be achieved with input current, IF, of 5 mA.
Ordering Information
Specify Part Number followed by Option Number (if desired). Example: HCPL-2219#XXX 060 = VDE 0884 VIORM = 630 Vpeak Option* 300 = Gull Wing Surface Mount Option 500 = Tape and Reel Packaging Option Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information.
*For HCPL-2219 only.
Schematic
IF + VF - 2
ICC 8 IO 7 IE 6 SHIELD 5 VCC
VO VE GND
3
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Package Outline Drawings
8-Pin DIP Package
9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 6 5 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010)
OPTION CODE* DATE CODE
HP XXXXZ YYWW RU 1 1.19 (0.047) MAX. 2 3 4
UL RECOGNITION
1.78 (0.070) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
5 TYP. 4.70 (0.185) MAX.
0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED.
1.080 0.320 (0.043 0.013)
0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010)
8-Pin DIP Package with Gull Wing Surface Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
8 7 6 5
1.016 (0.040) 1.194 (0.047)
4.826 TYP. (0.190) 6.350 0.25 (0.250 0.010) 9.398 (0.370) 9.906 (0.390)
1
2
3
4
1.194 (0.047) 1.778 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.381 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
4.19 MAX. (0.165)
+ 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
1.080 0.320 (0.043 0.013) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 0.25 (0.025 0.010)
12 NOM.
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Maximum Solder Reflow Thermal Profile
260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 10 11 12 T = 145C, 1C/SEC T = 115C, 0.3C/SEC
TEMPERATURE - C
T = 100C, 1.5C/SEC
TIME - MINUTES
Note: Use of nonchlorine activated fluxes is highly recommended.
Regulatory Information
The HCPL-2200/2219 have been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. VDE Approved according to VDE 0884/06.92. (HCPL-2219 Option 060 Only)
Insulation and Safety Related Specifications
Parameter Symbol Value Units Conditions Min. External Air Gap L(IO1) 7.1 mm Measured from input terminals to output terminals, (External Clearance) shortest distance through air. Min. External L(IO2) 7.4 mm Measured from input terminals to output terminals, Tracking Path shortest distance path along body. (External Creepage) Minimum Internal 0.08 mm Through insulation distance, conductor to conductor, Plastic Gap usually the direct distance between the photoemitter (Internal Clearance) and photodetector inside the optocoupler cavity. Tracking Resistance CTI 200 V DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance with CECC 00802.
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VDE 0884 Insulation Related Characteristics (HCPL-2219 OPTION 060 ONLY)
Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 300 V rms for rated mains voltage 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 12, Thermal Derating curve.) Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V VIORM VPR Symbol Characteristic I-IV I-III 55/85/21 2 630 1181 V peak V peak Units
VPR
945
V peak
VIOTM
6000
V peak
TS IS,INPUT PS,OUTPUT RS
175 230 600 109
C mA mW
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
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Absolute Maximum Ratings
(No Derating Required up to 70C) Parameter Storage Temperature Operating Temperature Average Forward Input Current Peak Transient Input Current ( 1 s Pulse Width, 300 pps) Reverse Input Voltage Average Output Current Supply Voltage Three State Enable Voltage Output Voltage Total Package Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile Symbol TS TA IF(AVG) IF(TRAN) Min. -55 -40 Max. 125 85 10 1.0 Units C C mA A Note 1
VR 5 V IO 25 mA VCC 0 20 V VE -0.5 20 V VO -0.5 20 V PT 210 mW 260C for 10 sec., 1.6 mm below seating plane See Package Outline Drawings section
1
Recommended Operating Conditions
Parameter Power Supply Voltage Enable Voltage High Enable Voltage Low Forward Input Current Forward Input Current Operating Temperature Fan Out Symbol VCC VEH VEL IF(ON) IF(OFF) TA N Min. 4.5 2.0 0 1.6* - 0 Max. 20 20 0.8 5 0.1 85[1] 4 Units V V V mA mA C TTL Loads
*The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be used to permit at least a 20% CTR degradation guardband.
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Electrical Specifications
For 0C TA[1] 85C, 4.5 V VCC 20 V, 1.6 mA IF(ON) 5 mA, 2.0 V VEH 20 V, 0.0 V VEL 0.8 V, 0 mA IF(OFF) 0.1 mA. All Typicals at TA = 25C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified. See Note 7. Parameter Sym. Logic Low VOL Output Voltage Logic High VOH Output Voltage Output Leakage IOHH Current (VOUT > VCC) Logic High Enable Voltage Logic Low Enable Voltage Logic High Enable Current Logic Low Enable Current Logic Low Supply Current Logic High Supply Current High Impedance State Output Current VEH VEL IEH Min. Typ. Max. Units Test Conditions 0.5 V IOL = 6.4 mA (4 TTL Loads) 2.4 * 100 500 2.0 0.8 20 100 0.004 250 -0.32 4.5 5.25 ICCH 2.7 3.1 IOZL IOZH 6.0 7.5 4.5 6.0 -20 20 100 500 25 40 IOSH -10 -25 IHYS VF BVR VF TA CIN 5 -1.7 0.12 1.5 1.7 1.75 V A A V V A A A mA mA mA mA mA A A A A mA mA mA mA mA V V VEN = 2.7 V VEN = 5.5 V VEN = 20 V VEN = 0.4 V VCC = 5.5 V VCC = 20 V VCC = 5.5 V VCC = 20 V VO = 0.4 V VO = 2.4 V VO = 5.5 V VO = 20 V IF = 0 mA IO = Open VE = Don't Care IF = 5 mA IO = Open VE = Don't Care VEN = 2 V, IF = 5 mA VEN = 2 V, IF = 5 mA 2 IOH = -2.6 mA VO = 5.5 V VO = 20 V *VOH = VCC - 2.1 V IF = 5 mA VCC = 4.5 V Fig. Note 1 2
IEL ICCL
Logic Low Short Circuit Output Current Logic High Short Circuit Output Current Input Current Hysteresis Input Forward Voltage Input Reverse Breakdown Voltage Input Diode Temperature Coefficient Input Capacitance
IOSL
VO = VCC = 5.5 V IF = 0 mA VO = VCC = 20 V VCC = 5.5 V VCC = 20 V VCC = 5 V TA = 25C IR = 10 A IF = 5 mA IF = 5 mA, VO = GND 3 4
2
mV/C IF = 5 mA
60
pF
f = 1 MHz, VF = 0 V, Pins 2 and 3
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Switching Specifications (AC)
For 0C TA[1] 85C, 4.5 V VCC 20 V, 1.6 mA IF(ON) 5 mA, 0.0 mA IF(OFF) 0.1 mA. All Typicals at TA = 25C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified. Parameter Propagation Delay Time to Logic Low Output Level Propagation Delay Time to Logic High Output Level Output Enable Time to Logic High Output Enable Time to Logic Low Output Disable Time from Logic High Output Disable Time from Logic Low Output Rise Time (10-90%) Output Fall Time (90-10%) Sym. tPHL tPLH tPZH tPZL tPHZ tPLZ tr tf Min. Typ. Max. Units Test Conditions 210 ns Without Peaking Capacitor 160 300 With Peaking Capacitor 170 ns Without Peaking Capacitor 115 300 With Peaking Capacitor 25 ns 28 105 60 55 15 ns ns ns ns ns Fig. Note 5, 6 4, 5 5, 6 7, 9 7, 8 7, 9 7, 8 5, 10 5, 10 4, 5
Parameter Logic High Common Mode Transient Immunity Logic Low Common Mode Transient Immunity
Sym. |CMH|
Device HCPL-2200 HCPL-2219
Min. 1,000 2,500 1,000 2,500
Units V/s V/s V/s V/s
Test Conditions IF = 1.6 mA |VCM| = 50 V VCC = 5 V TA = 25C |VCM| = 400 V |VCM| = 50 V |VCM| = 400 V VF = 0 V VCC = 5 V TA = 25C
Fig. 11
Note 6
|CML|
HCPL-2200 HCPL-2219
11
6
Package Characteristics
Parameter Input-Output Momentary Withstand Voltage* Input-Output Resistance Input-Output Capacitance Sym. VISO RI-O CI-O Min. 2500 Typ. Max. Units V rms pF Test Conditions RH 50%, t = 1 min., TA = 25C VI-O = 500 VDC f = 1 MHz, VI-O = 0 VDC Fig. Note 3, 8 3 3
1012 0.6
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage," publication number 5963-2203E.
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Notes: 1. Derate total package power dissipation, PT, linearly above 70C free air temperature at a rate of 4.5 mW/C. 2. Duration of output short circuit time should not exceed 10 ms. 3. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 4. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The tPHL propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing edge of the output pulse. 5. When the peaking capacitor is omitted, propagation delay times may increase by 100 ns. 6. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be
IOH - HIGH LEVEL OUTPUT CURRENT - mA
sustained with the output voltage in the logic high state (VO > 2.0 V). 7. Use of a 0.1 F bypass capacitor connected between pins 5 and 8 is recommended. 8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 3000 V rms for one second (leakage detection current limit, II-O 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.
VOL - LOW LEVEL OUTPUT VOLTAGE - V
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -60 -40 -20 0 20 40 60 80 100 VCC = 4.5 V IF = 0 mA VO = 6.4 mA
0
5
VO - OUTPUT VOLTAGE - V
VCC = 4.5 V IF = 5 mA VO = 2.7 V
-1 -2 -3 -4 -5 VO = 2.4 V -6 -7 -8 -60 -40 -20 0 20
VCC = 4.5 V TA = 25 C 4
3 IOH = -2.6 mA 2
1 IOL = 6.4 mA 0 0 0.5 1.0 1.5 2.0
40
60
80 100
TA - TEMPERATURE - C
TA - TEMPERATURE - C
IF - INPUT CURRENT - mA
Figure 1. Typical Logic Low Output Voltage vs. Temperature.
Figure 2. Typical Logic High Output Current vs. Temperature.
VCC
Figure 3. Output Voltage vs. Forward Input Current.
PULSE GEN. tr = tf = 5 ns f = 100 kHz 10 % DUTY CYCLE VO = 5 V IF INPUT MONITORING NODE
HCPL-2200
1 2 3
OUTPUT VO MONITORING NODE
5V D1 619
VCC 8
7 6
C2 = 15 pF 5 k
D2 D3 D4
1000
IF - FORWARD CURRENT - mA
R1
TA = 25 C 100 10 1.0 0.1 0.01 IF + VF -
4 C1 = 120 pF
GND 5
THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C1 AND C2. 2.15 k 1.10 k 681 RI 5 mA IF (ON) 1.6 mA 3 mA ALL DIODES ARE 1N916 OR 1N3064.
INPUT IF
1.2 1.3 1.4 1.5
0.001 1.1
IF (ON) 50 % IF (ON) 0 mA tPLH tPHL
VF - FORWARD VOLTAGE - V
OUTPUT VO
VOH 1.3 V VOL
Figure 4. Typical Input Diode Forward Characteristic.
Figure 5. Test Circuit for tPLH, tPHL, tr, and tf.
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250
tP - PROPAGATION DELAY - ns
200
VCC = 5 V C1 (120 pF) PEAKING CAPACITOR IS USED. SEE FIGURE 5.
IF (mA) 5 3 1.6
CL= 15 pF INCLUDING PROBE PULSE AND JIG CAPACITANCES. GENERATOR VCC ZO = 50 tr = tf = 5 ns VO HCPL-2200
1
+5 V
S1 D1 619
150
tPHL
1.6 3 5
VCC 8
7 6
IF
2 3
100
tPLH
CL 5 k
D2 D3 D4 S2
50 -60 -40 -20
4
GND 5
0
20
40
60
80 100
TA - TEMPERATURE - C
INPUT VC MONITORING NODE D1-4 ARE 1N916 OR 1N3064.
Figure 6. Typical Propagation Delays vs. Temperature.
INPUT VE
tPZL 1.3 V
tPLZ 0.5 V 0.5 V 1.3 V 0V tPHZ
3.0 V 1.3 V 0V S1 AND S2 CLOSED VOL VOH 1.5 V S1 AND S2 CLOSED
OUTPUT S1 CLOSED VO S2 OPEN tPZH OUTPUT VO S1 OPEN S2 CLOSED
Figure 7. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL.
Tp - ENABLE PROPAGATION DELAY - ns
tP - ENABLE PROPAGATION DELAY - ns
100 CL = 15 pF 80
VCC 20 V 4.5 V
200
CL = 15 pF
tr, tf - RISE, FALL TIME - ns
120
VCC 150
tPHZ
100 80 60
VCC = 5 V C2 = 15 pF
20 V 4.5 V
60
tPLZ 20 V
100
40 tPZL 20 0 -60 -40 -20
4.5 V
tr
20 V 50
tPZH
40 20
tf
4.5 V
0
20
40
60
80 100
0 -60 -40 -20
0
20
40
60
80 100
0 -60 -40 -20
0
20
40
60
80 100
TA - TEMPERATURE - C
TA - TEMPERATURE - C
TA - TEMPERATURE - C
Figure 8. Typical Logic Low Enable Propagation Delay vs. Temperature.
Figure 9. Typical Logic High Enable Propagation Delay vs. Temperature.
Figure 10. Typical Rise, Fall Time vs. Temperature.
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OUTPUT POWER - PS, INPUT CURRENT - IS
HCPL-2200
A B 1 2 3
VCC OUTPUT VO MONITORING NODE 0.1 F BYPASS
800 700 600 500 400 300 200 100 0 0
HCPL-2219 OPTION 060 ONLY PS (mW) IS (mA)
VCC 8
7 6 5
RIN
VFF
4
GND VCM -
PULSE GENERATOR +
VCM 0V VOH OUTPUT VO VOL * SEE NOTE 6.
50 V SWITCH AT A: IF = 1.6 mA VO (MIN.)* SWITCH AT B: IF = 0 mA VO (MAX.)*
25
50
75 100 125 150 175 200
TS - CASE TEMPERATURE - C
Figure 12. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884.
Figure 11. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
VCC1 (+5 V)
VCC1 (+5 V) 1.1 k 120 pF HCPL-2200 1 2 DATA INPUT TOTEM POLE OUTPUT GATE
1 2
VCC2 (+5 V) DATA OUTPUT
120 pF (OPTIONAL*) 1.1 k 1 2 HCPL-2200 VCC 8 7 6 GND 5
VCC2 (4.5 TO 20 V)
VCC
8 7 6
RL
CMOS
DATA OUTPUT
3 TTL OR LSTTL 4 GND
5
UP TO 16 LSTTL LOADS OR 4 TTL LOADS
DATA INPUT TOTEM POLE OUTPUT GATE
1
3 TTL OR LSTTL 4 VCC2 5V 10 V 15 V 20 V RL 1.1 K 2.37 K 3.83 K 5.11 K
2
Figure 13. Recommended LSTTL to LSTTL Circuit.
Figure 14. LSTTL to CMOS Interface Circuit.
VCC (+5 V)
VCC1 (+5 V) 1.1 k 1 DATA INPUT TTL OR LSTTL D1 3 4 GND 6 5 2 HCPL-2200 VCC 8 7
120 pF (OPTIONAL*) 1.1 k 1 2 4.7 k HCPL-2200 VCC 8 7 6 GND 5
DATA INPUT OPEN COLLECTOR GATE
3 TTL OR LSTTL 4
D1 (1N4150) REQUIRED FOR ACTIVE PULL-UP DRIVER.
Figure 15. Recommended LED Drive Circuit.
Figure 16. Series LED Drive with Open Collector Gate (4.7 k Resistor Shunts IOH from the LED).
*The 120 pF capacitor may be omitted in applications where 500 ns propagation delay is sufficient.
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