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MITSUBISHI LSIs MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7, M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S -5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC RAM FAST PAGE MODE 4194304-BIT (262144-WORD BY BY 16-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is small enough for battery back-up application. This device has 2CAS and 1W terminals with a refresh cycle of 512 cycles every 8.2ms.
PIN CONFIGURATION (TOP VIEW)
(5V)VCC DQ1 DQ2 DQ3 DQ4 (5V)VCC DQ5 DQ6 VSS(0V) DQ16 DQ15 DQ14 DQ13 VSS(0V) DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS(0V)
1 2 3 4 5 6 7 8 9
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
FEATURES
Type name
M5M44260CXX-5,-5S M5M44260CXX-6,-6S M5M44260CXX-7,-7S RAS CAS access access time time (max.ns) (max.ns) Address OE access access time time (max.ns) (max.ns) Power Cycle dissipatime tion (min.ns) (typ.mW)
DQ7
DQ8 10 NC 11 NC 12 W 13 RAS 14 NC 15 A0 16 A1 17 A2 18 A3 19
50 60 70
13 15 20
25 30 35
13 15 20
90 110 130
625 550 475
XX=J,TP
Standard 40pin SOJ, 44 pin TSOP (II) Single 5V10% supply Low stand-by power dissipation CMOS Input level 5.5mW (Max) CMOS Input level 550W (Max) * Operating power dissipation M5M44260Cxx-5,-5S 688mW (Max) M5M44260Cxx-6,-6S 605mW (Max) M5M44260Cxx-7,-7S 523mW (Max) Self refresh capability * Self refresh current 150A (Max) Extended refresh capability Extended refresh current 150A (Max) Fast-page mode (512-column random access), Read-modify-write, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities. Early-write mode, LCAS / UCAS and OE to control output buffer impedance 512 refresh cycles every 8.2ms (A0~A8) 512 refresh cycles every 128ms (A0~A8) * Byte or word control for Read/Write operation (2CAS, 1W type) * : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S : option) only
(5V)VCC
20
Outline 40P0K (400mil SOJ)
(5V)VCC DQ1 DQ2 DQ3 DQ4 (5V)VCC DQ5 DQ6 DQ7
1 2 3 4 5 6 7 8 9
44 43 42 41 40 39 38 37 36 35
VSS(0V) DQ16 DQ15 DQ14 DQ13 VSS(0V) DQ12 DQ11 DQ10 DQ9
DQ8 10
APPLICATION
Microcomputer memory, Refresh memory for CRT
NC 13
32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS(0V)
PIN DESCRIPTION
Pin name A0~A8 DQ1~DQ16 RAS LCAS UCAS W OE VCC VSS 1 Function Address inputs Data inputs / outputs Row address strobe input Lower byte control column address strobe input Upper byte control column address strobe input Write control input Output enable input Power supply (+5V) Ground (0V)
NC 14 W
15
RAS 16 NC 17 A0 18 A1 19 A2 20 A3 21 (5V)VCC 22
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC: NO CONNECTION
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to normal read,write and read-modify-write operations the M5M44260CJ, TP provides a number of other functions, e.g., fast page mode, RAS-only refresh and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs Operation Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write RAS only refresh Hidden refresh
CAS before RAS (Extended *) refresh
Input/Output OE ACT ACT ACT NAC NAC NAC DNC ACT DNC DNC DNC
Row address Column address DQ1~ DQ8
RAS ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT NAC
LCAS ACT NAC ACT ACT NAC ACT NAC ACT ACT ACT DNC
UCAS NAC ACT ACT NAC ACT ACT NAC ACT ACT ACT DNC
Self refresh * Stand-by
W NAC NAC NAC ACT ACT ACT DNC DNC DNC DNC DNC
Refresh Remark DQ9~ DQ16 OPN DOUT DOUT DNC DIN DIN OPN DOUT OPN OPN OPN YES YES YES YES YES YES YES YES YES YES No Fast page mode identical
APD APD APD APD APD APD APD DNC DNC DNC DNC
APD APD APD APD APD APD DNC DNC DNC DNC DNC
DOUT OPN DOUT DIN DNC DIN OPN DOUT OPN OPN OPN
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
BLOCK DIAGRAM
ROW ADDRESS STROBE INPUT RAS LOWER BYTE CONTROL COLUMN ADDRESS LCAS STROBE INPUT UPPER BYTE CONTROL UCAS COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT
VCC (5V)
CLOCK GENERATOR CIRCUIT
VSS (0V) LOWER UPPER
(8)LOWER DATA IN BUFFER
DQ1 DQ2 DQ8
W
(8)LOWER DATA OUT BUFFER
LOWER DATA INPUTS / OUTPUTS
VCC (5V) VSS (0V)
A0~A8 COLUMN DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8
(8)UPPER DATA IN BUFFER
SENSE REFRESH AMPLIFIER & I /O CONTROL
DQ9 DQ10 DQ16
ADDRESS INPUTS
ROW & COLUMN ADDRESS BUFFER
UPPER DATA INPUTS / OUTPUTS
ROW A0~ A8 DECODER
MEMORY CELL (4194304 BITS)
(8)UPPER DATA OUT BUFFER
VCC (5V) VSS (0V)
OE
OUTPUT ENABLE INPUT
2
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to VSS Ratings -1~7 -1~7 -1~7 50 1000 0~70 -65~150
(Note 1)
Ta=25C
Unit V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70C, unless otherwise noted)
Symbol VCC VSS VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Min 4.5 0 2.4 -0.5 * * Limits Nom 5.0 0 Max 5.5 0 6.0 0.8
Unit V V V V
Note 1 : All voltage values are with respect to VSS. * * : VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss.)
ELECTRICAL CHARACTERISTICS (Ta=0~70C , VCC=5V10%, VSS=0V, unless otherwise noted)
Symbol VOH VOL IOZ II ICC1(AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from Vcc, operating M5M44260C-5,-5S M5M44260C-6,-6S Test conditions IOH=-5mA IOL=4.2mA Q floating 0V VOUT 5.5V 0V VIN +6.0V, Other inputs pins=0V RAS, CAS cycling tRC=tWC=min. output open RAS= CAS =VIH, output open ICC2 Supply current from VCC, stand-by (Note 6) RAS= CAS VCC -0.5V output open RAS cycling, CAS=VIH tRC=min. output open RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. output open RAS cycling CAS 0.2V or CAS before RAS refresh cycling RAS 0.2V or VCC-0.2V CAS 0.2V or VCC-0.2V W 0.2V or VCC-0.2V OE 0.2V or VCC-0.2V A0~A8 0.2V or VCC-0.2V, DQ=open tRC=250s, tRAS=tRAS min~1s RAS=CAS 0.2V output open
(Note 2)
Min 2.4 0 -10 -10
Limits Typ
Max VCC 0.4 10 10 125 110 95 2 1.0 0.1 * 125 110 95 125 110 95 115 100 85
Unit V V A A mA
(Note 3,4,5) M5M44260C-7,-7S
mA
ICC3(AV)
Average supply current M5M44260C-5,-5S from Vcc, RAS only M5M44260C-6,-6S refresh mode (Note 3,5) M5M44260C-7,-7S Average supply current M5M44260C-5,-5S from Vcc M5M44260C-6,-6S Fast page mode (Note 3,4,5) M5M44260C-7,-7S Average supply current M5M44260C-5,-5S from Vcc CAS before RAS refresh M5M44260C-6,-6S (Note 3,5) M5M44260C-7,-7S mode
mA
ICC4(AV)
mA
ICC6(AV)
mA
ICC8(AV) *
Average supply current from VCC Extended-refresh mode
150
A
(Note 6)
ICC9(AV) *
Average supply current from VCC Self-refresh mode
(Note 6)
150
A
3
Note 2: Current flowing into an IC is positive, out is negative. 3: ICC1 (AV), ICC3 (AV), ICC4 (AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH. M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70C , VCC=5V10%, VSS=0V, unless otherwise noted)
Symbol CI (A) CI (CLK) CI / O Parameter Input capacitance, address inputs Input capacitance, clock inputs Input/Output capacitance, data ports Test conditions VI=VSS f=1MHz VI=25mVrms Min Limits Typ Max 5 7 7 Unit pF pF pF
SWITCHING CHARACTERISTICS (Ta=0~70C, VCC=5V10%, Vss=0V, unless otherwise noted, see notes 6,13,14)
Limits Symbol tCAC tRAC tAA tCPA tOEA tCLZ tOFF tOEZ Parameter Access time from CAS Access time from RAS Columu address access time Access time from CAS precharge Access time from OE Output low impedance time from CAS low Output disable time after CAS high Output disable time after OE high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 7) (Note 12) (Note 12)
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit ns ns ns ns ns ns ns ns
Min
Max 13 50 25 30 13 13 13
Min
Max 15 60 30 35 15 15 15
Min
Max 20 70 35 40 20 20 20
5
5
5
Note 6: An initial pause of 500 s is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh cycles). Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 2TTL loads and 100pF. 8: Assumes that tRCD tRCD(max) and tASC tASC(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT 10 A ) and is not reference to VOH(min) or VOL(max).
4
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Fast-Page Mode Cycles)
(Ta=0~70C, VCC=5V10%, VSS=0V, unless otherwise noted, see notes 6,13,14) Limits Symbol tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD tT Parameter Refresh cycle time Refresh cycle time * RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data Transition time
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min
Max 8.2 128 37
Min
Max 8.2 128 45
Min
Max 8.2 128 50
(Note 15)
(Note 16) (Note 17)
(Note 18) (Note 18) (Note 19) (Note 19) (Note 20)
30 18 5 0 10 13 0 0 8 13 0 0 13 13 1
25 7
50
40 20 5 0 10 15 0 0 10 15 0 0 15 15 1
30 10
50
50 20 5 0 10 15 0 0 10 15 0 0 20 20 1
35 10
50
Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. 16: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 17: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 18: Either tDZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH Parameter
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns
Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Read hold time after CAS high Read hold time after RAS high Column address to RAS hold time CAS hold time after OE low RAS hold time after OE low Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
(Note 21) (Note 21)
Min 90 50 13 50 13 0 0 0 25 13 13
Max 10000 10000
Min 110 60 15 60 15 0 0 0 30 15 15
Max 10000 10000
Min 130 70 20 70 20 0 0 0 35 20 20
Max 10000 10000
5
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH Parameter Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low OE hold time after W low
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
(Note 23)
Min 90 50 13 50 13 0 8 13 13 8 0 8 13
Max 10000 10000
Min 110 60 15 60 15 0 10 15 15 10 0 10 15
Max 10000 10000
Min 130 70 20 70 20 0 15 20 20 15 0 15 20
Max 10000 10000
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tWP tDS tDH tOEH Parameter Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low OE hold time after W low (Note 22)
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Note 23) (Note 23) (Note 23)
Min 126 86 49 86 49 0 31 68 43 13 13 8 0 8 13
Max 10000 10000
Min 150 100 55 100 55 0 35 80 50 15 15 10 0 10 15
Max 10000 10000
Min 180 120 70 120 70 0 45 95 60 20 20 15 0 15 20
Max 10000 10000
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 23: tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD(min), tAWD tAWD(min) and tCPWD tCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
6
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle)
Symbol tPC tPRWC tRAS tCP tCPRH tCPWD Parameter Fast page mode read/write cycle time Fast page mode read write/read modify write cycle time RAS low pulse width for read or write cycle (Note 25) (Note 26) CAS high pulse width RAS hold time after CAS precharge Delay time, CAS precharge to W low (Note 23)
(Note 24)
Limits
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit ns ns ns ns ns ns
Min 35 71 85 8 30 48
Max
100000 12
Min 40 80 100 10 35 55
Max
100000 15
Min 45 95 115 10 40 65
Max
100000 15
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 25: tRAS(min) is specified as two cycles of CAS input are performed. 26: tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle, Extended Refresh Cycle *
Symbol tCSR tCHR tCAS Parameter CAS setup time before RAS low CAS hold time after RAS low CAS low pulse width
(Note 27)
Limits
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit ns ns ns
Min 5 10 20
Max
Min 5 10 20
Max
Min 5 15 25
Max
Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Self Refresh Cycle *
Symbol tRASS tRPS tCHS
(Note 28)
Limits Parameter CBR self refresh RAS low pulse width CBR self refresh RAS high precharge time CBR self refresh CAS hold time
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Unit s ns ns
Min 100 90 -50
Max
Min 100 110 -50
Max
Min 100 130 -50
Max
7
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 29)
tRC tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tRAD tASR A0~A8 VIH VIL tRAH tASC tCAH
COLUMN ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tRPC
tCRP
tRAL tASR
ROW ADDRESS
ROW ADDRESS
tRRH tRCS W VIH VIL tDZC DQ1~DQ16 (INPUTS) VIH VIL tCAC tAA tCLZ DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z Hi-Z DATA VALID Hi-Z
tRCH
tCDD
tOFF
tRAC tDZO tOEA tOCH
tOEZ tODD
OE
VIH VIL tORH
Note 29
Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max) Indicates the invalid output.
8
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Read Cycle
tRC tRAS VIH VIL tCRP VIH VIL tCPN tRCD tCAS UCAS (or LCAS) tCSH tRSH tRPC tCRP tRP
RAS
LCAS (or UCAS)
VIH VIL tASR VIH VIL tRAH tRAD tASC tCAH tRAL tASR
A0~A8
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRRH tRCS W VIH VIL tRCH
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) tCAC tAA tCLZ DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
Hi-Z
tCDD
Hi-Z
tOFF
Hi-Z
DATA VALID
tRAC tDZO tOEA tOCH
tOEZ tODD
OE
VIH VIL tORH
9
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early write)
tWC tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tASR VIH VIL tRAH tASC tCAH tASR tRCD tCAS tRSH tCPN tCRP tRPC tRP
RAS
A0~A8
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tWCS VIH VIL tDS
tWCH
W
tDH
DQ1~DQ16 (INPUTS)
VIH VIL
DATA VALID
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
10 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Write Cycle (Early write)
tWC tRAS VIH VIL tCSH tCRP VIH VIL tCPN tRCD tCAS UCAS (or LCAS) tRSH tRPC tCRP tRP
RAS
LCAS (or UCAS)
VIH VIL tASR VIH VIL tRAH tASC tCAH
COLUMN ADDRESS
tASR
A0~A8
ROW ADDRESS
ROW ADDRESS
tWCS W VIH VIL
tWCH
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDS DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS)
Hi-Z
tDH
DATA VALID
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
11 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Delayed write)
tWC tRAS RAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tASR VIH VIL tRAH tASC tCAH tASR
COLUMN ADDRESS ROW ADDRESS
tRP
tRPC tRSH tCAS tCPN tCRP
tRCD
A0~A8
ROW ADDRESS
tCWL tRCS W VIH VIL tWCH tDZC DQ1~DQ16 (INPUTS) VIH VIL tCLZ
Hi-Z
tRWL tWP
tDS
tDH
DATA VALID
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO VIH VIL
tOEZ tODD
tOEH
OE
12 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Write Cycle (Delayed write)
tWC tRAS RAS VIH VIL tCSH tCRP VIH VIL tCPN VIH VIL tASR VIH VIL tRAH tASC tCAH tASR
ROW ADDRESS
tRP
tRPC tRSH tCAS tCRP
tRCD
UCAS (or LCAS)
LCAS (or UCAS)
A0~A8
ROW ADDRESS
COLUMN ADDRESS
tRCS VIH VIL
tCWL tRWL tWP
W
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS)
Hi-Z
tWCH tDS
Hi-Z
tDH
DATA VALID
tCLZ
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO
tOEZ tODD
tOEH
OE
VIH VIL
13 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tASR VIH VIL tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tRPC tCRP tRP
RAS
A0~A8
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS W VIH VIL tDZC DQ1~DQ16 (INPUTS) VIH VIL
Hi-Z
tAWD tCWD tRWD
tCWL tRWL tWP
tDS
tDH
DATA VALID
tCAC tAA tCLZ
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
DATA VALID
Hi-Z
tRAC tDZO VIH VIL tOEA
tODD tOEZ
tOEH
OE
14
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH VIL tCSH tRCD tCRP UCAS (or LCAS) VIH VIL tCPN VIH VIL tASR tRAH tRAD tASC tCAH tASR tRSH tCAS tRPC tCRP tRP
RAS
LCAS (or UCAS)
A0~A8
VIH VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH VIL
tAWD tCWD tRWD
tCWL tRWL tWP
W
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL
Hi-Z
tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS)
Hi-Z
tDS
tDH
DATA VALID
tCAC tAA tCLZ
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
DATA VALID
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tOEH
OE
VIH VIL
15
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS RAS VIH VIL tRPC tCRP VIH LCAS/UCAS VIL tASR tRAH tASR tCRP tRP
A0~A8
VIH VIL
ROW ADDRESS
ROW ADDRESS
W
VIH VIL
DQ1~DQ16 (INPUTS)
VIH VIL
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
16
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle, Extended Refresh Cycle *
tRC tRP RAS VIH VIL tRPC tCSR tCHR tRAS tRAS
tRC tRP
tRPC VIH LCAS/UCAS VIL
tCSR
tCHR
tRPC
tCRP
tCPN tASR A0~A8 VIH VIL tRCH W VIH VIL tCDD DQ1~DQ16 (INPUTS) VIH VIL tOFF DQ1~DQ16 VOH (OUTPUTS) VOL tOEZ tODD OE VIH VIL
Hi-Z Hi-Z ROW ADDRESS COLUMN ADDRESS
tRCS
17 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 30)
tRC tRAS RAS VIH VIL tCRP VIH LCAS/UCAS VIL tRAD tASR VIH VIL tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
A0~A8
ROW ADDRESS
tRCS tRAL VIH W VIL tDZC DQ1~DQ16 (INPUTS) VIH VIL tCAC tAA tCLZ
Hi-Z DATA VALID Hi-Z
tRRH
tCDD
tOFF
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
tRAC tDZO VIH VIL
tOEA tORH
tOEZ
tODD
OE
Note 30: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle described above.
18 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tRAD tASR VIH VIL tRAH tASC tCAH
COLUMN ADDRESS1
tRP
RAS
tPC tCAS tCP tCAS tCP
tRSH tCAS
tRCD
tCPRH tASC tCAH tASC tCAH tASR
ROW ADDRESS
A0~A8
ROW ADDRESS
COLUMN ADDRESS2
COLUMN ADDRESS3
tRAL tRCS VIH VIL tDZC VIH VIL tAA tCLZ DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z DATA VALID-1 Hi-Z Hi-Z
tRCH tRCS
tRCH tRRH
tRCH
tRCS
W
tDZC
tDZC
tCDD
DQ1~DQ16 (INPUTS)
Hi-Z
Hi-Z
tCAC tOFF tAA
tCAC tCLZ tOFF
DATA VALID-2 Hi-Z
tCAC tAA tCLZ tOFF
DATA VALID-3
tRAC tDZO VIH VIL
tCPA tOEA tOCH tOEZ tOEA tOCH
tCPA tOEZ tOEA tOCH tOEZ
OE
tODD tDZO
tODD tDZO
tORH
tODD
19 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Byte Read Cycle
tRAS VIH VIL tCSH tCRP UCAS (or LCAS) VIH VIL tRCD tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
RAS
LCAS (or UCAS)
VIH VIL tRAD tASR tRAH tASC tCAH tASC tCAH tCPRH tASC tCAH tASR
ROW ADDRESS
A0~A8
VIH VIL
ROW ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
COLUMN ADDRESS3
tRAL tRCS W VIH VIL tRCH tRCS tRRH tRCH tRCS
tRCH
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) tAA tCLZ DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z Hi-Z
Hi-Z
tDZC
Hi-Z
tDZC
tCDD
tCAC tOFF
tCAC tAA tCLZ tOFF
DATA VALID-2
tCAC tAA tCLZ tOFF
DATA VALID-3
DATA VALID-1
tRAC tDZO tOEA tOCH
tCPA tOEA tOEZ tOCH
tCPA tOEA tOEZ tOCH tOEZ
OE
VIH VIL tODD tDZO tODD tDZO tORH tODD
20
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
RAS
tASR
A0~A8
VIH VIL
ROW ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
COLUMN ADDRESS3
ROW ADDRESS
tWCS W VIH VIL tDS DQ1~DQ16 (INPUTS) VIH VIL
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
tDS
DATA VALID-2
tDH
tDS
tDH
DATA VALID-1
DATA VALID-3
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
21
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Byte Write Cycle (Early Write)
tRAS VIH VIL tCSH tCRP UCAS (or LCAS) VIH VIL tRCD tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
RAS
LCAS (or UCAS)
VIH VIL tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC tCAH tASR
A0~A8
ROW ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
COLUMN ADDRESS3
ROW ADDRESS
tWCS W VIH VIL
tWCH
tWCS
tWCH
tWCS
tWCH
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDS DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) tDH
Hi-Z
tDS
tDH
tDS
tDH
DATA VALID-1
DATA VALID-2
DATA VALID-3
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
22 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS RAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tASR VIH VIL tRAH tASC tCAH tASC tRWL tCAH tCWL tRCD tCAS tCP tPC tCAS tRSH
tRP
tASR
ROW ADDRESS
A0~A8
ROW ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
tRCS VIH VIL tWCH tDZC DQ1~DQ16 (INPUTS) VIH VIL
Hi-Z
tCWL tWP
tRCS tWP
W
tWCH tDH
DATA VALID-1
tDS
tDZC
Hi-Z
tDS
tDH
DATA VALID-2
tCLZ DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z Hi-Z
tCLZ
Hi-Z
tDZO VIH VIL
tOEZ tODD tDZO
tOEZ tODD
tOEH
OE
23
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Fast-Page Mode Byte Write Cycle (Delayed Write)
tRAS VIH VIL tCRP VIH VIL tRCD tCSH tCAS tCP UCAS (or LCAS) tRSH tPC tCAS
tRP
RAS
LCAS (or UCAS)
VIH VIL tASR tRAH tASC tCAH tASC tCAH tRWL tCWL tASR
ROW ADDRESS
A0~A8
VIH VIL
ROW ADDRESS
COLUMN ADDRESS1
COLUMN ADDRESS2
tCWL tRCS tWP W VIH VIL tWCH
tRCS tWP
tWCH
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDZC DQ9~DQ16 VIH (or DQ1~DQ8) (INPUTS) VIL
Hi-Z
Hi-Z
tDS
tDH
DATA VALID-1
tDZC
Hi-Z
tDS
tDH
DATA VALID-2
tCLZ DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z Hi-Z
tCLZ
Hi-Z
tOEZ tDZO VIH VIL tODD tDZO
tOEZ tODD tOEH
OE
24 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Read-Write, Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tASR VIH VIL tRAH tRAD tASC tCAH
COLUMN ADDRESS1
tRP
RAS
tRWL tCAS tPRWC tCP tCAS
tRCD
tASC
tCAH
tCWL
tASR
ROW ADDRESS
A0~A8
ROW ADDRESS
COLUMN ADDRESS2
tAWD tRCS VIH VIL tRWD tDZC DQ1~DQ16 (INPUTS) VIH VIL tAA tCLZ DQ1~DQ16 (OUTPUTS) VOL VOH
Hi-Z
DATA VALID-1
tCWD
tCWL tWP
tAWD tRCS tCWD tWP
W
tCPWD tDS tDH
DATA VALID-1
tDZC
Hi-Z
tDS
tDH
DATA VALID-2
Hi-Z
tCAC
tCAC tAA tCLZ
Hi-Z
DATA VALID-2
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tDZO
tCPA tOEA
tODD tOEZ tOEH
OE
VIH VIL
25
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Byte Read-Write, Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP UCAS (or LCAS) VIH VIL tRCD tCAS tCP tPRWC tCAS
tRP
RAS
tRWL
LCAS (or UCAS)
VIH VIL tASR VIH VIL tRAD tRAH tASC tCAH
COLUMN ADDRESS1
tASC
tCAH
tCWL
tASR
ROW ADDRESS
A0~A8
ROW ADDRESS
COLUMN ADDRESS2
tRCS W VIH VIL
tAWD tCWD
tCWL tWP tRCS
tAWD tCWD
tWP
tRWD
tCPWD
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS)
Hi-Z
Hi-Z
tDS
tDH
DATA VALID-1
tDZC
Hi-Z
tDS
tDH
DATA VALID-2
tCAC tAA tCLZ
tCAC tAA tCLZ
DATA VALID-1
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
Hi-Z
DATA VALID-2
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tDZO
tCPA tOEA
tODD tOEZ
tOEH
OE
VIH VIL
26
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh Cycle *
(Note28)
tRP RAS VIH VIL
tRASS
tRPS
tRPC tRPC tCSR VIH LCAS/UCAS VIL tCPN tASR A0~A8 VIH VIL tRCH VIH VIL tCDD DQ1~DQ16 (INPUTS) VIH VIL tOFF DQ1~DQ16 VOH (OUTPUTS) VOL tOEZ tODD OE VIH VIL
Hi-Z Hi-Z ROW ADDRESS COLUMN ADDRESS
tCHS
tCRP
tRCS
W
27 M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Note 28 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width (tRASS) of RAS signal during self refresh period. 1. Distributed refresh during Read/Write operation (A) Timing Diagram
Read / Write Cycle Self Refresh Cycle Read / Write Cycle
tNSD
tRASS100s
tSND
RAS
last refresh cycle
first refresh cycle
Table 2
Read / Write Cycle CBR distributed refresh RAS only distributed refresh Read / Write Self Refresh tNSD250s tNSD16s Self Refresh Read / Write tSND250s tSND16s
(B) Definition of distributed refresh tREF tREF / 512 tREF / 512
RAS
refresh cycle read/write cycles refresh cycle refresh cycle read/write cycles
Definition of CBR distributed refresh (Including extended refresh) The CBR distributed refresh performs more than 512 constant period (250s max.) CBR cycles within 128 ms. Definition of RAS only distributed refresh All combinations of nine row address signals (A0~A8) are selected during 512 constant period (16s max.) RAS only refresh cycles within 8.2 ms. Note: Hidden refresh may be used instead of CBR refresh. RAS/CAS refresh may be used instead of RAS only refresh. 1.1 CBR distributed refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSD (shown in table 2).
Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within tSND (shown in table 2). 1.2 RAS only distributed refresh Switching from read/write operation to self refresh operation. The time interval tNSD from the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16s. Switching from self refresh operation to read/write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16s.
28
M5M44260CJ,TP-5,-5S : Under development
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
2. Burst refresh during Read/Write operation (A) Timing diagram
Read / Write Self Refresh Read / Write
tNSB
tRASS100s
tSNB
RAS
refresh cycles 511 cycles last refresh Cycles
first refresh cycles
refresh cycles 511 cycles
Table 3
Read / Write Cycle CBR burst refresh RAS only burst refresh Read / Write Self Refresh tNSB8.2ms Self Refresh Read / Write tSNB8.2ms
tNSB+tSNB8.2ms
(B) Definition of burst refresh
8.2ms
RAS
refresh cycles 512 cycles
read/write cycles
Definition of CBR burst refresh The CBR burst refresh performs more than 512 continuous CBR cycles within 8.2 ms. Definition of RAS only burst refresh All combination of nine row address signals (A0~A8) are selected during 512 continuous RAS only refresh cycles within 8.2 ms. 2.1 CBR burst refresh Switching from read/write operation to self refresh operation. The time interval tNSB from the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 8.2 ms. Switching from self refresh operation to read/write operation. The time interval tSNB from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period should be set within 8.2 ms. 2.2 RAS only burst refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB (shown in table 3). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within tSNB (shown in table 3).
29
M5M44260CJ,TP-5,-5S : Under development

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