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19-1134; Rev 0; 10/96
KIT ATION EVALU E AILABL AV
12-Bit, 30Msps, TTL-Output ADC
_____________________________Features
o Monolithic, 12-Bit, 30Msps Converter o On-Chip Track/Hold o 2.0V Analog Input Range o High Input Impedance o 66dB SNR at 1MHz Input o Low Power: 1.1W o 5pF Input Capacitance o TTL-Compatible Outputs
_________________General Description
The MAX1172 analog-to-digital converter (ADC) is a 12-bit monolithic ADC capable of sample rates greater than 30Msps. An on-board input buffer and track/hold function ensure excellent dynamic performance without the need for external components. A 5pF input capacitance minimizes development problems. Logic inputs and outputs are TTL compatible. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is a very low 1.1W with power-supply voltages of +5.0V and -5.2V. The MAX1172 also provides a wide input voltage range of 2.0V. The MAX1172 is available in a 32-lead ceramic sidebrazed package and a 44-lead surface-mount CERQUAD package.
MAX1172
________________Ordering Information
PART TEMP. RANGE 0C to +70C 0C to +70C PIN-PACKAGE 32 Ceramic SB 44 CERQUAD
_________________________Applications
Radar Receivers Professional Video Instrumentation Imaging Digital Communications Digital Spectrum Analyzers
MAX1172CDJ MAX1172CBH
___________________Pin Configurations
D1 D0 N.C. DGND DVCC VEE N.C. AGND N.C. VCC N.C.
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22
TOP VIEW
________________Functional Diagram
VIN
INPUT BUFFER
4-BIT FLASH CONVERTER 4 ERROR CORRECTION, DECODING 12 AND OUTPUT TLL DRIVERS DIGITAL OUTPUT
D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 N.C.
1 2 3 4 5 6 7 8 9 10 11
MAX1172
N.C. VFB VSB VRT1 VRT2 VIN VRT3 VST VFT N.C. VCC
ANALOG GAIN COMPRESSION PROCESSOR
TRACK/ HOLD AMPLIFIERS
ASYNCHRONOUS 8-BIT SAR
8
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
N.C. D12 DGND DVCC N.C. CLK N.C. VEE N.C. AGND N.C.
CERQUAD
12-Bit, 30Msps, TTL-Output ADC MAX1172
ABSOLUTE MAXIMUM RATINGS
VCC .......................................................................................+6V VEE .........................................................................................-6V Analog Input ........................................................VFB VIN VFT VFB, VFT ................................................................. -3.0V, +3.0V Reference Ladder Current ..................................................12mA CLK IN ...................................................................................VCC Digital Outputs.......................................................0mA to -30mA Operating Temperature Range...............................0C to +70C Junction Temperature (Tj)................................................+175C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = 2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 30MHz, 50% clock duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Resolution DC ACCURACY (TA = +25C) Integral Nonlinearity Differential Nonlinearity No Missing Codes ANALOG INPUT Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth Positive Full-Scale Error Negative Full-Scale Error REFERENCE INPUT Reference Ladder Resistance Reference Ladder Tempco TIMING CHARACTERISTICS Maximum Conversion Rate Overvoltage Recovery Time Pipeline Delay (Latency) Output Delay Aperture Delay Time Aperture Jitter Time TA = +25C TA = +25C TA = +25C VI V VI V V V 14 1 5 30 40 20 1 18 MHz ns Clock Cycle ns ns ps-RMS VI V 500 800 0.8 /C 3dB small signal TA = +25C VIN = 0V, TA = +25C VI I I V V V V 100 2.0 30 300 5 120 5.0 5.0 60 V A k pF MHz LSB LSB full scale 250kHz sample rate IV IV I 2.0 0.8 Guaranteed LSB LSB CONDITIONS TEST LEVEL MIN 12 TYP MAX UNITS Bits
2
_______________________________________________________________________________________
12-Bit, 30Msps, TTL-Output ADC
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = 2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 30MHz, 50% clock duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DYNAMIC PERFORMANCE fIN = 500kHz Effective Number of Bits fIN = 1MHz fIN = 3.58MHz fIN = 500kHz Signal-to-Noise Ratio (without Harmonics) fIN = 1MHz fIN = 3.58MHz fIN = 500kHz Harmonic Distortion fIN = 1MHz fIN = 3.58MHz fIN = 500kHz Signal-to-Noise and Distortion fIN = 1MHz fIN = 3.58MHz Spurious-Free Dynamic Range Differential Phase Differential Gain DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Maximum Input Current Low Maximum Input Current High Pulse Width Low (CLK) Pulse Width High (CLK) DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage TA = +25C TA = +25C I I 2.4 0.6 V V TA = +25C TA = +25C V V I I IV IV 0 0 15 15 300 5 5 2.4 4.0 0.8 20 20 V V A A ns ns TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX I IV I IV I IV I IV I IV I IV I IV I IV I IV V V V 63 58 63 58 62 58 63 59 62 58 59 57 60 55 59 55 57 54 10.0 9.8 9.5 66 61 65 60 64 60 65 61 64 60 61 59 62 57 61 57 59 56 74 0.2 0.7 dBc Degrees % dB dB dB Bits CONDITIONS TEST LEVEL MIN TYP MAX UNITS
MAX1172
fIN = 1MHz, TA = +25C fIN = 3.58MHz and 4.35MHz, TA = +25C fIN = 3.58MHz and 4.35MHz, TA = +25C
_______________________________________________________________________________________
3
12-Bit, 30Msps, TTL-Output ADC MAX1172
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = 2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 30MHz, 50% clock duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER POWER-SUPPLY REQUIREMENTS VCC Voltages DVCC -VEE ICC, TA = +25C Currents Power Dissipation Power-Supply Rejection 5V 0.25V, -5.2V 0.25V DICC, TA = TMIN to TMAX -IEE, TA = +25C IV IV IV I IV I VI V 4.75 4.75 -4.95 5.0 5.0 -5.2 135 40 45 1.1 1.0 5.25 5.25 -5.45 150 55 70 1.3 W LSB mA V CONDITIONS TEST LEVEL MIN TYP MAX UNITS
Note 1: Typical thermal impedances (unsoldered, in free air): 32 Ceramic SB: jA = 50C/W 44 CERQUAD: jA = 78C/W, jA at 1m/s airflow = 58C/W, jC = 3.3C/W Use forced-air cooling or heatsinking to maintain Tj 150C.
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests are pulsed; therefore, Tj = TC = TA.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25C. Parameter is guaranteed over specified temperature range.
4
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12-Bit, 30Msps, TTL-Output ADC
__________________________________________Typical Operating Characteristics
(fS = 30Msps, fIN = 1MHz, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY
MAX1170 TOC-01
MAX1172
TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY
MAX1170 TOC-02
SNR, THD, SINAD vs. SAMPLE RATE
MAX1170 TOC-03
80 70 60 SNR (dB) 50 40 30 20 1 10 INPUT FREQUENCY (MHz)
80 70 60 THD (dB) 50 40 30 20
80 70 SNR, THD, SINAD (dB) 60 50 40 30 20 SNR, THD SINAD
100
1
10 INPUT FREQUENCY (MHz)
100
1
10 SAMPLE RATE (Msps)
100
SIGNAL-TO-NOISE AND DISTORTION vs. INPUT FREQUENCY
MAX1170 TOC-04
SPECTRAL RESPONSE
MAX1170 TOC-05
SNR, THD, SINAD vs. TEMPERATURE
MAX1170 TOC-06
80 70 60 50 40 30 20 1 10 0INPUT FREQUENCY (MHz)
0
75
SNR, THD, SINAD (dB)
-30 AMPLITUDE (dB) SINAD (dB)
70 SNR 65 THD 60 SINAD
-60
-90
55 -120 100 0 1 2 3 FREQUENCY (MHz) 4 5
50 -25 0 50 25 TEMPERATURE (C) 75
_______________________________________________________________________________________
5
12-Bit, 30Msps, TTL-Output ADC MAX1172
_________________________________________________________________________Pin Description
PIN NAME Ceramic SB 1, 15 2-13 14 16, 32 17 18, 31 19, 30 20, 29 21 22 23 24 25 26 27 28 -- CERQUAD 14, 41 43, 44, 1-10 13 15, 40 17 19, 39 21, 37 23, 35 25 26 27 28 29 30 31 32 11, 12, 16, 18, 20, 22, 24, 33, 34, 36, 38, 42 DGND D0-D11 D12 DVCC CLK VEE AGND VCC VFT VST VRT3 VIN VRT2 VRT1 VSB VFB N.C. Digital Ground TTL Outputs (D0 = LSB) TTL Output Overrange Bit Digital +5.0V Supply (TTL Outputs) TLL Clock Input -5.2V Supply Analog Ground +5.0V Supply Force for Top of Reference Ladder Sense for Top of Reference Ladder Voltage Reference Tap 3 Analog Input, 2.0V typical Voltage Reference Tap 2 Voltage Reference Tap 1 Sense for Bottom of Reference Ladder Force for Bottom of Reference Ladder No Connection FUNCTION
6
_______________________________________________________________________________________
12-Bit, 30Msps, TTL-Output ADC MAX1172
N+1 N
N+2 tPWH tPWL
CLK tD
OUTPUT DATA
N-2
N-1
DATA VALID N
DATA VALID N+1
Figure 1a. Timing Diagram
CLK tD
OUTPUT DATA
DATA VALID
Figure 1b. Single-Event Clock
Table 1. Timing Parameters
PARAMETER tD tPWH tPWL DESCRIPTION CLK to Data Valid Prop Delay CLK High Pulse Width CLK Low Pulse Width 15 15 MIN TYP 14 MAX 18 300 UNITS ns ns ns
_______________Detailed Description
The MAX1172 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the MAX1172 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria for achieving the optimal device performance.
Power Supplies and Grounding
The MAX1172 requires -5.2V and +5V analog supply voltages. The +5V supply is common to analog VCC and digital DVCC. A ferrite bead in series with each supply line reduces the transient noise injected into the analog VCC. These beads should be connected as close to the device as possible. The connection between the beads and the MAX1172 should not be shared with any other device. Bypass each power-supply pin as close to the device as possible. Use 0.1F for VEE and VCC, and 0.01F for DVCC (chip capacitors are preferred).
7
_______________________________________________________________________________________
12-Bit, 30Msps, TTL-Output ADC MAX1172
CLK (TTL) VIN (2V) +5V + C19 1F 4 2 VIN VOUT 6
R1 100
17 CLK
24 VIN +2.5V + 5 1F 10k 30k C2 0.01F 23 VRT3 C3 0.01F 25 VRT2 C4 0.01F 1 10k 8 3 2 26 VRT1 -5.2V 4 C17 0.01F 6 C16 1F DGND AGND 30k C6 0.01F -2.5V C7 0.01F 28 VFB C5 0.01F 27 VSB C1 0.01F 21 VFT
MAX1172
COARSE ADC 4
D12 14 (OVERRANGE) D11 13 D10 12 (MSB)
IC1 (REF-03)
GND TRIM
R 22 VST 2R ANALOG PRESCALER D9 11 D8 10 DECODING NETWORK DIGITAL OUTPUTS (LSB) D7 9 D6 8 D5 7 D4 6 D3 5 D2 4 D1 3 R SUCCESSIVE INTERPOLATION STAGE N DGND 32 C13 0.01F DGND 1 15 FB D1 C15 C14 10F 10F FB FB D0 2
2R SUCCESSIVE INTERPOLATION STAGE 1
2R
IC2 OP-07
7
2R
+5V C18 0.01F
AGND
AGND
DVCC 29
18
31
19
30
20
16
DVCC
VCC
VCC
VEE
VEE
C8 C10 0.1F 0.1F
C12 0.01F
C9 C11 0.1F 0.1F NOTES: 1) D1 = SCHOTTKY OR HOT CARRIER DIODE 2) FB = FERRITE BEAD, FAIR RIGHT P/N 2743001111, TO BE MOUNTED AS CLOSELY AS POSSIBLE. THE FERRITE BEAD TO ADC CONNECTION SHOULD NOT BE SHARED WITH ANY OTHER DEVICE. 3) C1-C3 = CHIP CAPACITOR (RECOMMENDED) MOUNTED AS CLOSELY TO THE DEVICE'S PIN AS POSSIBLE 4) USE OF A SEPARATE SUPPLY FOR VCC AND DVCC IS NOT RECOMMENDED 5) R1 PROVIDES CURRENT LIMITING TO 45mA -5.2V (ANALOG) +5V (ANALOG)
Figure 2. Typical Interface Circuit
8
_______________________________________________________________________________________
12-Bit, 30Msps, TTL-Output ADC
AGND and DGND are the two grounds available on the MAX1172. These two internal grounds are isolated on the device. The use of ground planes is recommended to achieve optimum device performance. DGND is needed for the DVCC return path (40mA typical) and for the return path for all digital output logic interfaces. AGND and DGND should be separated from each other and connected together only at the device through a ferrite bead. A Schottky or hot carrier diode connected between AGND and VEE is required. The use of separate power supplies between VCC and DVCC is not recommended due to potential power-supply sequencing latchup conditions. Use of the recommended interface circuit shown in Figure 2 will provide optimum device performance for the MAX1172.
MAX1172
VCC
VIN
ANALOG PRESCALER
VFT
VEE
Voltage Reference
The MAX1172 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage reference ladder (+2.5V typical), VFB (-2.5V typical) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800. The +2.5V voltage source for reference VFT must be current limited to 20mA maximum if a different driving circuit is used in place of the recommended reference circuit shown in Figures 2 and 3. In addition, there are five reference ladder taps (VST, VRT1, VRT2, VRT3, and VSB). VST is the sense for the top of the reference ladder (+2.0V), VRT2 is the midpoint of the ladder (0.0V typical), and VSB is the sense for the bottom of the reference ladder (-2.0V). VRT1 and VRT3 are quarter-point ladder taps (+1.0V and -1.0V typical, respectively). The voltages seen at V ST and VSB are the true full-scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5V and -2.5V typical, respectively). VST and VSB can be used to monitor the actual full-scale input voltage of the device. VRT1, VRT2, and VRT3 should not be driven to the expected ideal values, as is commonly done with standard flash converters. A decoupling capacitor of 0.01F connected to AGND from each tap is recommended to minimize high-frequency noise injection. The analog input range will scale proportionally with respect to the reference voltage if a different input
Figure 3. Analog Equivalent Input Circuit
range is required. The maximum scaling factor for device operation is 20% of the recommended reference voltages of VFT and VFB. However, because the MAX1172 is laser trimmed to optimize performance with 2.5V references, its accuracy will degrade if operated beyond a 2% range. An example of a recommended reference driver circuit is shown in Figure 2. IC1 is REF-03, the +2.5V reference with a tolerance of 0.6% or 0.015V. The 10k potentiometer supports an adjustable range of 150mV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3LSB matching between VFT and VFB. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the VFB voltage to the desired level. Adjust R1 and R4 such that VST and VSB are exactly +2.0V and -2.0V, respectively. The following errors are defined: +FS error = top of ladder offset voltage = (+FS - VST) -FS error = bottom of ladder offset voltage = (-FS - VSB) Where the +FS (full scale) input voltage is defined as the output 1LSB above the transition of 1-10 and 1-11, and the -FS input voltage is defined as the output 1LSB below the transition of 0-00 and 0-01.
_______________________________________________________________________________________
9
12-Bit, 30Msps, TTL-Output ADC MAX1172
Analog Input
VIN is the analog input. The full-scale input range will be 80% of the reference voltage or 2V with VFB = -2.5V and VFT = +2.5V. The drive requirements for the analog inputs are minimal compared to those of conventional flash converters, due to the MAX1172's extremely low 5pF input capacitance and high 300k input impedance. For example, for an input signal of 2Vp-p with an input frequency of 10MHz, the peak output current required for the driving circuit is only 628A.
SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE
65 63 SNR (dB) 61 59 57 tPWH DUTY CYCLE = tPWH tPWL
MAX1170 FIG-04
67
Clock Input
The MAX1172 is driven from a single-ended TTL input (CLK). The clock pulse width (t PWH ) must be kept between 15ns and 300ns to ensure proper operation of the internal track/hold amplifier (Figure 1a). When operating the MAX1172 at sampling rates above 3Msps, it is recommended that the clock input duty cycle be kept at 50% to optimize performance (Figure 4). The analog input signal is latched on the rising edge of the CLK. The clock input must be driven from fast TTL logic (VIH 4.5V, tRISE < 6ns). In the event the clock is driven from a high current source, use a 100 (R1, Figure 2) resistor in series to current limit to approximately 45mA.
55 53 51
25 35 45 55 65 75 DUTY CYCLE OF POSITIVE CLOCK PULSE (%)
Figure 4. Signal-to-Noise Ratio vs. Clock Duty Cycle
Overrange Output
The overrange output (D12) is an indication that the analog input signal has exceeded the full-scale input voltage by 1LSB. When this condition occurs, the outputs will switch to logic 1s. All other data outputs are unaffected by this operation. This feature makes it possible to include the MAX1172 in higher resolution systems.
Digital Outputs
The format of the output data (D0-D11) is straight binary (Table 2). The outputs are latched on the rising edge of CLK with a typical propagation delay of 14ns. There is a one clock cycle latency between CLK and the valid output data (Figure 1a). The digital outputs' rise times and fall times are not symmetrical. The rise time's typical propagation delay is 14ns, and the typical fall time is 6ns (Figure 5). The nonsymmetrical rise and fall times create approximately 8ns of invalid data.
Evaluation Board
The MAX1170 evaluation kit (EV kit) is available to aid designers in demonstrating the full performance of the MAX1172 (or of the MAX1170/MAX1171). This board includes a reference circuit, clock driver circuit, output data latches, and on-board reconstruction of the digital data. A separate EV kit manual describing the operation of this board is available. Contact the factory for price and availability.
Table 2. Output Data Information
ANALOG INPUT > +2.0V + 1/2LSB +2.0V - 1LSB 0.0V -2.0V + 1LSB < -2.0V OVERRANGE D10 1 0 0 0 0 OUTPUT CODE D9-D0 1 1 1 111 1111 11 OO 00 00 1 111 OOOO 0000 0000 111O OOOO 000O 0000
(O indicates the flickering bit between logic 0 and 1).
10
______________________________________________________________________________________
tPWL
12-Bit, 30Msps, TTL-Output ADC MAX1172
N N+1
CLK IN
2.4V 6ns typ 3.5V 2.4V (N - 2) 0.8V 0.5V tPD1 14ns typ INVALID DATA (N - 1) tRISE 6ns
DATA OUT (ACTUAL)
INVALID DATA (N)
DATA OUT (EQUIVALENT)
(N - 2)
INVALID DATA
(N - 1)
INVALID DATA
(N - 1)
Figure 5. Digital Output Characteristics
____Pin Configurations (continued)
TOP VIEW
DGND 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11 D10 12 D11 13 D12 14 DGND 15 DVCC 16 32 DVCC 31 VEE 30 AGND
MAX1172
29 VCC 28 VFB 27 VSB 26 VRT1 25 VRT2 24 VIN 23 VRT3 22 VST 21 VFT 20 VCC 19 AGND 18 VEE 17 CLK
Ceramic SB
______________________________________________________________________________________
11
12-Bit, 30Msps, TTL-Output ADC MAX1172
________________________________________________________Package Information
DIM A B C D E F G H I J INCHES MAX MIN 0.099 0.081 0.020 0.016 0.105 0.095 0.050 typ - - 0.040 0.225 0.175 1.620 1.580 0.605 0.585 0.012 0.009 0.620 0.600 MILLIMETERS MIN MAX 2.06 2.51 0.41 0.51 2.41 2.67 - 1.27 1.02 - 4.45 5.72 40.13 41.15 14.86 15.37 0.23 0.30 15.24 15.75
32
1
G A E F I
H
32-PIN SIDEBRAZED PACKAGE
J
C B D
DIM A B C D E F G H
C
D
A
B
INCHES MAX MIN 0.000 0.546 typ 0.694 0.679 0.040 0.038 0.000 0.016 typ 0.000 0.008 typ 0.051 0.027 0.000 0.006 typ 0.140 0.115
MILLIMETERS MIN MAX 14.00 typ - 17.40 17.80 0.98 1.02 0.40 typ - 0.20 typ - 0.70 1.30 0.15 typ - 2.96 3.58
A B
44-PIN CERQUAD
H G
0-5 E F
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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