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| MC74HC174A Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The MC74HC174A is identical in pinout to the LS174. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of six D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active-low. http://onsemi.com MARKING DIAGRAMS 16 16 1 * * * * * * * Output Drive Capability: 10 LSTTL Loads TTL NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 162 FETs or 40.5 Equivalent Gates LOGIC DIAGRAM D0 3 D1 4 DATA INPUTS D2 6 D3 11 D4 13 14 D5 CLOCK 9 PIN 16 = VCC PIN 8 = GND RESET 1 2 Q0 5 Q1 7 Q2 10 Q3 12 Q4 15 Q5 PDIP-16 N SUFFIX CASE 648 MC74HC174AN AWLYYWW 1 16 16 1 SO-16 D SUFFIX CASE 751B 1 A WL YY WW HC174A AWLYWW = Assembly Location = Wafer Lot = Year = Work Week NONINVERTING OUTPUTS PIN ASSIGNMENT RESET Q0 D0 D1 Q1 D2 Q2 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q5 D5 D4 Q4 D3 Q3 CLOCK FUNCTION TABLE Inputs Reset L H H H H Clock X D X H L X X Output Q L H L No Change No Change Value 40.5 1.5 5.0 Units ea. ns L ORDERING INFORMATION Device MC74HC174AN MC74HC174AD MC74HC174ADR2 Package PDIP-16 SOIC-16 SOIC-16 Shipping 2000 / Box 48 / Rail 2500 / Reel (c) Semiconductor Components Industries, LLC, 2000 March, 2000 - Rev. 7 II IIIIIIIIIIIII II III I IIIIIIIIIIIII IIIIIIIIIIIII II IIIIIIIIIIIII IIIIIIIIIIII II II I I IIIIIIIIIIIII IIIIIIIIIIIII II I II IIIIIIIIIIIII II IIIIIIIIIIII II IIIIIIIIIIIII IIIIIIIIIII I Design Criteria Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product W pJ .0075 *Equivalent to a two-input NAND gate. 1 Publication Order Number: MC74HC174A/D MC74HC174A IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIII IIIIIIIIIIIIIIIIIIIII I I II II I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I I I III I I I I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I II I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIII I I I I IIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I III II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 -0.5 to VCC + 0.5 20 25 50 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature Plastic DIP SOIC Package mW Tstg TL - 65 to + 150 260 _C _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 0 0 + 125 1000 500 400 _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VIH Parameter Test Conditions VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 - 55 to 25_C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 v 85_C v 125_C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 Unit V Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A V VOH Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A v v v v v v V Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA 3.98 5.48 0.1 0.1 0.1 3.84 5.34 0.1 0.1 0.1 VOL Maximum Low-Level Output Voltage V 0.26 0.26 0.33 0.33 http://onsemi.com 2 IIIII IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIII IIII II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIII III IIII II IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIII IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIII IIII IIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIII IIII IIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I II IIIIIIIIII IIIIIIIIIIIIIIIIIII IIII IIII IIII IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I I I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I NOTES: 1. Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + SICC. IIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol ICC Iin Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Parameter Vin = VCC or GND Iout = 0 A Vin = VCC or GND Test Conditions AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol Symbol tr, tf trec tsu tw tw th tPLH tPHL tPLH tPHL tTLH tTHL fmax CPD Cin Maximum Input Rise and Fall Times Minimum Pulse Width, Reset Minimum Pulse Width, Clock Minimum Recovery Time, Reset Inactive to Clock Minimum Hold Time, Clock to Data Minimum Setup Time, Data to Clock Power Dissipation Capacitance (Per Enabled Output)* Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Propagation Delay, Reset to Q (Figures 2 and 4) Maximum Propagation Delay, Clock to Q (Figures 1 and 4) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Parameter Parameter http://onsemi.com Fig. 1 2 1 2 3 3 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 MC74HC174A 3 - 55 to 25_C Min 5.0 5.0 5.0 5.0 5.0 5.0 50 10 9.0 75 15 13 75 15 13 VCC V VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 6.0 6.0 1000 500 400 Max - 55 to 25_C - 55 to 25_C Guaranteed Limit Typical @ 25C, VCC = 5.0 V 0.1 110 21 19 110 22 19 6.0 30 35 4.0 10 75 15 13 Min 5.0 5.0 5.0 5.0 5.0 5.0 95 19 16 95 19 16 65 13 11 v 85_C Guaranteed Limit Guaranteed Limit 1000 500 400 Max v 85_C v 125_C v 85_C v 125_C 1.0 140 28 24 140 28 24 4.8 24 28 10 95 19 16 40 62 Min 110 22 19 110 22 19 5.0 5.0 5.0 5.0 5.0 5.0 75 15 13 v 125_C 1.0 160 32 27 165 33 28 160 110 22 19 4.0 20 24 10 1000 500 400 Max MHz Unit Unit Unit A A pF pF ns ns ns ns ns ns ns ns ns MC74HC174A EXPANDED LOGIC DIAGRAM CLOCK D0 RESET 9 3 1 C D1 4 D R C D2 6 D Q R C D3 11 D R C D4 13 D R C D5 14 D Q R D C Q R 2 Q0 Q 5 Q1 7 Q2 Q 10 Q3 Q 12 Q4 15 Q5 SWITCHING WAVEFORMS tr 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL tPHL Q trec 50% CLOCK GND VCC tf VCC RESET GND tPHL tw 50% CLOCK VCC GND Figure 1. Figure 2. TEST POINT VALID VCC DATA 50% GND tsu CLOCK 50% GND th VCC *Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT CL* Figure 3. Figure 4. Test Circuit http://onsemi.com 4 MC74HC174A PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE R -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 10 0 10 0 0.020 0.040 1.01 0.51 B 1 8 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 -B - 1 8 P 8 PL 0.25 (0.010) M B M G F K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S http://onsemi.com 5 MC74HC174A Notes http://onsemi.com 6 MC74HC174A Notes http://onsemi.com 7 MC74HC174A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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